CN101500166A - Collecting, encoding and compressing system for video stream - Google Patents
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Abstract
The invention relates to a collecting, encoding and compressing system of a video stream, comprising the following steps: an collecting encoding unit collects a video image in a way of adjustable image size and, then obtains an original video stream data after encoding and sends the original video stream data to a compressing unit at a set frame rate; the compressing unit receives the original video stream data sent by the collecting encoding unit in a way of adjustable frame rate, then compresses stream data according to MPEG4 compressing standard and temporarily stores the compressed data in a register in the compressing unit; and a microcontroller is used for initializing all the parameters of the collecting encoding unit and the compressing unit, the register in the compressing unit is mapped as an outer register of the microcontroller in a hardware wiring way, and the compressed video stream data stored in the register is directly read by the microcontroller and sent out. The invention can realize small size, low frame rate and high compression rate, meets the user need of higher image quality by dynamically adjusting parameters, and has strong scalability and flexibility.
Description
Technical field
The present invention relates to field of video monitoring, be particularly suitable for field of video monitoring, be specifically related to a kind of collection, coding and compressibility of video flowing based on the low bandwidth radio communication technology.
Background technology
Along with the continuous development of multimedia technology, wireless communication technology and sensor technology, the multimedia wireless sensor network technology has caused social common concern.With video, audio frequency, image, text is the multimedia application of basic element, in such as numerous areas such as battlefield visual control, environmental monitoring, security monitoring, traffic monitoring, Smart Home, medical treatment ﹠ healths, has broad application prospects.
The wireless video flow monitoring is the important branch that multimedia wireless sensor network is used.The Video stream information of remote shooting is transferred to service end by wireless mode, for effective monitoring provides visual information intuitively.The major advantage of wireless video flow monitoring is: radio communication has been removed the trouble of wiring from the one hand; Video flowing has not only brought intuitive on the other hand, and also can obtain than the more multidate information of still image.Therefore, the wireless video streaming supervisory control system has obtained unprecedented development.At present to those service ends and monitored end distance from nearer application scenario because transmission range is near, the wireless transmission of single-hop just is enough to satisfy the demand.Such wireless video streaming supervisory control system has occupied the staple market of wireless video flow monitoring.
Yet,, therefore directly limited transmission range, thereby made the remote video stream supervisory control system be faced with great challenge because the world and domestic Wireless Management Committee all limit the transmitting power of civilian radio band.Adopt simple point-to-point wireless transmission can not satisfy the needs of remote monitoring.The more excellent long-distance video flow monitoring solution of cost performance is called in market.
In recent years, the development of wireless sensor network technology makes the wireless video streaming supervisory control system face new opportunity.By the wireless multi-hop host-host protocol, the long-distance video stream information can by hop-by-hop transfer to service end.Moreover, wireless sensor network also gives video monitoring more wide application space, for example, by the fusion treatment to multisource video information, can realize the three-dimensional reconstruction to monitoring scene visual information.
With regard to existing wireless sensor network technology level, wireless video monitoring based on wireless sensor network technology may make a breakthrough in the constraint of transmission range, but its prerequisite is to solve following two challenges: the one, even video flowing is through after effectively compressing, still there are the bigger characteristics of data traffic, the 2nd, the effective bandwidth of wireless transmission itself is extremely limited.These two problems are tangled mutually.Bigger data volume has not only been aggravated the pressure of wireless transmission on the one hand, and disturbs the effective bandwidth that has further limited network between the frequent stream that transmission brought.Limited on the other hand transmission bandwidth makes a large amount of video datas get clogged, thereby the storage capacity of system has been proposed more strict requirement.This is two key challenge that present video wireless sensor network technology is faced.
At these two key challenge, can correspondingly be optimized remote wireless video flow monitoring system from two different approach, specifically comprise: (1) improves the bandwidth ability of wireless transmission.This can solve from the angle of the physical layer of wireless protocols, MAC (Media Access Control) layer, network layer and cross-layer optimizing.But because these methods still stay in the angle of research at present mostly, therefore unripe relatively complete commercial solution is not adopted widely.Generally adopt other bigger wireless solutions of transmission bandwidth on the engineering at present, as IEEE802.11, general packet radio service gprs etc.These schemes can not be formed complicated digital communication network usually, and mean higher cost and power consumption; (2) reduce the data traffic of video flowing, this approach is in a kind of feasible program that does not improve under the hardware cost prerequisite.
In order to reduce the data traffic of video flowing, at present, MPEG (the MovingPicture Experts Group) compression standards (soft compression or hard compress mode) that adopt compress video data more on the engineering.Yet this compression standard can not be realized the effective compression to the interframe redundant information, and the compression ratio of image can only reach tens times.What is more important: existing hard compression chip often has clear and definite requirement (for example data of 25 frames/second PAL, 30 frames/second NTSC form) to the frame rate of system and image resolution ratio, thereby is unfavorable for reducing the data volume of video flowing.
Summary of the invention
The collection, coding and the compressibility that the purpose of this invention is to provide a kind of video flowing.
For achieving the above object, the present invention adopts following technical scheme:
A kind of collection of video flowing, coding and compressibility comprise:
Video image is gathered in the adjustable mode of picture size in the capturing and coding unit, obtains the original video flow data behind the coding, and the original video flow data is sent to compression unit to set frame rate;
Compression unit receives the original video flow data that the capturing and coding unit sends with way of adjustable frame rate, with the MPEG4 compression standard it is compressed the temporary register in compression unit in back;
Microcontroller, the picture size, coded format, the setting frame rate that are used for initialization capturing and coding unit, and the received frame speed of initialization compression unit, is the chip external memory of microcontroller with the hardware wire laying mode with the register mappings in the compression unit, and microcontroller directly reads the video stream data after the compression of register memory storage and sends.
Preferably, this system also comprises the multimode power supply, is used to the each several part power supply except that microcontroller, and described multimode power supply cuts off the power supply of each several part before microcontroller enters sleep pattern under the control of microcontroller
Preferably, this system also comprises the external hardware data buffer, and described external hardware data buffer is connected with compression unit, the video stream data when being used for register in compression unit and overflowing after the store compressed.
Preferably, encode in the YUV4:2:2 mode in described capturing and coding unit, communicates by letter with compression unit with external sync mode in described capturing and coding unit, and the video stream data behind the coding is sent to compression unit
Preferably, the capturing and coding unit is that model is the video capture processor of OV7660.
Preferably, described compression unit is that model is the video stream compression chip of ML86410.
Preferably, described microcontroller employing model is the single-chip microcomputer of Atmega128L.
Preferably, the external data read-write control line signal of described Chip Microcomputer A tmega128L is directly connected to respectively on the read-write pin of video stream compression chip ML86410.
Preferably, described multimode power supply employing model is a NCP551 series three-terminal voltage-stabilizing chip.
Preferably, described external hardware data buffer is that model is the buffer of MD56V62320, and described microcontroller is connected with the address wire of buffer MD56V62320 is corresponding with data wire.
Utilize collection, coding and the compressibility of video flowing provided by the invention, have following beneficial effect:
1) can realize small size, low frame rate and high compression rate, be a video integrated solution very low to the transmission bandwidth requirement;
2) the present invention also can pass through dynamically-adjusting parameter, satisfies the user to the more requirement of high image quality, has very strong scalability and flexibility;
3) can be applicable to all kinds of low-power consumption, low-cost field of video monitoring, as service robot, intelligent toy, intelligent transportation, automotive electronics, health supervision, tele-medicine, military technology etc., be particularly useful for low bandwidth radio transmission occasion, for example based on the application of ZigBee.
Description of drawings
Fig. 1 is collection, coding and the compressibility block diagram of video flowing of the present invention;
Fig. 2 A, Fig. 2 B are the interface connection layout between video acquisition and coding chip OV7660 and the video compression chip ML86410 in the embodiment of the invention;
Fig. 3 is the interface connection layout between video compression chip ML86410 and the microcontroller Atmega128L in the embodiment of the invention;
Fig. 4 A, Fig. 4 B are the interface connection layout between video compression chip ML86410 and the external data buffer MD56V62320 in the embodiment of the invention;
Embodiment
Collection, coding and the compressibility of the video flowing that the present invention proposes are described as follows in conjunction with the accompanying drawings and embodiments.
The present invention proposes a kind of video flowing collection, coding and compressibility that is suitable for low bandwidth from reducing the angle of video stream data amount.Its guiding theory is: (1) adopts video stream compression standard MPEG4, to improve data compression rate; (2) satisfying under the prerequisite of picture quality, the video data behind the adjustment capturing and coding is to the frame rate of compression unit transmission; (3) under the prerequisite of meeting consumers' demand, reduce picture size.They all can play the purpose that reduces the video stream data amount, thereby make the present invention be applicable to the occasion of a low bandwidth radio territory net.In addition, in order further to reduce power consumption, adopt the multimode voltage control method further to reduce power consumption.
As shown in Figure 1, collection, coding and the compressibility of the video flowing that the present invention proposes comprise: the capturing and coding unit, gather video image in the adjustable mode of picture size, obtain the original video flow data behind the coding, the original video flow data is sent to compression unit to set frame rate; Compression unit receives the original video flow data that the capturing and coding unit sends with way of adjustable frame rate, with the MPEG4 compression standard it is compressed the temporary register in compression unit in back; The multimode power supply is used to the each several part power supply except that microcontroller, and the multimode power supply cuts off the power supply of each several part before microcontroller enters sleep pattern under the control of microcontroller; The external hardware data buffer, the external hardware data buffer is connected with compression unit, the video stream data when being used for register in compression unit and overflowing after the store compressed; Microcontroller, the picture size, coded format, the setting frame rate that are used for initialization capturing and coding unit, and the received frame speed of initialization compression unit, is the chip external memory of microcontroller with the hardware wire laying mode with the register mappings in the compression unit, and microcontroller directly reads the video stream data after the compression of register memory storage and sends by serial ports.Encoding in the YUV4:2:2 mode in the capturing and coding unit, communicates by letter with compression unit with external sync mode in the capturing and coding unit, and the video stream data behind the coding is sent to compression unit.
After tested, be about about the 1k byte (QVGA form, 1 frame/second speed) in data volume under the bright light environments according to the output of the designed video flowing of this Integrated Solution, can on the 10 ZigBee networks of jumping (employing CC2430 chip, Z-stack protocol stack), reach stable transfer.
Embodiment
Compression unit is for adopting the hard compression chip ML86410 of video of MPEG4 video stream compression standard in the present embodiment, and this chip supports single video stream compression and frame rate dynamically to adjust; The capturing and coding unit adopts the adjustable cmos image acquisition chip OV7660 of picture size; To the high speed address Design of Signal between hard compression chip ML86410 of video and external hardware data buffer source terminal impedance match circuit; Adopted the multimode voltage control method that the different parts of system are powered the power consumption when further having reduced device free.
Present embodiment is a core with MPEG4 video compression chip ML86410, its links to each other with 8 parallel-by-bit buses on the one hand and between video acquisition and the coding CMOS chip OV7660, to link to each other with microcontroller Atmega128L (be that ML86410 no longer is the peripheral hardware of Atmega128L to mode by hardware address mapping on the other hand, and become its external data memory, thereby available access instruction is directly visited).ML86410 receives the original video stream information that transports from OV7660 with external sync mode, after compression, automatically the information cache after the compression to register (when register overflows, be buffered to the external hardware data buffer, this external hardware data buffer is fully by the ML86410 hardware management) in, and the flag bit in its status register of time update.Microcontroller is known the full state of sky of register and external data memory by inquiry mode, delivers to serial ports output after reading corresponding data.Microcontroller is also controlled the power supply that multi-modal voltage comes each parts of management system, so that when device free, in time closes unnecessary power supply, and self switches to sleep state, reaches the purpose that reduces the whole system power consumption.
Provide the specific implementation of each several part below.
1) compression unit
Lectotype selection has directly determined the realizability of design object.Owing to will realize to the high efficiency of compression of Video stream information with to the support of small size video image, so the core of this programme is the selection to the video stream compression chip.The ML86410 chip is the product of Japanese OKI company, not only can support CIF (352 * 288), VGA (640 * 480), this class generic video picture format of PAL (720 * 576), NTSC (720 * 480), and can support the normal video image of QCIF (176 * 144), QVGA (320 * 240) and so on reduced size, this is favourable to reducing amount of bandwidth.In addition, it can be provided with the frame-skipping mode, and the frame rate scope was 0～30 frame/second, and this has further supported the requirement of low bandwidth.In addition, ML86410 has considered the difference between the input and output speed, therefore support that from hardware (heap(ed) capacity is 64MB to an external sync dynamic memory SDRAM hardware data buffer, bus frequency is 81MHZ), the existence of external hardware buffer has greatly alleviated the requirement to the processor response speed.ML86410 is that the ideal of this programme is selected.
2) capturing and coding unit
Video acquisition and encoding function mostly are integrated in a CMOS (the ComplementaryMetal Oxide Semiconductor) camera chip at present, and kind is a lot, the wide range of selection.The choice criteria of present embodiment is that greatest frame rate was not higher than for 30 frame/seconds, and certainly under the prerequisite of considering cost, if can directly support the small size video image of QCIF, QVGA and so on, nature can save the workload of many software programming and debugging.OV7660 is the product of U.S. OmniVision company, and it supports the outer synchronous output of YUV4:2:2 form, and energy and ML86410 be interface easily.In addition, it also directly supports QCIF and QVGA video image format, adopts small encapsulation, also helps reducing equipment size, thereby is a well selection.Though there are up to a hundred registers OV7660 inside, be the external synchronization signal of exportable QVGA form under its back default configuration that powers on, this function is that benifit is arranged very much for getting rid of possible hardware and software fault of later stage.
3) microcontroller
For the selection of microcontroller, one side makes every effort to reduce cost, and is convenient with the selected chip interface in outside on the other hand, especially will support the addressing system of the external data memory of 16 bit address/8 bit data.In addition, preferably can directly support I
2C (Inter-Integrated Circuit) serial line interface is with the software overhead between simplification and the video acquisition OV7660.In conjunction with the requirement to cost, present embodiment is finally selected 8 Chip Microcomputer A tmega128L of atmel corp, and actual effect finds, can also the lower chip of the same type of alternative costs, and as Atmega32 etc., with further cost squeeze.
4) multimode power supply
For the selection of power supply circuits, remove needed all voltages of taking into account system each several part (except the microprocessor required voltage), be specially the various voltage of 1.5V, 1.8V, 2.5V and 3.3V, also want to control the work of every part voltage module.Before microcontroller is entering sleep pattern, can control the multimode power supply and quit work, thereby the power supply supply of other parts of cut-out system reaches purpose of power saving.Present embodiment has adopted NCP551 series three terminal regulator chip, and these chips have one to enable to control pin, can satisfy the requirement of present embodiment.
Microcontroller sends the used serial ports part of data simple fixation relatively, and present embodiment adopts MAX3232 as interface chip, and this part circuit is simple relatively, does not do here and gives unnecessary details.
4) interface section
Fig. 2 is the interface connection layout between video acquisition and coding chip OV7660 and the MPEG4 video compression chip ML86410.YUV4:2:2 data format with 8 between them communicates, and audio video synchronization adopts external sync mode.YUVD0～YUVD7 is 8 a data bus connection among the figure, and HSYNC is a horizontal-drive signal, and VSYNC is a vertical synchronizing signal, is used to provide frame synchronization and line synchronizing signal.
Video acquisition is relative simple with interface between coding chip OV7660 and the microcontroller Atmega128L, passes through I between them
2The C bus links to each other, in addition, for the sleep of control of video collection and coding chip OV7660 with reset, (wherein: the OVPWD signal is used to control OV7660 and enters sleep state also to be provided with OVPWD and OVRST signal respectively, the OVRST signal is used to control OV7660 and resets), and link to each other with microcontroller Atmega128L.
Fig. 3 is the interface connection layout between MPEG4 video compression chip ML86410 and the microcontroller Atmega128L.In order to reduce the burden of software, this programme adopts the hard wire mode register mappings among the ML86410 to be become the external data memory of ATMEGA128, thereby can directly obtain video stream data after the compression by the forms data reading command, save loaded down with trivial details sequencing control read-write.Among the figure, all register addresss of ML86410 are limited in the scope of 0x3000～0x3242, and this finishes by the hardware decoding circuit of outside fully.Owing to used 16 bit address and the multiplexing mode of 8 bit data bus, therefore adopted the 74H573 latch to latch least-significant byte address (latch signal is controlled by the ale signal of Atmega128L).On the read-write control pin XREN and XWEN that the external data read-write control line Rd of Atmega128L and Wr signal are directly connected to ML86410.Such connection mode promptly becomes the internal register of ML86410 the external data storage unit of microcontroller Atmega128L.
Fig. 4 is the interface connection layout between MPEG4 video compression chip ML86410 and the external data buffer MD56V62320.This circuit is the external hardware data buffer that ML86410 is provided with in order to prevent overflowing of internal register.The hardware queue administrative unit of ML86410 chip internal manages this external data buffer.The connection relative fixed of this circuit only needs corresponding linking to each other of address and data/address bus got final product.But because the frequency of address signal is up to 81MHZ, so impedance matching circuit is absolutely necessary.This programme has adopted source terminal impedance matching process to the address bus part of this partial circuit.Here, according to the routine agreement, address wire all is designed to 50 ohm characteristic impedance.
It more than is the hardware components of this programme.Owing to when design hardware, taken into full account the possible expense of software, so the design of software section is simple relatively.Here its execution mode being done one simply introduces.
Software section comprises initialization module and two parts of video compression data read module.Initialization module is specifically responsible for: start the work of multimode power supply each several part, the related hardware and the interface of initialization microcontroller self, every setting of initialization OV7660 and ML86410.
Specifically being provided with of ML86410 is as follows:
WriteML86410 (INTMSK, 0 x fc); // only allow data ready and data read complete to interrupt
WriteML86410 (INTSTS, 0 X 08); All interrupt flag bits of // removing
WriteML86410 (BUSIFCNFG, 0 X 0); // outside DRAM highway width and column address figure place be set
WriteML86410 (INIMAGE, 0 X 66); // picture format QVGA (320*240)
writeML86410(VSTART，0?X?00)；
WriteML86410 (HSTART, 0 x 00); // effective coverage of image is set
WriteML86410 (IMGCPTMODE, 0 X 3e); // External synchronization mode is jumped on the clock along effective
writeML86410(ENCPROFILE，0?X?30)；
WriteML86410 (CODINGTYPE, 0 X 01); // compression standard is MPEG4
WriteML86410 (RATECNTLTYPE, 0 x 02); The setting of // frame rate
WriteML86410 (INTRAREFRESHRATE, 0 x 0a); //IPPP mode
writeML86410(INTRAQUANT，0?x?04)；
WriteML86410 (INTERQUANT, 0 x 04); The setting of // image compression quality
WriteML86410 (STRMACCSIZ, MACSIZE); The setting of // subframe lengths
For OV7660, only picture format need be set is that QVGA gets final product work, certainly also can be according to the setting of the requirement of picture quality being adjusted related register.
The Frame that the video compression data read module of microcontroller at first reads the ML86410 register arrives indicating bit, if truly have Frame to arrive, then frame data is divided into a plurality of subframes and progressively reads in, and sends on the serial ports subsequently.Kernel program is explained as follows:
while(1){
Tempt=readML86410 (INTSTS); // read frame data whether to arrive sign
while((tempt&0?x?01)＝＝0)
Tempt=readML86410 (INTSTS); // read repeatedly, arrive until frame data
WriteML86410 (INTsTs, 0X01); This sign of // removing
11＝(uint32_t)readML86410(STRMSIZI)；
1h＝(uint32_t)readML86410(STRMSIZ1+0?x?01)；
h1＝(uint32_t)((readML86410(STRMSIZ2))&0?x?0f)；
Framesize=(((h1＜＜8)+1h)＜＜8)+11; // read and calculate the length of frame data
readsize＝0；
while(readsize<framesize){
tempt＝readML86410(DMACNTL)；
while((tempt&0?x?01)＝＝0)
Tempt=readML86410 (DMACNTL); // wait for that the DREQ signal is effective
for(uint8_t?i＝0；i<macpacketsize；i++，readsize++){
tempt＝readML86410(STRMDATA)；
if(enqueue(tempt))
UartDebug_txQueue (); // advance team's success, trigger serial ports and send
else?while(！enqueue(tempt))
UartDebug_txQueue (); // queue full then triggers sending at once
}
writeML86410(DMACNTL，0X10)；
tempt＝readML86410(DMACNTL)；
while(tempt&0?x?01)
tempt＝readML86410(DMACNTL)；
WriteML86410 (DMACNTL, 0 X 00); // run through subframe, put the DACK signal and once jump the edge down
} // to this runs through all data in the frame
tempt＝readML86410(INTSTS)；
while((tempt&0x02)！＝0?X?02)
tempt＝readML86410(INTSTS)；
WriteML86410 (INTSTS, 0 X 02); // removing one-frame data read complete interrupt identification
Kernel software partly is reading the video compression data among the ML86410.Here be provided with a serial ports formation and come the unbalanced problem of speed that exists between buffered serial port parts and the compression member.
Above execution mode only is used to illustrate the present invention; and be not limitation of the present invention; the those of ordinary skill in relevant technologies field; under the situation that does not break away from the spirit and scope of the present invention; can also make various variations and modification; therefore all technical schemes that are equal to also belong to category of the present invention, and scope of patent protection of the present invention should be defined by the claims.
Claims (10)
1, a kind of collection of video flowing, coding and compressibility is characterized in that, comprising:
Video image is gathered in the adjustable mode of picture size in the capturing and coding unit, obtains the original video flow data behind the coding, and the original video flow data is sent to compression unit to set frame rate;
Compression unit receives the original video flow data that the capturing and coding unit sends with way of adjustable frame rate, with the MPEG4 compression standard it is compressed the temporary register in compression unit in back;
Microcontroller, the picture size, coded format, the setting frame rate that are used for initialization capturing and coding unit, and the received frame speed of initialization compression unit, is the chip external memory of microcontroller with the hardware wire laying mode with the register mappings in the compression unit, and microcontroller directly reads the video stream data after the compression of register memory storage and sends.
2, system according to claim 1, it is characterized in that this system also comprises the multimode power supply, be used to the each several part power supply except that microcontroller, described multimode power supply cuts off the power supply of each several part before microcontroller enters sleep pattern under the control of microcontroller.
3, system according to claim 1 and 2, it is characterized in that, this system also comprises the external hardware data buffer, and described external hardware data buffer is connected with compression unit, the video stream data when being used for register in compression unit and overflowing after the store compressed.
4, system according to claim 1 and 2 is characterized in that, encodes in the YUV4:2:2 mode in described capturing and coding unit, communicates by letter with compression unit with external sync mode in described capturing and coding unit, and the video stream data behind the coding is sent to compression unit.
5, system according to claim 1 and 2 is characterized in that, the capturing and coding unit is that model is the video capture processor of OV7660.
6, system according to claim 1 and 2 is characterized in that, described compression unit is that model is the video stream compression chip of ML86410.
7, system according to claim 6 is characterized in that, it is the single-chip microcomputer of Atmega128L that described microcontroller adopts model.
8, system according to claim 7 is characterized in that, the external data read-write control line signal of described Chip Microcomputer A tmega128L is directly connected to respectively on the read-write pin of video stream compression chip ML86410.
9, system according to claim 2 is characterized in that, it is NCP551 series three-terminal voltage-stabilizing chip that described multimode power supply adopts model.
10, system according to claim 3 is characterized in that, described external hardware data buffer is that model is the buffer of MD56V62320, and described microcontroller is connected with the address wire of buffer MD56V62320 is corresponding with data wire.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105472442A (en) * | 2015-12-01 | 2016-04-06 | 上海交通大学 | Out-chip buffer compression system for superhigh-definition frame rate up-conversion |
| WO2016078379A1 (en) * | 2014-11-17 | 2016-05-26 | 华为技术有限公司 | Method and device for compressing stream data |
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| WO2016078379A1 (en) * | 2014-11-17 | 2016-05-26 | 华为技术有限公司 | Method and device for compressing stream data |
| CN105680868A (en) * | 2014-11-17 | 2016-06-15 | 华为技术有限公司 | Method and equipment for compressing streaming data |
| US9768801B1 (en) | 2014-11-17 | 2017-09-19 | Huawei Technologies Co., Ltd. | Method and device for compressing flow data |
| US10218381B2 (en) | 2014-11-17 | 2019-02-26 | Huawei Technologies Co., Ltd. | Method and device for compressing flow data |
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