CN110389904A - The storage equipment of FTL table with compression - Google Patents
The storage equipment of FTL table with compression Download PDFInfo
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- CN110389904A CN110389904A CN201810360299.XA CN201810360299A CN110389904A CN 110389904 A CN110389904 A CN 110389904A CN 201810360299 A CN201810360299 A CN 201810360299A CN 110389904 A CN110389904 A CN 110389904A
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- 230000006835 compression Effects 0.000 title abstract description 6
- 238000007906 compression Methods 0.000 title abstract description 6
- 238000012545 processing Methods 0.000 claims description 74
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1009—Address translation using page tables, e.g. page table structures
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Abstract
This application involves solid storage devices, more particularly to the FTL table for using compression in solid storage device, the application from external memory by moving the memory access unit for accommodating FTL entry to caching, the storage unit for accommodating FTL entry is moved from the memory access unit in caching to utilize FTL entry, it realizes and utilizes the boundary alignment by storage unit by memory access unit, the boundary of FTL entry is not always aligned in the purpose of the storage FTL entry of the form compression on the boundary of storage unit, to achieve the effect that the space for having saved the storage equipment of FTL table occupancy.
Description
Technical field
This application involves solid storage devices, and in particular to the FTL table of compression is used in solid storage device.
Background technique
Fig. 1 illustrates the block diagram of the solid storage device of the prior art.Solid storage device 102 is coupled with host, uses
In providing storage capacity for host.Host can be coupled in several ways between solid storage device 102, coupled modes packet
It includes but is not limited by such as SATA (Serial Advanced Technology Attachment, serial advanced technology attachment
Part), SCSI (Small Computer System Interface, small computer system interface), SAS (Serial
Attached SCSI, Serial Attached SCSI (SAS)), IDE (Integrated Drive Electronics, integrated drive electronics),
USB (Universal Serial Bus, universal serial bus), PCIE (Peripheral Component Interconnect
Express, PCIe, high speed peripheral component interconnection), NVMe (NVM Express, high speed non-volatile memory), Ethernet, optical fiber it is logical
Road, cordless communication network etc. connect host and solid storage device 102.Host, which can be, to be set through the above way with storage
The standby information processing equipment communicated, for example, personal computer, tablet computer, server, portable computer, network exchange
Machine, router, cellular phone, personal digital assistant etc..Storing equipment 102 includes interface 103, control unit 104, one or more
A NVM chip 105 and DRAM (Dynamic Random Access Memory, dynamic RAM) 110.
Nand flash memory, phase transition storage, FeRAM (Ferroelectric RAM, ferroelectric memory), MRAM (Magnetic
Random Access Memory, magnetoresistive memory), RRAM (Resistive Random Access Memory, resistance-change memory
Device) etc. be common NVM.
Interface 103 can be adapted to for example, by the side such as SATA, IDE, USB, PCIE, NVMe, SAS, Ethernet, optical-fibre channel
Formula and host exchanging data.
Control unit 104 is used to control the data transmission between interface 103, NVM chip 105 and DRAM 110, also
For storage management, host logical address to flash memory physical address map, erasure balance, bad block management etc..Control unit 104 can
It is realized by the various ways of software, hardware, firmware or combinations thereof, for example, control unit 104 can be FPGA (Field-
Programmable gate array, field programmable gate array), ASIC (Application Specific
Integrated Circuit, application specific integrated circuit) or a combination thereof form.Control unit 104 also may include place
Device or controller are managed, software is executed in processor or controller and carrys out the hardware of manipulation and control component 104 to handle IO
(Input/Output) it orders.Control unit 104 is also coupled to DRAM 110, and may have access to the data of DRAM 110.In
DRAM can store the data of the I/O command of FTL table and/or caching.
Control unit 104 includes flash interface controller (or being Media Interface Connector controller, flash memory channel controller), is dodged
It deposits interface controller and is coupled to NVM chip 105, and sent out in a manner of the interface protocol to follow NVM chip 105 to NVM chip 105
It orders out, to operate NVM chip 105, and receives the command execution results exported from NVM chip 105.Known NVM chip connects
Mouth agreement includes " Toggle ", " ONFI " etc..
In solid storage device, safeguarded using FTL (Flash Translation Layer, flash translation layer (FTL)) from
Map information of the logical address to physical address.Logical address constitutes the solid-state that the upper layer software (applications)s such as operating system are perceived and deposits
Store up the memory space of equipment.Physical address is the address for accessing the physical memory cell of solid storage device.In related skill
Also implement address of cache using intermediate address form in art.Such as logical address is mapped as intermediate address, and then will be intermediate
Address is further mapped as physical address.
The table structure for storing the map information from logical address to physical address is referred to as FTL table.FTL table is that solid-state is deposited
Store up the important metadata in equipment.The data item of usual FTL table has recorded the ground in solid storage device as unit of data page
Location mapping relations.
FTL table includes multiple FTL entries (or list item).In one case, one is had recorded in each FTL entry to patrol
Collect the corresponding relationship of page address and a Physical Page.In another case, continuously multiple patrol is had recorded in each FTL entry
Collect the corresponding relationship of page address and continuous multiple Physical Page.In still another case, logical block is had recorded in each FTL entry
The corresponding relationship of address and physical block address.In the case that still another, logical block address and physical block are recorded in FTL entry
The mapping relations and/or logical page address of address and the mapping relations of physical page address.
In " DFTL:A Flash Translation Layer Employing Demand-based Selective
Caching of Page-level Address Mappings " discloses improved FTL algorithm and its in solid storage device
The middle mode applied, full text can be from http://www.cse.psu.edu/~buu1/papers/ps/dftl-
Asplos09.pdf is obtained.Application No. is 2017113473632 Chinese patent application, (entitled " large capacity solid-state is deposited
Store up the address conversion method and device of equipment ") it provides suitable for large capacity solid storage device FTL table and its usage mode.
Summary of the invention
With the promotion of solid storage device capacity, such as the solid storage device with 4TB capacity, FTL table include 10^
9 entries cause the storage FTL in solid storage device to consume a large amount of storage space.To ensure to access the property of FTL table
Can, FTL table is generally stored with the DRAM memory of such as ddr interface.It is arranged in solid storage device and stores FTL table enough
DRAM memory also increases the cost of solid storage device.Need to save the storage space of FTL table occupancy.
According to a first aspect of the present application, it provides according to the first of the application first aspect the storage equipment, comprising: external
The front-end processing unit of memory and control unit, the control unit will be accommodated with the accessed corresponding FTL of logical address
The memory access unit of entry is moved by external memory to the FTL caching of the control unit, will be moved into FTL caching
Memory access location contents receive the storage unit with the accessed corresponding FTL entry of logical address move to front-end processing unit so that
With FTL entry；Wherein, storage unit presses the boundary alignment of memory access unit, and the boundary of FTL entry is not always aligned in storage unit
Boundary.
According to the first of the application first aspect the storage equipment, wherein the memory access unit is external memory and control
The minimum unit of data is transmitted between component.
Equipment is stored according to the first or second of the application first aspect, wherein the memory access unit is memory lines.
According to one of first of the application first aspect to third storage equipment, wherein before the storage unit is described
Hold the minimum unit of data transmission between processing unit and FTL caching.
According to one of the first to fourth of the application first aspect storage equipment, wherein the front-end processing unit calculates
With obtaining accommodating the storage of memory access unit with the accessed corresponding FTL entry of logical address relative to FTL table initial address
Location, and the memory access unit is moved from external memory to FTL according to the storage address and is cached.
According to the 5th of the application first aspect the storage equipment, wherein the front-end processing unit calculates m*se/sl and obtains
The integer part dl of quotient obtains accommodating with the accessed corresponding FTL entry of logical address by the integer part dl of the quotient
Storage address of the memory access unit relative to FTL table initial address, wherein m is corresponding with the logical address of access in FTL table
The number of the FTL entry stored before FTL entry, se are the size of the FTL entry in terms of bit, and sl is the memory access in terms of bit
The size of unit.
According to the 6th of the application first aspect the storage equipment, wherein it is the memory access unit of 64 bytes for size, it is described
M*se low 9 are given up or are moved to right and obtain the calculated result of m*se/sl by front-end processing unit.
According to the 6th or the 7th of the application first aspect the storage equipment, wherein the front-end processing unit calculates m*se/
Sl obtains the integer part rl of remainder, is obtained by the integer part rl of the remainder corresponding with accessed logical address
The initial address of FTL entry FTL caching in the memory access unit in relative to the memory access unit initial address away from
From.
According to the 8th of the application first aspect the storage equipment, wherein it is the memory access unit of 64 bytes for size, it is described
Front-end processing unit is by the low 9 integer part rl as m*se/sl remainder of m*se.
According to the 8th or the 9th of the application first aspect the storage equipment, wherein the front-end processing unit calculates (sl-
Rl), if the result of (sl-rl) is less than se, the front-end processing unit will be accommodated with the accessed corresponding FTL of logical address
The memory access unit of entry initial address and the memory access unit of described memory access unit the latter are moved to FTL and are cached.
According to the 5th of the application first aspect the storage equipment, wherein the front-end processing unit calculates m*se/sm/sml
The integer part dl of quotient is obtained, obtains accommodating with the accessed corresponding FTL of logical address by the integer part dl of the quotient
The storage address of the memory access unit of entry relative to FTL table initial address, wherein m is same in FTL table accesses logically
The number of the FTL entry stored before the corresponding FTL entry in location, se are the size of the FTL entry in terms of bit, and sm is with bit
The size of the storage unit of meter, sml are the size of the memory access unit in terms of storage unit.
According to one of the 5th to the 11st of the application first aspect the storage equipment, wherein the front-end processing unit meter
It calculates and obtains accommodating the memory access unit with accessed logical address corresponding FTL entry end address, if accommodating the end ground
The memory access unit of location is identical as the memory access unit for accommodating the storage address, then the memory access unit for accommodating the storage address can be complete
The FTL entry is accommodated entirely.
According to the 12nd of the application first aspect the storage equipment, wherein the front-end processing unit calculates m*se+se-1
Obtain the end address with the accessed corresponding FTL entry of logical address in FTL table, wherein m is in FTL table with access
The corresponding FTL entry of logical address before the number of FTL entry that stores, se is the size of FTL entry in terms of bit.
According to the first of the application first aspect storage equipment, wherein the front-end processing unit be calculated move to
Memory access location contents described in FTL caching receives the storage unit with the accessed corresponding FTL entry of logical address relative to FTL
The storage address of table initial address, and removed the storage unit from the memory access unit in FTL caching according to the storage address
Move to front-end processing unit.
According to the 14th of the application first aspect the storage equipment, wherein the front-end processing unit calculates m*se/sm and obtains
To the integer part dm of quotient, the storage address is obtained by the integer part dm of the quotient, wherein m is in FTL table with access
The corresponding FTL entry of logical address before the number of FTL entry that stores, se is the size of FTL entry in terms of bit, sm
For the size of the storage unit in terms of bit.
According to the 15th of the application first aspect the storage equipment, wherein be the storage list of 32 bit double words for size
M*se low 5 are given up or are moved to right and obtain the calculated result of m*se/sm by member, the front-end processing unit.
According to the 14th or the 15th of the application first aspect the storage equipment, wherein the front-end processing unit calculates
The integer part rm for the remainder that m*se/sm is obtained is obtained by the integer part rm of the remainder with accessed logical address
The initial address of the corresponding FTL entry distance relative to the initial address of the storage unit in the memory unit.
According to the 17th of the application first aspect the storage equipment, wherein be the storage list of 32 bit double words for size
Member, the front-end processing unit is by the low 5 integer part rm as m*se/sm remainder of m*se.
According to the 17th or the 18th of the application first aspect the storage equipment, wherein the front-end processing unit calculates
(sm-rm), if the result of (sm-rm) is less than se, the front-end processing unit will accommodate corresponding with accessed logical address
The storage unit of FTL entry initial address and the storage unit of described storage unit the latter move to the front-end processing list
Member.
According to one of the 14th to the 19th of the application first aspect the storage equipment, wherein the front-end processing unit
The storage unit for accommodating the end address with the accessed corresponding FTL entry of logical address is calculated, if accommodating the knot
The storage unit of beam address is identical as the storage unit for accommodating the storage address, then accommodates the storage unit of the storage address
The FTL entry can be accommodated completely.
According to the 20th of the application first aspect the storage equipment, wherein the front-end processing unit calculates m*se+se-1
Obtain the end address with the accessed corresponding FTL entry of logical address in FTL table.
According to the 21st of the application first aspect the storage equipment, wherein front-end processing unit is according to accessed n
The initial address of the corresponding FTL entry of continuous logical address and end address obtain accommodating from FTL entry m to FTL entry m+n
Storage unit and memory access unit.
According to the 22nd of the application first aspect the storage equipment, wherein FTL entry is in FTL table in terms of bit
Initial address is that end address of m*se, FTL entry m+n in FTL table in terms of bit is (m+n) * se+se-1.
According to one of the first to the 23rd of the application first aspect storage equipment, wherein add in response to memory access unit
It is loaded onto FTL caching, the FTL entry that the memory access unit that the front-end processing unit record is loaded onto FTL caching is accommodated is patrolled
Collect address.
According to the 24th of the application first aspect the storage equipment, wherein the front-end processing unit, which compares, to be accessed
Logical address and record move the logical address of FTL entry accommodated to the memory access unit that FTL is cached, to access
Logical address is then cached from FTL in the range of the logical address for the FTL entry that the buffered memory access unit of record is accommodated
It obtains with the corresponding FTL entry of the logical address to be accessed.
According to the 24th of the application first aspect the storage equipment, wherein the front-end processing unit, which calculates to be located at, to be added
Corresponding first logical address of same first FTL entry being loaded at the initial address of the memory access unit in FTL caching, judges memory access
Whether unit accommodates the first FTL entry completely；The front-end processing unit calculates same at the end address for being located at memory access unit
Corresponding second logical address of 2nd FTL entry, judges whether memory access unit accommodates the 2nd FTL entry completely；At the front end
The FTL entry that reason unit record memory access unit completely accommodates.
According to the 26th of the application first aspect the storage equipment, wherein the front-end processing unit calculates l1*sl/
Se, the integer part de for obtaining quotient indicate same first FTL entry corresponding first at the initial address of memory access unit
Logical address, wherein l1 is the memory access unit stored before the memory access unit l1 in the multiple memory access units for store FTL table
Number, sl is the size of memory access unit in terms of bit, and se is the size of the FTL entry in terms of bit.
According to the 27th of the application first aspect the storage equipment, wherein the front-end processing unit calculates l1*sl/
Se obtains the integer part re of the remainder of quotient, if re is 0, the memory access unit accommodates the first FTL entry completely.
According to the 26th of the application first aspect the storage equipment, wherein the front-end processing unit calculates (l1*sl+
Sl-1)/se, the integer part of obtained quotient indicate the 2nd FTL entry pair at the end address of the memory access unit
The second logical address answered, wherein l1 is to store before the memory access unit l1 in the multiple memory access units for store FTL table
The number of memory access unit, sl are the size of the memory access unit in terms of bit, and se is the size of the FTL entry in terms of bit.
According to the 29th of the application first aspect the storage equipment, wherein the front-end processing unit calculates (l1*sl+
Sl-1 the integer part ree for the remainder that)/se is obtained, if ree is se-1, the memory access unit l1 completely contains the 2nd FTL
Entry.
According to the 27th or the 28th of the application first aspect the storage equipment, wherein the front-end processing unit
I1*sl/se calculating is transformed to (l1*sl*2^j/se)/(2^j) to calculate, wherein j is the larger integer convenient for calculating.
According to the 27th or the 28th of the application first aspect the storage equipment, wherein the front-end processing unit
By calculating re=l1*sl-de*se, the division calculation in l1*sl/se is converted into multiplication and subtraction.
According to the 25th of the application first aspect the storage equipment, wherein the front-end processing unit is calculated with interviewed
Poor d of the initial address in terms of bit of the initial address visiting memory cell of the corresponding FTL entry of the logical address asked, d/se are obtained
The integer part of quotient indicates the quantity of the FTL entry completely accommodated before the FTL entry in memory access unit；The front end
Processing unit calculate the end address of the end address visiting memory cell with the accessed corresponding FTL entry of logical address with than
The poor a of spy's meter, the integer part that a/se obtains quotient indicate the FTL completely accommodated after the FTL entry in memory access unit
The quantity of entry；In record memory access unit the FTL entry that is completely accommodated before the FTL entry to the FTL entry it
The logical address of the FTL entry completely accommodated afterwards；Wherein, se is the size of the FTL entry in terms of bit.
According to the first of the application first aspect the storage equipment, further includes: the host coupled with the front-end processing unit
Interface, the host interface are used for host exchange command and data.
According to the first of the application first aspect the storage equipment, further includes: the medium for accessing the NVM chip connects
Mouthful.
According to the first of the application first aspect storage equipment, wherein the FTL entry it is of different sizes in storage unit
The integral multiple of size.
According to the first of the application first aspect the storage equipment, wherein the FTL caching is inside the control unit
Memory.
According to a second aspect of the present application, the side according to the first of the application second aspect the access FTL table clause is provided
Method, comprising the following steps: obtain the logical address of I/O command access；External storage is calculated according to the logical address of I/O command access
The memory access unit with the accessed corresponding FTL entry of logical address is accommodated in device, and the memory access unit is loaded onto caching；
It is calculated according to the logical address of I/O command access and is accommodated in the memory access unit with the accessed corresponding FTL item of logical address
Purpose access unit address；According to address of the storage unit in the memory access unit, deposited described in acquisition from caching
Storage unit is to use FTL entry.
According to the method for the first of the application second aspect the access FTL table clause, wherein receiving is calculated with accessed
The corresponding FTL entry of logical address storage address of the memory access unit relative to FTL table initial address, and according to the storage
Address is moved from external memory to caching by the memory access unit.
According to the method for the second of the application second aspect the access FTL table clause, wherein calculate m*se/sl and obtain quotient's
Integer part dl obtains accommodating the visit with the accessed corresponding FTL entry of logical address by the integer part dl of the quotient
The storage address of the memory cell relative to FTL table initial address, wherein m is corresponding with the logical address of access in FTL table
The number of the FTL entry stored before FTL entry, se are the size of the FTL entry in terms of bit, and sl is the memory access in terms of bit
The size of unit.
The method for accessing FTL table clause according to the third of the application second aspect, wherein be the visit of 64 bytes for size
M*se low 9 are given up or are moved to right and obtain the calculated result of m*se/sl by memory cell.
According to the second of the application second aspect or the method for third access FTL table clause, wherein calculate m*se/sl and obtain
To the integer part rl of remainder, obtained by the integer part rl of the remainder with the accessed corresponding FTL item of logical address
Distance of the purpose initial address in the memory access unit in FTL caching relative to the initial address of the memory access unit.
According to the method for the 5th of the application second aspect the access FTL table clause, wherein be the visit of 64 bytes for size
Memory cell, by the low 9 integer part rl as m*se/sl remainder of m*se.
According to the method for the 5th or the 6th of the application second aspect the access FTL table clause, wherein it calculates (sl-rl), if
(sl-rl) result is less than se, then will accommodate the memory access list of the initial address of the same accessed corresponding FTL entry of logical address
The memory access unit of first and described memory access unit the latter is moved to caching.
According to the method for the first of the application second aspect the access FTL table clause, wherein calculate m*se/sm/sml and obtain
The integer part dl of quotient obtains accommodating with the accessed corresponding FTL entry of logical address by the integer part dl of the quotient
The storage address of the memory access unit relative to FTL table initial address, wherein m is in FTL table with the logical address pair of access
The number of the FTL entry stored before the FTL entry answered, se are the size of the FTL entry in terms of bit, and sm is in terms of bit
The size of storage unit, sml are the size of the memory access unit in terms of storage unit.
According to one of the method for the first to the 8th of the application second aspect the access FTL table clause, wherein appearance is calculated
The memory access unit received with the end address of the accessed corresponding FTL entry of logical address, if accommodating the visit of the end address
Memory cell is identical as the memory access unit for accommodating the storage address, then the memory access unit for accommodating the storage address can accommodate completely
The FTL entry.
According to the method for the 9th of the application second aspect the access FTL table clause, wherein calculate m*se+se-1 and held
The end address received with the accessed corresponding FTL entry of logical address.
According to the method for the first of the application second aspect the access FTL table clause, wherein the institute into caching is moved in calculating
Storage unit that memory access location contents is received with the accessed corresponding FTL entry of logical address is stated relative to FTL table initial address
The first storage address, and the storage unit is obtained from caching to use FTL entry according to first storage address.
According to the method for the 11st of the application second aspect the access FTL table clause, wherein calculate m*se/sm and obtain quotient
Integer part dm, the storage address is obtained by the integer part dm of the quotient, wherein m be FTL table in access patrolling
The number of the FTL entry stored before volume corresponding FTL entry in address, se are the size of the FTL entry in terms of bit, sm be with
The size of the storage unit of bit meter.
According to the method for the 12nd of the application second aspect the access FTL table clause, wherein be that 32 bits are double for size
M*se low 5 are given up or are moved to right and obtain the calculated result of m*se/sm by the storage unit of word.
According to the method for the 11st or the 12nd of the application second aspect the access FTL table clause, wherein calculate m*se/
The integer part rm for the remainder that sm is obtained is obtained corresponding with accessed logical address by the integer part rm of the remainder
The initial address of the FTL entry distance relative to the initial address of the storage unit in the memory unit.
According to the method for the 14th of the application second aspect the access FTL table clause, wherein be that 32 bits are double for size
The storage unit of word, by the low 5 integer part rm as m*se/sm remainder of m*se.
According to the method for the 14th or the 15th of the application second aspect the access FTL table clause, wherein calculate (sm-
Rm), if the result of (sm-rm) is less than se, obtain and accommodated with the accessed corresponding FTL entry of logical address from caching
The storage unit of the storage unit of initial address and described storage unit the latter is to use FTL entry.
According to one of the method for the 11st to the 16th of the application second aspect the access FTL table clause, wherein calculate
To the storage unit accommodated with accessed logical address corresponding FTL entry end address, if accommodating the end address
Storage unit is identical as the storage unit for accommodating the storage address, then the storage unit for accommodating the storage address can be held completely
Receive the FTL entry.
According to the method for the 17th of the application second aspect the access FTL table clause, wherein calculate m*se+se-1 and obtain
It accommodates with accessed logical address corresponding FTL entry end address.
According to the method for the 18th of the application second aspect the access FTL table clause, wherein according to n accessed company
The initial address of the corresponding FTL entry of continuous logical address and end address obtain accommodating from FTL entry m to FTL entry m+n's
Storage unit and memory access unit.
According to the 19th of the application second aspect the access FTL table clause method, wherein FTL entry in FTL table with
End address (m+n) * se+se-1 of initial address m*se, the FTL entry m+n of bit meter in FTL table in terms of bit.
According to the method for the first of the application second aspect the access FTL table clause, wherein memory access unit is loaded onto caching
Afterwards, the logical address for the FTL entry that buffered memory access unit is accommodated is recorded；The method also includes: compare I/O command and wants
The logical address for the FTL entry that the logical address of access and the buffered memory access unit of record are accommodated, if I/O command will visit
The logical address asked then is postponed in the range of the logical address for the FTL entry that the buffered memory access unit of record is accommodated
It deposits and obtains with the I/O command logical address to be accessed corresponding FTL entry.
According to the method for the 21st of the application second aspect the access FTL table clause, wherein in response to by memory access unit
It is loaded onto caching, calculates corresponding first logical address of same first FTL entry being located at the initial address of memory access unit；Judgement
Whether memory access unit accommodates the first FTL entry completely；Calculate the same 2nd FTL entry pair being located at the end address of memory access unit
The second logical address answered；Judge whether memory access unit accommodates the 2nd FTL entry completely；Record memory access unit completely accommodates
FTL entry.
According to the method for the 22nd of the application second aspect the access FTL table clause, wherein calculate l1*sl/se, obtain
Integer part de to quotient indicates the same first FTL entry corresponding first at the initial address of memory access unit logically
Location, wherein l1 is of the memory access unit stored before the memory access unit l1 in the multiple memory access units for store FTL table
Number, sl are the size of the memory access unit in terms of bit, and se is the size of the FTL entry in terms of bit.
According to the method for the 22nd or the 23rd of the application second aspect the access FTL table clause, wherein calculate
L1*sl/se obtains the integer part re of the remainder of quotient, if re is 0, the memory access unit l1 accommodates the first FTL entry completely,
Wherein, l1 is the number of the memory access unit stored before the memory access unit l1 in the multiple memory access units for store FTL table, sl
For the size of the memory access unit in terms of bit, se is the size of the FTL entry in terms of bit.
According to the method for the 22nd of the application second aspect the access FTL table clause, wherein calculate (l1*sl+sl-
1)/se, it is corresponding that the integer part of obtained quotient indicates the 2nd FTL entry at the end address of the memory access unit l1
The second logical address, wherein l1 is the visit that stores before the memory access unit l1 in the multiple memory access units for store FTL table
The number of memory cell, sl are the size of the memory access unit in terms of bit, and se is the size of the FTL entry in terms of bit.
According to the method for the 25th of the application second aspect the access FTL table clause, wherein calculate (l1*sl+sl-
1) the integer part ree for the remainder that/se is obtained, if ree is se-1, the memory access unit l1 completely contains the 2nd FTL articles
Mesh, wherein l1 is of the memory access unit stored before the memory access unit l1 in the multiple memory access units for store FTL table
Number, sl are the size of the memory access unit in terms of bit, and se is the size of the FTL entry in terms of bit.
According to the method for the 23rd or the 24th of the application second aspect the access FTL table clause, wherein by l1*
Sl/se is transformed to (l1*sl*2^j/se)/(2^j), and wherein j is the larger integer convenient for calculating.
According to the method for the 25th or the 26th of the application second aspect the access FTL table clause, wherein pass through re
Division calculation in l1*sl/se is converted to multiplication and subtraction by=l1*sl-de*se.
According to the method for the 21st of the application second aspect the access FTL table clause, wherein in response to by memory access unit
It is loaded onto caching, calculates the initial address of the initial address visiting memory cell with the accessed corresponding FTL entry of logical address
Poor d in terms of bit, the integer part that d/se obtains quotient, which indicates, completely to be accommodated before the FTL entry in memory access unit
The quantity of FTL entry；With calculating the end of the end address visiting memory cell with the accessed corresponding FTL entry of logical address
Poor a of the location in terms of bit, the integer part that a/se obtains quotient are indicated in memory access unit and are completely accommodated after the FTL entry
FTL entry quantity；The FTL entry completely accommodated before the FTL entry in record memory access unit is in the FTL item
The logical address of the FTL entry completely accommodated after mesh；Wherein, se is the size of the FTL entry in terms of bit.
According to the third aspect of the application, the journey according to the first of the application third aspect including program code is provided
Sequence, when being loaded into host and executing on host, described program makes the processor of host execute visit described in any of the above embodiments
The method for asking FTL table clause.
The application from external memory by moving the memory access unit for accommodating FTL entry to caching, from the visit in caching
The storage unit for accommodating FTL entry is moved in memory cell to utilize FTL entry, is realized and is utilized by storage unit by memory access unit
Boundary alignment, the boundary of FTL entry be not always aligned in the boundary of storage unit form compression storage FTL entry mesh
, to achieve the effect that the space for having saved the storage equipment of FTL table occupancy.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The some embodiments recorded in invention can also be obtained according to these attached drawings other for those of ordinary skill in the art
Attached drawing.
Fig. 1 illustrates the block diagram of the solid storage device of the prior art；
Fig. 2 illustrates the block diagram of the solid storage device according to the embodiment of the present application；
Fig. 3 illustrates the signal for storing FTL entry in a compressed format in external memory according to the embodiment of the present application
Figure；
Fig. 4 illustrates the FTL entry stored in a compressed format in external memory according to the access of the embodiment of the present application
Flow chart；
Fig. 5 illustrates the schematic diagram of the FTL entry according to the embodiment of the present application in FTL cache unit.
Specific embodiment
With reference to the attached drawing in the embodiment of the present invention, technical solution in the embodiment of the present invention carries out clear, complete
Ground description, it is clear that described embodiments are some of the embodiments of the present invention, instead of all the embodiments.Based on the present invention
In embodiment, those skilled in the art's every other embodiment obtained without making creative work, all
Belong to the scope of protection of the invention.
Fig. 2 illustrates the block diagram of the solid storage device according to the embodiment of the present application.The control unit of solid storage device
104 include host interface 210, front-end processing unit 260, backend processing unit 270 and the medium for accessing NVM chip 105
Interface 220.
Host interface 210 is used for host exchange command and data.In one example, host passes through with storage equipment
NVMe/PCIe protocol communication, host interface 210 handle PCIe protocol data packet, extract NVMe protocol command, and return to host
Return the processing result of NVMe protocol command.
Front-end processing unit 260 is coupled to host interface 210, and the I/O command of storage equipment is sent to for receiving host.
For reading I/O command, the logical address that front-end processing unit 260 is accessed according to I/O command inquires FTL table to obtain with logically
The corresponding physical address in location, and indicate that backend processing unit 270 passes through Media Interface Connector 220 from NVM chip 105 according to physical address
Read data.For writing I/O command, front-end processing unit 260 is I/O command allocated physical address, indicates backend processing unit 270
Data that I/O command to be written will be write by Media Interface Connector and are written to the physical address distributed and the front end of NVM chip 105
Processing unit 260 also updates FTL table with the physical address of distribution.
Control unit 104 is additionally coupled to external memory (for example, DRAM with ddr interface) 110.External memory
110 segment space be used to store FTL.Multiple entries that FTL table is stored in external memory 110 are illustrated in Fig. 2
(FTL entry 0, FTL entry 1, FTL entry 2, FTL entry 3 ... FTL entry m, FTL entry m+1, FTL entry m+2, FTL item
Mesh m+3 etc.).FTL entry has specified size, for example, 30 bits, for describing on NVM chip 10^9 or 2^30
The physical address of physical memory cell.
External memory 110 has biggish access delay.To improve FTL table access performance, control unit further includes FTL
Caching 262.FTL caching 262 is the memory inside control unit, has lower access delay.Front-end processing unit 260 will
The FTL entry obtained from external memory 110 is buffered in FTL caching 262, and during handling I/O command, is cached using FTL
FTL entry in 262.
For the FTL entry with such as 30 bit sizes, in the prior art, the storage unit using 4 byte-sizeds exists
FTL entry is stored in external memory.General 4 byte constitutes double word (DWORD), obtains by 4 byte-sizeds access external memory
The preferable support of the prior art is arrived.
However, storing FTL entry (30 bit) with the storage unit of double word size (32 bit), waste in storage unit
2 bits.When FTL entry has such as 10^9 or 2^30 FTL entry, the memory space for amounting to waste is more than 100MB.
With continued reference to Fig. 2, external memory 110 is carried out to the data transmission between control unit by memory lines.As
Citing, memory lines size are 64 bytes, by the bus of control unit access external memory and/or the data of storage control
Width determines.Memory lines are that the minimum data size of data is transmitted between external memory 110 and control unit.
It is to be appreciated that FTL entry can have other sizes, for example, 29 bits, 31 bits, 32 bits, 34 bits are even
It is greater or lesser.
Fig. 3 illustrates the signal for storing FTL entry in a compressed format in external memory according to the embodiment of the present application
Figure.
Memory access unit is the minimum unit that data are transmitted between external memory and control unit, for example, memory lines.It visits
Memory cell includes multiple storage units, and it is the front-end processing unit 260 of control unit that storage unit, which has the size of such as double word,
The minimum unit of data transmission between (referring also to Fig. 2) and FTL caching.Storage unit presses the boundary alignment of memory access unit, thus
The initial address of the initial address of memory access unit always storage unit, and the knot of the end address of memory access unit always storage unit
Beam address, there is no the storage units across two memory access units.
According to the embodiment of Fig. 3, the size of FTL entry is less than storage unit, is such as 30 bits.Multiple FTL of FTL table
Entry is tightly packed (also referred to as compressed format storage) in the memory unit, the knot of a FTL entry (such as FTL entry 0)
Tail does not have unappropriated memory space between two FTL entries close to the beginning of next FTL entry (such as FTL entry 1).
Since the size of FTL entry is less than the size of storage unit, thus FTL entry and the boundary of storage unit and be not always aligned,
Correspondingly, FTL entry also and is not always aligned with the boundary of memory access unit.For example, the initial address of FTL entry 0 is same to store list
The initial address alignment of member, and the initial address of FTL entry 1 is located at 30 bit of initial address of storage unit 0 (apart
2 bit of initial address of storage unit 1), the initial address of FTL entry 2 is located at 28 bit of initial address at a distance of storage unit 1
Place.
For example, C point is the boundary of memory access unit L0 and memory access unit L1 and the boundary of storage unit in Fig. 3.And A point
It is the boundary of storage unit, is not but the boundary of memory access unit, nor the boundary of FTL entry.B point is the boundary of FTL entry,
Rather than the boundary of memory access unit, nor the boundary of storage unit.
Solid storage device indicates the logical address to be accessed from the I/O command of host interface.The same FTL of logical address
Entry is corresponding, for example, it is corresponding for NVM to have recorded same logical address in the FTL entry uniquely determined with the value of logical address
The physical address of storage chip.
For access with a certain logical address m corresponding FTL entry (for example, FTL entry m, m be 0 or positive integer), at front end
The memory access unit L1 that FTL entry m is contained in external memory 110 is moved FTL caching by reason unit 260 (referring also to Fig. 2)
262.Front-end processing unit also identifies which storage unit in the memory access unit L1 for moving FTL caching 262 is contained and to be visited
The FTL entry asked.
According to an embodiment of the present application, the memory access unit that specified FTL entry m is accommodated in external memory 110 is determined
(L1), to move memory access unit L1 to FTL caching 262 from external memory 110.And it also needs to determine in memory access unit L1
The storage unit k (and possible storage unit k+1) of specified FTL entry m is accommodated, to remove FTL entry m from FTL caching 262
Move to front processing unit 260.
As an example, I/O command instruction will access logical address m, and FTL entry m has recorded the corresponding object of same logical address m
Manage address.M FTL entry (FTL entry 0 arrives FTL entry m-1) is stored before FTL entry m in FTL table, thus relative to
The initial address of FTL table is stored, initial address of the FTL entry m in FTL table in terms of bit is m*se, and wherein se represents FTL item
Purpose size (bit number) (for example, 30).The size of storage unit in terms of bit is denoted as sm (for example, 32 bit double words).
The size of memory access unit in terms of bit is denoted as sl (for example, 64 bytes (512 bit)).
Calculate m*se/sm, the integer part (being denoted as dm) of obtained quotient indicate storage unit k (referring to Fig. 3) relative to
The storage address of FTL table initial address.Optionally, it is the storage unit of 32 bit double words for size, m*se low 5 is given up
(such as a high position of the reservation in addition to low 5, or move to right 5) obtain the calculated result of m*se/sm.Division is substituted with bit operating
Operation, will be obviously improved calculating speed.
M*se/sm is calculated, the initial address that the integer part (being denoted as rm) of obtained remainder indicates FTL entry m is being deposited
Distance in storage unit k (referring to Fig. 3) relative to the initial address of storage unit k.It optionally, is 32 bit double words for size
Storage unit, by low 5 of m*se be used as rm.
Further, if (sm-rm) is less than se, it is meant that storage unit k cannot accommodate FTL entry m, thus FTL completely
The part of entry m is stored by storage unit k+1.
Calculate the integer part (being denoted as dl) of quotient that m*se/sl is obtained indicate memory access unit l (referring to Fig. 3) relative to
The storage address of FTL table initial address.Optionally, it is the memory access unit of 64 bytes for size, gives up (example for m*se low 9
As retained a high position in addition to low 9, or move to right 9) obtain the calculated result of m*se/sl.
Optionally, the size of the memory access unit in terms of storage unit is denoted as sml (for example, every memory access unit accommodates 16
Storage unit).The integer part (being denoted as dl) for calculating the quotient that m*se/sm/sml is obtained indicates memory access unit l1 (referring to Fig. 3)
Storage address relative to FTL table initial address.
M*se/sl is calculated, the initial address that the integer part (being denoted as rl) of obtained remainder indicates FTL entry m is being visited
Distance in memory cell l1 (referring to Fig. 3) relative to the initial address of memory access unit l1.It optionally, is 64 bytes for size
Memory access unit is used as rl for low 9 of m*se.
Further, if (sl-rl) is less than se, it is meant that memory access unit l1 cannot accommodate FTL entry m, thus FTL completely
The part of entry m is interviewed memory cell l2 storage.
In alternative embodiments, m*se is initial address of the FTL entry m in FTL table in terms of bit, and is passed through
(m*se+se-1) end address of the FTL entry m in FTL table in terms of bit is obtained.In a similar way, it obtains accommodating FTL item
The storage unit and memory access unit of end address (m*se+se-1) of the mesh m in FTL table in terms of bit.By identifying the storage
Whether unit/memory access unit and storage unit k/ memory access unit l1 are identical, and can carry out recognition memory cell k accommodate FTL item completely
Can mesh m and memory access unit l1 accommodate FTL entry m completely.
In still optional embodiment, the continuous multiple logical addresses of I/O command access, initial logical address m,
And the logical address that ends up is m+n.M*se is initial address of the FTL entry m in FTL table in terms of bit, and passes through ((m+n) * se
+ se-1) obtain end address of the FTL entry m+n in FTL table in terms of bit.And then it obtains accommodating from FTL entry m to FTL item
The storage unit and memory access unit of mesh m+n.
Fig. 4 illustrates the FTL entry stored in a compressed format in external memory according to the access of the embodiment of the present application
Flow chart.
Step S410, front-end processing unit (referring also to Fig. 2, front-end processing unit 260) receive I/O command, obtain I/O command
The logical address of access.The logical address of I/O command access can be one or more.For clear purpose, accessed with I/O command
The embodiment of Fig. 4 displaying is described for one logical address.
Step S420 is calculated according to the logical address of I/O command access and is accommodated the logic with access in external memory 110
The memory access unit l1 (and possible memory access unit l2) of the corresponding FTL entry of address m.Step S430, to external memory 110
It reads memory access unit l1 (and possible memory access unit l2), memory access unit l1 (and possible memory access unit l2) is loaded
To FTL caching 262.Step S440, front-end processing unit 260 are calculated also according to the logical address that I/O command accesses in memory access unit
Storage unit (the storage of the corresponding FTL entry m of logical address of the same access accommodated in l1 (and possible memory access unit l2)
Unit mm and possible storage unit mm+1) address.
Step S450, front-end processing unit is according to storage unit mm (and possible storage unit mm+1) in memory access unit
Address in l1 (and possible memory access unit l2) obtains storage unit mm (and possible storage from FTL caching 262
Unit mm+1) to use FTL entry m.
Fig. 5 illustrates the schematic diagram of the FTL entry according to the embodiment of the present application in FTL cache unit.
It is received in the memory access unit including FTL entry in the FTL caching that Fig. 5 is shown, the knot as the method for executing Fig. 4
Fruit.For purposes of clarity, FTL entry m is accommodated by single storage unit and memory access unit.
Along with FTL entry m be transferred to FTL caching 262, it is adjacent with FTL entry m and for same memory access unit l1 accommodate
Multiple other FTL entry (part of FTL entry m-1, FTL entry m+1 and FTL entry m-2 and portions of FTL entry m+2
Point) all it is transferred to FTL caching 262.
In Fig. 5, the part of FTL entry m-2 is located at except memory access unit l1 with the part of FTL entry m+2, these parts are not
FTL caching 262 is loaded by Fig. 4 method shown.
Other than the FTL entry m that the logical address m according to I/O command is loaded, it is also stored in FTL caching 262
Other FTL entries.These other FTL entries can be fully utilized.If the following received I/O command of front-end processing unit 260 is visited
FTL entry (FTL entry m-1 to FTL entry m+1) present in FTL caching 262 is asked, without again from external memory 110
FTL entry is read, and directly from 262 access FTL entry of FTL caching, to be accelerated by the acquisition time for shortening FTL entry
Processing to I/O command.
In order to use these other FTL entries in FTL caching 262, need to know corresponding to these other FTL entries
Logical address.Initial address i.e. relative to storage FTL table, FTL cache starting point of the memory access unit l1 in terms of bit in 262
Location is l1*sl, and wherein l1 is number of the memory access unit l1 in multiple memory access units of storage FTL table (since 0).
L1*sl/se is calculated, the integer part (being denoted as de) of obtained quotient indicates the initial address positioned at memory access unit l1
The corresponding logical address (m-2) of the FTL entry m-2 (referring to Fig. 5) at place.Calculate l1*sl/se, the integer part of obtained remainder
(being denoted as re) indicates the initial address of memory access unit l1 at a distance of the distance of the initial address of FTL entry m-2 (in terms of bit).If
Re is 0, it is meant that memory access unit l1 completely contains FTL entry m-2, if re is greater than 0, it is meant that the endless lift face of memory access unit l1
Receive FTL entry m-2.
Similarly, (l1*sl+sl-1)/se is calculated, the integer part of obtained quotient is indicated positioned at the end of memory access unit l1
The corresponding logical address (m+2) of FTL entry m+2 (referring to Fig. 5) at tail address.(l1*sl+sl-1)/se is calculated, what is obtained is remaining
The integer part of number (being denoted as ree) indicates the end address of memory access unit l1 at a distance of the distance of the initial address of FTL entry m+2
(in terms of bit).If ree is se-1, it is meant that memory access unit l1 completely contains FTL entry m+2, if ree is less than se-1, meaning
Taste the imperfect receiving FTL entry m+2 of memory access unit l1.
Division calculation is time-consuming.In alternative embodiments, the division calculation in l1*sl/se is converted into multiplication
With shifting function, the quotient (de) of l1*sl/se and the process of remainder (re) are obtained with quickening.For example, l1*sl/se is transformed to
(l1*sl*2^j/se)/(2^j), wherein j is that front-end processing unit 260 can be convenient for the larger integer of calculating, for example, 20~30.
To which l1*sl/se is transformed to l1*sl multiplied by (2^j/se) again divided by the calculating of (2^j).Since j is known designated value (example
Such as, the value in 20~30), so that (2^j/se) is also the given value (being denoted as A) that can be calculated, for convenient for front-end processing unit
260 processing, take the integer part of (2^j/se) to give up fractional part as A.Front-end processing unit calculates l1*sl multiplied by A.It removes
It is converted into the calculating of (2^j) and moves to right j operations.To which front-end processing unit 260 is by calculating l1*sl multiplied by A, incite somebody to action
To result move to right j, to obtain the quotient (de) of l1*sl/se.So that the original calculating process divided by se is replaced by once
Multiplication (multiplied by A) and primary displacement (moving to right j).
Further, remainder re=l1*sl-de*se can pass through multiplication and subtraction according to obtained quotient (de)
Operation obtains remainder (re).Further, by positive integer se be decomposed into one or more 2 power and (for example, 30=2^4+2^
3+2^2+2^1).Remember se=2^a1+2^a2+ ...+2^ai (wherein ai is positive integer), then de*se=de* (2^a1+2^a2+ ...+
2^ai)=de*2^a1+de*2^a2+ ...+de*2^ai.And de*2^ai can be obtained by the way that de is moved to left ai times, thus by multiplication
Operation is converted to shift left operation and add operation.As another example, 30=(2^4-1) * 2, thus de*30=(de*2^4-
De) * 2, thus the result by the way that de is moved to left 4 subtracts de, then obtained result is moved to left 1, obtains the value of de*30.
Based on the introduction of scheme disclosed above, one of ordinary skill in the art will recognize in a variety of determining memory access unit l1
The mode of all FTL entries completely accommodated.For example, calculating the starting point of the initial address visiting memory cell l1 of FTL entry m
Difference (be denoted as d) of the location in terms of bit, the integer part for the quotient that d/se is obtained indicate in memory access unit l1 before FTL entry m
Also completely contain how many a FTL entries.The serial number of these entries is before the serial number of FTL entry m, and the sequence with FTL entry m
It is number adjacent.Similarly, it determines and also completely contains how many a FTL entries in memory access unit l1 after FTL entry m.
Still optionally, in known memory access unit l1 the initial address of first FTL entry completely accommodated basis
On, according to the size (se) of the size (sl) of memory access unit l1 and FTL entry, also it is convenient to determine that memory access unit l1's is complete
All FTL entries accommodated.
FTL is cached the first FTL entry completely accommodated in the memory access unit l1 in 262 to be denoted as (start_e), it will
The last one the FTL entry completely accommodated in memory access unit l1 in FTL caching 262 is denoted as (end_e).In FTL entry
(start_e) all FTL entries between FTL entry (end_e) are all completely contained in FTL caching 262.Front-end processing
Unit 260 records FTL entry (start_e) ranges of logical addresses corresponding with FTL entry (end_e) (from start_e to end_
e).And then the logical address to be accessed in response to receiving I/O command of front-end processing unit 260, it to be accessed by comparing I/O command
Whether logical address belongs to ranges of logical addresses (from start_e to end_e) and determines whether required FTL entry is present in
In FTL caching 262.For the FTL entry being present in FTL caching 262, front-end processing unit 260 is obtained from FTL caching 262
FTL entry is taken, and need not be in access external memory 110.
In one embodiment, for writing I/O command, will remember in the corresponding FTL entry of the logical address of same write order
The physical address of record is updated to distribute to the new physics address for writing I/O command.Front-end processing unit 260 caches in 262 more in FTL
New FTL entry, and the memory access unit that updated FTL entry is accommodated in FTL caching 262 is write back into external memory 110.
The embodiment of the present application also provides a kind of program including program code, when being loaded into host and execute on host
When, described program makes the processor of host execute one of the method provided above according to the embodiment of the present application.
It should be understood that the combination of the frame of each frame and block diagram and flow chart of block diagram and flow chart can be respectively by including
The various devices of computer program instructions are implemented.These computer program instructions can be loaded into general purpose computer, dedicated meter
To generate machine on calculation machine or other programmable datas control equipment, to control equipment in computer or other programmable datas
The instruction of upper execution creates for realizing the device for the function of specifying in one or more flow chart box.
These computer program instructions, which can also be stored in, can guide computer or other programmable datas to control equipment
Computer-readable memory in working in a specific way, so as to using being stored in computer-readable memory
Instruction to manufacture including the product for realizing the computer-readable instruction of specified function in one or more flow chart box.
Computer program instructions can also be loaded into computer or other programmable datas control equipment on so that computer or its
A series of operation operation is executed in his programmable data control equipment, to generate computer implemented process, and then is being counted
The instruction executed on calculation machine or other programmable datas control equipment provides for realizing institute in one or more flow chart box
The operation of specified function.
Thus, the frame of block diagram and flow chart is supported for executing the combination of the device of specified function, for executing specified function
The combination of the operation of energy and the combination of the program instruction means for executing specified function.It should also be understood that block diagram and flow chart
Each frame and the combination of frame of block diagram and flow chart can be by executing specified functions or operations, hardware based dedicated meters
Calculation machine system is realized, or is realized by the combination of specialized hardware and computer instruction.
Although the example of present invention reference is described, it is intended merely to the purpose explained rather than the limit to the application
System, the change to embodiment, increase and/or deletion can be made without departing from scope of the present application.
In the field benefited involved in these embodiments, from the description above with the introduction presented in associated attached drawing
Technical staff will be recognized the application recorded here it is many modification and other embodiments.It should therefore be understood that this Shen
It please be not limited to disclosed specific embodiment, it is intended to will modify and other embodiments include in the scope of the appended claims
It is interior.Although using specific term herein, them are only used on general significance and describing significance and not is
The purpose of limitation and use.
Claims (10)
1. a kind of storage equipment, comprising: the front-end processing unit of external memory and control unit, the control unit will accommodate
Memory access unit with the accessed corresponding FTL entry of logical address is moved by external memory to the FTL of the control unit
The memory access location contents moved into FTL caching is received depositing with the accessed corresponding FTL entry of logical address by caching
Storage unit is moved to front-end processing unit to use FTL entry；Wherein, storage unit presses the boundary alignment of memory access unit, FTL item
Purpose boundary is not always aligned in the boundary of storage unit.
2. storage equipment according to claim 1, wherein the front-end processing unit is calculated what receiving was accessed together
Storage address of the memory access unit of the corresponding FTL entry of logical address relative to FTL table initial address, and according to the storage ground
The memory access unit is moved from external memory to FTL and is cached in location.
3. storage equipment according to claim 2, wherein the front-end processing unit calculates m*se/sl and obtains the whole of quotient
Number part dl obtains accommodating the memory access with the accessed corresponding FTL entry of logical address by the integer part dl of the quotient
Storage address of the unit relative to FTL table initial address, wherein m is in FTL table with the corresponding FTL item of logical address of access
The number of the FTL entry stored before mesh, se are the size of the FTL entry in terms of bit, and sl is the memory access unit in terms of bit
Size.
4. storage equipment according to claim 3, wherein the front-end processing unit calculates m*se/sl and obtains remainder
Integer part rl obtains the starting with the accessed corresponding FTL entry of logical address by the integer part rl of the remainder
Distance of the address in the memory access unit in FTL caching relative to the initial address of the memory access unit.
5. storage equipment according to claim 2, wherein the front-end processing unit calculates m*se/sm/sml and obtains quotient
Integer part dl, obtain accommodating with the accessed corresponding FTL entry of logical address by the integer part dl of the quotient
The storage address of the memory access unit relative to FTL table initial address, wherein m is that the logical address in FTL table with access is corresponding
FTL entry before the number of FTL entry that stores, se is the size of FTL entry in terms of bit, and sm is depositing in terms of bit
The size of storage unit, sml are the size of the memory access unit in terms of storage unit.
6. storage equipment according to claim 1, wherein the front-end processing unit is calculated to move to FTL and cache
Described in memory access location contents receive the storage unit with the accessed corresponding FTL entry of logical address and originated relative to FTL table
The storage address of address, and moved the storage unit to preceding from the memory access unit in FTL caching according to the storage address
Hold processing unit.
7. a kind of method for accessing FTL table clause, comprising the following steps:
Obtain the logical address of I/O command access；
It is calculated in external memory and is accommodated with the accessed corresponding FTL item of logical address according to the logical address of I/O command access
Purpose memory access unit, and the memory access unit is loaded onto caching；
It is corresponding with accessed logical address that the receiving in the memory access unit is calculated according to the logical address of I/O command access
The access unit address of FTL entry；
According to address of the storage unit in the memory access unit, the storage unit is obtained from caching to use FTL
Entry.
8. the method for access FTL table clause according to claim 7, wherein after memory access unit is loaded onto caching, record quilt
The logical address for the FTL entry that the memory access unit of caching is accommodated；The method also includes: compare the I/O command logic to be accessed
The logical address for the FTL entry that the buffered memory access unit of address and record is accommodated, if I/O command to be accessed logically
Location then obtains same IO from caching in the range of the logical address for the FTL entry that the buffered memory access unit of record is accommodated
Order the corresponding FTL entry of the logical address to be accessed.
9. the method for access FTL table clause according to claim 8, wherein in response to memory access unit is loaded onto caching,
Calculate corresponding first logical address of same first FTL entry being located at the initial address of memory access unit；
Judge whether memory access unit accommodates the first FTL entry completely；
Calculate corresponding second logical address of same 2nd FTL entry being located at the end address of memory access unit；
Judge whether memory access unit accommodates the 2nd FTL entry completely；
The FTL entry that record memory access unit completely accommodates.
10. the method for access FTL table clause according to claim 8, wherein slow in response to memory access unit to be loaded onto
It deposits, calculates the initial address of the initial address visiting memory cell with the accessed corresponding FTL entry of logical address in terms of bit
Poor d, the integer part that d/se obtains quotient indicates the FTL entry completely accommodated before the FTL entry in memory access unit
Quantity；
The end address of the end address visiting memory cell with the accessed corresponding FTL entry of logical address is calculated in terms of bit
Poor a, the integer part that a/se obtains quotient indicates the FTL entry completely accommodated after the FTL entry in memory access unit
Quantity；
The FTL entry completely accommodated before the FTL entry in record memory access unit is extremely completely held after the FTL entry
The logical address for the FTL entry received；
Wherein, se is the size of the FTL entry in terms of bit.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101788951A (en) * | 2008-08-15 | 2010-07-28 | 北京北大众志微系统科技有限责任公司 | Storage system and storage method thereof for network computer |
| CN103425600A (en) * | 2013-08-23 | 2013-12-04 | 中国人民解放军国防科学技术大学 | Address mapping method for flash translation layer of solid state drive |
| CN104268098A (en) * | 2014-08-28 | 2015-01-07 | 上海交通大学 | On-chip cache system for transformation on ultrahigh-definition video frame rates |
| CN104303162A (en) * | 2012-01-12 | 2015-01-21 | 才智知识产权控股公司(2) | Systems and methods for managing cache admission |
| CN104487952A (en) * | 2012-05-22 | 2015-04-01 | 网络装置公司 | Specializing i/o access patterns for flash storage |
| CN107229417A (en) * | 2016-03-25 | 2017-10-03 | 三星电子株式会社 | Data storage device and its operating method |
| CN107870867A (en) * | 2016-09-28 | 2018-04-03 | 北京忆芯科技有限公司 | 32 bit CPUs access the method and apparatus more than 4GB memory headrooms |
-
2018
- 2018-04-20 CN CN201810360299.XA patent/CN110389904A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101788951A (en) * | 2008-08-15 | 2010-07-28 | 北京北大众志微系统科技有限责任公司 | Storage system and storage method thereof for network computer |
| CN104303162A (en) * | 2012-01-12 | 2015-01-21 | 才智知识产权控股公司(2) | Systems and methods for managing cache admission |
| CN104487952A (en) * | 2012-05-22 | 2015-04-01 | 网络装置公司 | Specializing i/o access patterns for flash storage |
| CN103425600A (en) * | 2013-08-23 | 2013-12-04 | 中国人民解放军国防科学技术大学 | Address mapping method for flash translation layer of solid state drive |
| CN104268098A (en) * | 2014-08-28 | 2015-01-07 | 上海交通大学 | On-chip cache system for transformation on ultrahigh-definition video frame rates |
| CN107229417A (en) * | 2016-03-25 | 2017-10-03 | 三星电子株式会社 | Data storage device and its operating method |
| CN107870867A (en) * | 2016-09-28 | 2018-04-03 | 北京忆芯科技有限公司 | 32 bit CPUs access the method and apparatus more than 4GB memory headrooms |
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