CN108595349A - The address conversion method and device of mass-memory unit - Google Patents
The address conversion method and device of mass-memory unit Download PDFInfo
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- CN108595349A CN108595349A CN201810381624.0A CN201810381624A CN108595349A CN 108595349 A CN108595349 A CN 108595349A CN 201810381624 A CN201810381624 A CN 201810381624A CN 108595349 A CN108595349 A CN 108595349A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1009—Address translation using page tables, e.g. page table structures
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F12/1036—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation
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Abstract
The application provides the address conversion method and device of mass-memory unit, wherein, storage device includes address converting device, address converting device includes basic memory block, at least partly, the entry of address translation table has recorded logical address and the mapping relations of physical address to the entry of basic memory block storage address conversion table.
Description
Technical field
This application involves mass-memory unit more particularly to the address conversion methods and device of mass-memory unit.
Background technology
Fig. 1 illustrates the block diagram of solid storage device.Solid storage device (Solid State Drive, SSD) 102 is same
Host is coupled, for providing storage capacity for host.Host is the same as can phase coupling in several ways between solid storage device 102
It closes, coupled modes include but not limited to for example, by SATA (Serial Advanced Technology Attachment, string
Row Advanced Technology Attachment), SCSI (Small Computer System Interface, small computer system interface), SAS
(Serial Attached SCSI, Serial Attached SCSI (SAS)), IDE (Integrated Drive Electronics, integrated driving
Device electronics), USB (Universal Serial Bus, universal serial bus), PCIE (Peripheral Component
Interconnect Express, PCIe, peripheral component interconnection), NVMe (NVM Express, high speed non-volatile memory),
Ethernet, optical-fibre channel, cordless communication network etc. connect host and solid storage device 102.Host can be can be by upper
The information processing equipment that mode is communicated with storage device is stated, for example, personal computer, tablet computer, server, portable meter
Calculation machine, the network switch, router, cellular phone, personal digital assistant etc..Storage device 102 includes interface 103, control unit
Part 104, one or more NVM chips 105 and DRAM (Dynamic Random Access Memory, dynamic random-access
Memory) 110.
Nand flash memory, phase transition storage, FeRAM (Ferroelectric RAM, ferroelectric memory), MRAM (Magnetic
Random Access Memory, magnetoresistive memory), RRAM (Resistive Random Access Memory, resistance-change memory
Device) etc. be common NVM.
Interface 103 can be adapted to for example, by the side such as SATA, IDE, USB, PCIE, NVMe, SAS, Ethernet, optical-fibre channel
Formula and host exchanging data.
Control unit 104 is used to control the data transmission between interface 103, NVM chips 105 and DRAM 110, also
For storage management, host logical address to flash memory physical address map, erasure balance, bad block management etc..Control unit 104 can
It is realized by the various ways of software, hardware, firmware or combinations thereof, for example, control unit 104 can be FPGA (Field-
Programmable gate array, field programmable gate array), ASIC (Application Specific
Integrated Circuit, application specific integrated circuit) or a combination thereof form.Control unit 104 can also include place
Device or controller are managed, software is executed in processor or controller and carrys out the hardware of manipulation and control component 104 to handle IO
(Input/Output) it orders.Control unit 104 is also coupled to DRAM 110, and may have access to the data of DRAM 110.
DRAM can store the data of the I/O command of FTL tables and/or caching.
Control unit 104 includes flash interface controller (or being Media Interface Connector controller, flash memory channel controller), is dodged
It deposits interface controller and is coupled to NVM chips 105, and sent out to NVM chips 105 in a manner of following the interface protocol of NVM chips 105
Go out order, to operate NVM chips 105, and receives the command execution results exported from NVM chips 105.Known NVM chips connect
Mouth agreement includes " Toggle ", " ONFI " etc..
Data are usually stored and read on storage medium by page.And data are erased in blocks.Block (also referred to as physical block) packet
Containing multiple pages.Page (being known as Physical Page) on storage medium has fixed size, such as 17664 bytes.Physical Page can also
With other sizes.
In solid storage device, using FTL (Flash Translation Layer, flash translation layer (FTL)) come safeguard from
Map information of the logical address to physical address.Logical address constitutes the solid-state that the upper layer software (applications)s such as operating system are perceived and deposits
Store up the memory space of equipment.Physical address is the address of the physical memory cell for accessing solid storage device.In existing skill
Also implement address of cache using intermediate address form in art.Such as logical address is mapped as intermediate address, and then will be intermediate
Address is further mapped as physical address.For most of NVM storage mediums, the physical address for accessing it is such as page address.
The device for providing the conversion from logical address to physical address is referred to as FTL tables (also referred to as address translation table).FTL
Table is the important metadata in solid storage device.The data item of usual FTL tables has recorded in solid storage device with data page
For the address mapping relation of unit.The FTL tables of large capacity solid storage device have larger size, such as several GB.
FTL tables include multiple FTL table clauses (or list item).Application No. is 201510430174.6 Chinese patent Shens
Please in provide the examples of FTL table structures.In one example, had recorded in each FTL table clauses a logical page address with
The correspondence of one Physical Page.In another example, logical block address is had recorded in each FTL table clauses with physical block
The correspondence of location.In still another example, the mapping relations of logical block address and physical block address are recorded in FTL tables,
And/or the mapping relations of logical page address and physical page address.FTL table clauses can also record logical address and one or more
The mapping relations of physical address.
In still another example, FTL tables are stored in continuous memory address space, are remembered in each FTL table clauses
Physical address is recorded, and represents the logical address corresponding to physical address with the memory address of each FTL table clauses itself.FTL tables
Size of the quantity of entry dependent on solid storage device logical address space and the storage list representated by each FTL table clauses
The size of member.
It needs frequently to access FTL tables when the controller work of solid storage device.When reading NVM storage mediums, pass through
Logical address inquires FTL tables to obtain the physical address of the NVM storage mediums of storage data.When NVM storage mediums are written, it is
The data allocated physical address of write-in, and record in FTL the correspondence of the logical address and physical address of write-in.Occurring
When the operations such as GC (garbage reclamation), erasure balance, the mapping relations of logical address and physical address change, and need to update
FTL。
Have existed a variety of technical solutions for accessing FTL.It is carried in Chinese invention patent application CN 201610346104.7
FTL tables quick access method and device have been supplied, the present invention is incorporated by reference into.
Invention content
The characteristics of FTL tables include list item quantity more (several hundred million FTL table clauses are managed in common solid storage device),
Size small (about several to more than ten byte), the access randomness of each entry (are distributed in entirely the access of FTL table clauses by force
Table space and lack locality).And due to the solid storage device of large capacity to be supported, so being frequently necessary to be performed for more than
The access of the memory headroom of 4GB.
For GB grades of data of storage, generally using DRAM, (Dynamic Random Access Memory, dynamic random are visited
Ask memory).And the access delay of DRAM can not match CPU (Central Processing Unit, central processing unit) etc.
High speed processing component, and seriously affect the process performance of storage control.Traditionally, using Cache (cache memory)
As storage middle layer, high-speed data access ability is provided for CPU by caching the partial data in DRAM.
The address conversion method and its device for being designed to provide mass-memory unit of the application.
According to the application's in a first aspect, providing the first storage device according to the application first aspect, wherein including
Address converting device, address converting device include basic memory block, and the entry of basic memory block storage address conversion table is at least
The entry of part, address translation table has recorded logical address and the mapping relations of physical address.
According to the first storage device of the first aspect of the application, provide according to the second of the application first aspect the storage
Equipment, wherein logical address includes the Process identifier and virtual page address of non-overlapping copies, and Process identifier is for determining basis
The base address of memory block, virtual page address be used for determine address translation table entry at least partially in depositing in basic memory block
Storage space is set.
According to the first or second storage device of the first aspect of the application, according to the application first aspect is provided
Three storage devices, wherein flash memory conversion equipment further includes extension storage block；The entry of extension storage block storage address conversion table
Second part；The first part of the entry of address translation table and second part to be combined as same logical address corresponding physically
Location.
According to the third storage device of the first aspect of the application, provide according to the 4th of the application first aspect the storage
Equipment, wherein logical address includes extension storage block address and the offset of non-overlapping copies, and extension storage block address is for extending
Data cell is addressed in memory block, offset in data cell for determining second part.
According to the second to the 4th storage device of the first aspect of the application, according to the application first aspect is provided
Five storage devices, wherein the length of virtual page address is determined by the size that CPU is the virtual memory space that each process provides
It is fixed.
According to the second to the 5th storage device of the first aspect of the application, according to the application first aspect is provided
Six storage devices, wherein the length of Process identifier is determined by the quantity of basic memory block.
According to the first to the 6th storage device of the first aspect of the application, according to the application first aspect is provided
Seven storage devices, wherein at least one basis memory block is continuously placed in memory.
According to the first to the 6th storage device of the first aspect of the application, according to the application first aspect is provided
Eight storage devices, wherein at least one basis memory block is discontinuously placed in memory；Address converting device further includes process mark
Know symbol table, Process identifier table includes quantity Process identifier entry identical with the basic quantity of memory block, each process mark
Know the address of the basic memory block of symbol program recording one.
According to the second of the first aspect of the application or the 8th storage device, according to the application first aspect is provided
Nine storage devices, wherein Process identifier is the part that NameSpace identifier is indicated in logical address.
According to the 8th to the 9th storage device of the first aspect of the application, according to the application first aspect is provided
Ten storage devices, wherein the size of corresponding basic memory block is recorded in Process identifier entry.
According to the third of the first aspect of the application to the tenth storage device, according to the application first aspect is provided
11 storage devices, wherein extension storage block is a part for one of basic memory block.
According to the third of the first aspect of the application to the tenth storage device, according to the application first aspect is provided
12 storage devices, wherein extension storage block and basic memory block non-overlapping copies.
According to the third storage device of the first aspect of the application, provides and deposited according to the 13rd of the application first aspect the
Equipment is stored up, wherein extension storage block address overlaps each other with part of the virtual page address in logical address.
According to the second aspect of the application, the first memory management unit according to the application second aspect is provided, is used for
Logical address is converted into physical address, wherein memory management unit include the first page table and first bypass translation cache, first
At least partly, the first bypass translation cache stores the item being frequently used in the first page table to the entry storage physical address of page table
Mesh.
According to the first memory management unit of the second aspect of the application, second according to the application second aspect is provided
Memory management unit, wherein memory management unit further includes the second page table；The basis of the entry storage physical address of first page table
Address；The extended address of the entry storage physical address of second page table；Base address and extended address are combined as with logically
The corresponding physical address in location.
According to the second memory management unit of the second aspect of the application, the third according to the application second aspect is provided
Memory management unit, wherein memory management unit further includes the second bypass translation cache, the second bypass translation cache storage second
The entry being frequently used in page table.
According to the third aspect of the application, the first address conversion method according to the application third aspect is provided, wherein
Include the following steps：In response to receiving I/O Request, logical address is obtained from I/O Request；It is obtained physically according to logical address
The first part of location；The second part of physical address is obtained according to logical address；Combine first part and the physics of physical address
The second part of address, obtains physical address.
According to the first address conversion method of the third aspect of the application, second according to the application third aspect is provided
Address conversion method, wherein using the first part of logical address as Process identifier, and by the second part of logical address
As virtual page address；The base of the basic memory block of the table clause for storing flash memory conversion table is determined according to Process identifier
Location determines that the first part of physical address stores storage location in the block on basis, from basic memory block according to virtual page address
Read the first part of physical address.
According to the first address conversion method of the third aspect of the application, the third according to the application third aspect is provided
Address conversion method, wherein extract first part from logical address and extract second as Process identifier, and from logical address
Part is used as virtual page address；The basis of the table clause for storing flash memory conversion table is determined according to the first part of logical address
The base address of memory block determines that the first part of physical address stores in the block deposit on basis according to the second part of logical address
Storage space is set, and the first part of physical address is read from basic memory block.
According to the first of the third aspect of the application to third address conversion method, provide according to the application third aspect
The 4th address conversion method, wherein with the storage location in the Part III addressing extension memory block of logical address, and will
The Part IV of logical address is as deviant；It is read from extension storage block with Part IV according to the Part III of logical address
Go out the second part of physical address.
According to the 4th address conversion method of the third aspect of the application, the 5th according to the application third aspect is provided
Address conversion method, wherein address a data cell in extension storage block with the Part III of logical address, use deviant
The second part of physical address is determined in data cell.
According to the first to the 5th address conversion method of the third aspect of the application, provide according to the application third aspect
The 6th address conversion method, wherein logical address further includes the 5 with Process identifier and virtual page address non-overlapping copies
Part；Flash memory conversion method further includes：Physical address is combined with Part V, to address the data that I/O Request is accessed.
According to the first to the 6th address conversion method of the third aspect of the application, provide according to the application third aspect
The 7th address conversion method, wherein further include：The space size of recognition logic address；If the space size of logical address is big
In threshold value, then the second part of physical address is obtained；Otherwise, using the first part of physical address as physical address.
According to the first to the 7th address conversion method of the third aspect of the application, provide according to the application third aspect
The 8th address conversion method, wherein while obtaining the first part of physical address, obtain the second part of physical address.
According to the first address conversion method of the third aspect of the application, the 9th according to the application third aspect is provided
Address conversion method, wherein using the first part of logical address as Process identifier, and by the second part of logical address
As virtual page address；Process identifier and virtual page address are supplied to memory management unit；Memory management unit according into
Journey identifier and virtual page address inquire the first page table and obtain the first part of physical address.
According to the 9th address conversion method of the third aspect of the application, the tenth according to the application third aspect is provided
Address conversion method, wherein further include：Memory management unit turns according to Process identifier and the first bypass of virtual page address inquiry
Change caching；If Process identifier has hit the first bypass translation cache, the first bypass translation cache output with virtual page address
First physical page address of the entry being hit, the first part of the part of the first physical page address as physical address.
According to the first address conversion method of the third aspect of the application, the tenth according to the application third aspect is provided
One address conversion method, wherein using the first part of logical address as Process identifier, and by second of logical address
It is allocated as virtual page address；Process identifier and virtual page address are supplied to memory management unit；Memory management unit according to
Process identifier and virtual page address inquire the first page table and obtain first memory page address, according to first memory page address with
The Part VI of logical address obtains first memory address, accesses first memory address and obtains first of physical address
Point.
According to the 11st address conversion method of the third aspect of the application, according to the application third aspect is provided
Ten double-address conversion methods, wherein further include：Memory management unit is inquired according to Process identifier and virtual page address by the of first
Road translation cache；If Process identifier has hit the first bypass translation cache, the first bypass translation cache with virtual page address
First memory page address is exported, with obtaining first memory according to the Part VI of first memory page address and logical address
Location accesses first memory address and obtains the first part of physical address.
According to the tenth to the tenth double-address conversion method of the third aspect of the application, provide according to the application third party
13rd address conversion method in face, wherein further include：If the first bypass translation cache is hit, ignore from the first page table
It is middle to inquire obtaining as a result, terminating inquiry to the first page table.
According to the tenth to the 13rd address conversion method of the third aspect of the application, provide according to the application third party
14th address conversion method in face, wherein further include：If Process identifier and the bypass conversion of virtual page address miss first
Caching, then：At least one entry of first bypass translation cache is write back into the first page table；It is loaded with logically from the first page table
The corresponding entry of Process identifier and virtual page address of location simultaneously fills the Empty Entry in the first bypass translation cache；By in the of first
Road translation cache output corresponding second physical page address with the Process identifier and virtual page address of logical address, as physics
The first part of address.
According to the tenth to the 13rd address conversion method of the third aspect of the application, provide according to the application third party
15th address conversion method in face, wherein further include：If Process identifier and the bypass conversion of virtual page address miss first
Caching, then：At least one entry of first bypass translation cache is write back into the first page table；It is loaded with logically from the first page table
The corresponding entry of Process identifier and virtual page address of location simultaneously fills the Empty Entry in the first bypass translation cache；By in the of first
Road translation cache output corresponding first memory page address with the Process identifier and virtual page address of logical address, according to the
One memory page address and the Part VI of logical address obtain first memory address, access first memory address and obtain object
Manage the first part of address.
According to the 9th to the 15th address conversion method of the third aspect of the application, provide according to the application third party
16th address conversion method in face, wherein using the Part VII of logical address as extension storage block address, by it is specified into
Journey identifier and extension storage block address are supplied to memory management unit；According to specified Process identifier and extension storage block
Location is from extension storage block output data unit；The of physical address is obtained from data cell according to the Part VIII of logical address
Two parts.
According to the 9th to the 15th address conversion method of the third aspect of the application, provide according to the application third party
17th address conversion method in face, wherein extract Part IX as extension storage block address from logical address, and will specify
Process identifier and extension storage block address be supplied to memory management unit；According to specified Process identifier and extension storage
Second page table of block address audit memory administrative unit obtains data cell, according to the Part X of logical address from data cell
The middle second part for obtaining physical address.
According to the 17th address conversion method of the third aspect of the application, according to the application third aspect is provided
18 address conversion methods, wherein further include：While inquiring the second page table, deposited according to specified Process identifier and extension
Store up block address inquiry the second bypass translation cache；If the first bypass translation cache and the second bypass translation cache are hit,
The third physical page address for the entry that first bypass translation cache output is hit, the first part as physical address；Second
4th physical page address of the entry that bypass translation cache output is hit, using the part of the 4th physical page address as physically
The second part of location.
According to the second of the third aspect of the application to eighteenthly location conversion method, provide according to the application third party
19th address conversion method in face, wherein Process identifier is the part that NameSpace identifier is indicated in logical address.
According to the fourth aspect of the application, provides and be situated between according to the first storage for storing program of the application fourth aspect
Matter, wherein be loaded into processor operation in response to program, program makes processor execute above-mentioned flash memory conversion method.
The embodiment of the present application provides the address conversion of mass-memory unit using address converting device, reduces data
Access delay improves the processing speed of address translation process.
Description of the drawings
In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, to embodiment or will show below
There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments described in application can also be obtained according to these attached drawings other attached for those skilled in the art
Figure.
Fig. 1 is the block diagram of solid storage device in the prior art；
Fig. 2 is the schematic diagram according to the address converting device of the embodiment of the present application one；
Fig. 3 illustrates the flow chart that logical address is converted to physical address according to the embodiment of the present application two；
Fig. 4 illustrates the flow chart that logical address is converted to physical address according to the embodiment of the present application three；
Fig. 5 illustrates the schematic diagram of the address converting device according to the embodiment of the present application four；And
Fig. 6 illustrates the flow chart that logical address is converted to physical address according to the embodiment of the present application five.
Specific implementation mode
With reference to the attached drawing in the embodiment of the present application, technical solutions in the embodiments of the present application carries out clear, complete
Ground describes, it is clear that described embodiment is some embodiments of the present application, instead of all the embodiments.Based on the application
In embodiment, the every other embodiment that those skilled in the art are obtained without making creative work, all
Belong to the range of the application protection.
Embodiment one
Fig. 2 is the schematic diagram according to the address converting device of the embodiment of the present application one.Embodiment according to fig. 2, address turn
Changing device is used to the logical address 210 of input being converted to physical address 220.Logical address is that solid storage device is presented to use
The index of the memory space at family, and NVM chip of the physical address for indexing solid storage device and physical storage block thereon
With the data cell on page or memory block.For purpose that is clear and illustrating, the physical address of address converting device output
Indicate that Physical Page, each physical address include 34 bits, each logical address includes 46 bits, and low 12 bit of logical address is used
High 34 bit of addressing data in data cell (for example, Physical Page), logical address is used for the determination data sheet to be accessed
Member.Address converting device obtains the physical address of 34 bits according to high 34 bit of logical address.It is to be appreciated that address conversion
The size of the input logic address of device, output physical address and/or data cell can have other sizes.
Storage address conversion table (safeguarding the map information from logical address to physical address) in main memory.Referring to Fig. 2, basis
The entry of memory block (240,242,244,246) storage address conversion table, and in main memory.Basic memory block (240,242,
244,246) size is several GB (gigabyte, Giga Byte), such as 2GB.The data structure of address translation table is known
, to according to logical address, obtain storing (at least partly) object corresponding to the entry of the logical address in main memory
Manage address.In one example, address translation table is stored with plane (Flat) structure, has recorded the address conversion of logical address L
The entry of table is stored at physical address (B+L*4), and wherein B indicates the base address of basic memory block where address translation table, and
Address conversion table clause for each logical address occupies 4 bytes of storage space.In another example, address translation table with
Tree structure stores.The leaf node of tree has recorded the entry of address translation table, and nonleaf node has recorded address conversion table clause
Index.Tree structure is traversed by logical address L, to obtain the object of the corresponding address conversion table clauses of record logical address L
Manage address.
Embodiment according to fig. 2, basic memory block (240,242,244,246) have 8 (to show 4 in Fig. 2, remaining is not
Show), the size of each basis memory block is 2GB.Logical address order recording address is pressed with planar structure in basic memory block
The entry of conversion table.The part memory space of basic memory block 240 be provided to spread foundation memory block (260,262,264,
266).Each of spread foundation memory block program recording corresponds to the part ratio of the physical address of one of address conversion table clause
It is special.As an example, the size of each entry of spread foundation memory block is 2 bits.The entry of spread foundation memory block presses logic
Sequence of addresses arranges, to according to logical address, can be expanded stored in basic memory block correspond to the logical address
Entry 2 bit physical addresses.
Logical address 210 includes the multiple portions of non-overlapping copies, be denoted as respectively Process identifier PID, virtual page address with
Page bias internal.As an example, the parts PID are 3 bits (for example, 3 bit of highest of logical address 210), virtual page address part
For 29 bits (for example, time high 29 bit of logical address 210), page bias internal part is 12 bits (for example, logical address 210
Minimum 12 bit).Embodiment according to fig. 2, address converting device determine storage address conversion table according to the PID of logical address
One of the basic memory block (240,242,244,246) of entry, and the entry of address translation table is determined according to virtual page address
Storage location (offset of the base address relative to basic memory block) in basic memory block.The entry of access address conversion table
32 bit datas are exported, the base address as physical address 220.
Logical address 210 is also used for the entry of addressing extension memory block.Logical address 210 is divided into extension storage block address
(for example, 30 bit of highest of logical address 210) and byte bias internal (for example, minimum 2 bit of logical address 210).Extension
MBA memory block address overlaps each other with part of the virtual page address in logical address.To which extension storage block address is for amounting to
Data cell (a such as byte) is addressed in the extension storage block of memory space 1GB, and byte bias internal is for determining the data sheet
Extended address of 2 bits as physical address 220 in member.
It will be appreciated by those skilled in the art that ground, solid storage device can provide the memory space of other sizes, have difference
The data cell of quantity.And accordingly the size of the various pieces of adjustment logical address 210, basic memory block in memory it is big
The size of extension storage block small, in memory, to complete from logical address to the conversion of the physical address for NVM chips.
Embodiment according to fig. 2, it is the virtual memory that each process provides that the size (2GB) of basic memory block, which is CPU,
The size in space, and determine therefrom that the length of the virtual page address part of logical address 210 (for being addressed in basic memory block
Basic memory block entry).The length of the parts PID of logical address 210 is dependent on the basic memory block for accommodating address translation table
Quantity so that PID is for addressing one of basic memory block.The number of entries of all basis memory blocks is address conversion table clause
Quantity is also equal to the quantity of the entry of extension storage block.The part (extension storage address and byte bias internal) of logical address 210
It is also used to address that the entry of extension storage block.Combination foundation memory block entry and the entry of extension storage block obtain physical address,
To the size of the entry and the entry of extension storage block of adjustable basic memory block.For example, physical address is 34 bits, and base
Plinth memory block entry is 32 bits, and extension storage block entry is 2 bits.Obviously, basic memory block entry is set to 32 bits,
It is consistent with the data-bus width of general CPU, be conducive to by CPU access and data transmission.It is appreciated that basic memory block
Entry, the length of the entry of extension storage block can be other sizes.
In one embodiment, multiple basic memory blocks are continuously placed in memory, to which the value according to PID can be counted
Calculate the base address of corresponding basic memory block.And in another embodiment, multiple basis memory blocks are not connected in memory
It is continuous to place, to which continuous bulk memory space need not be used to accommodate basic memory block, and use Process identifier table
(PID tables) (including entry 280,282,284 and 286) records the base address of the corresponding basic memory blocks of each PID.For example, item
Mesh 280 records the base address of basic memory block 240, and entry 282 records the base address of basic memory block 242, and entry 284 records base
The base address of plinth memory block 244, entry 286 record the base address of basic memory block 246.With PID index PID tables, corresponded to
The base address of basic memory block.
Still optionally, PID, virtual page address, basic MBA memory block address and/or byte bias internal can be located at logical address
210 a variety of positions.
In alternative embodiments, NameSpace identifier will be indicated in logical address 210 or I/O Request
The part of (NameSpace ID, NSID) obtains the base address of basic memory block as PID with PID index PID tables.Due to making
With PID tables so that basic memory block can respectively have different sizes.It is deposited according to based on the index that PID tables obtain
The base address of storage block obtains corresponding entry, as physically according to virtual page address as deviant from basic memory block
Some or all of location.Further, the size that corresponding basic memory block is recorded also in the entry of PID tables is (acceptable inclined
Shifting value), if the virtual page address used has exceeded the size of basic memory block, prevent this logical address space to NSID
Out-of-bounds access.
In the embodiment of Fig. 2, extension storage block is located in basic memory block 240, and the storage for occupying basic memory block 240 is empty
Between.The ranges of logical addresses corresponding to memory space that basic memory block 240 is occupied is not applied to user's access.Optionally,
Extension storage block and basic memory block be not be overlapped in memory headroom.
Embodiment two
Fig. 3 illustrates the flow chart that logical address is converted to physical address according to the embodiment of the present application two.It can be by CPU
Flow chart shown in software or memory management unit (MMU, Memory Management Unit) implementing Fig. 3 is executed, and is applied
In the address converting device of embodiment according to fig. 2.
As shown in figure 3, logical address be converted to physical address including：IO in response to receiving access storage device is asked
It asks, logical address (310) is obtained from I/O Request.Using the specified portions of logical address as PID, and by the another of logical address
One specified portions are as virtual page address.Specifically, it is used as PID from logical address extraction specified portions (for example, 3 bit of highest)
(referring also to Fig. 2), and from logical address extract another specified portions (for example, secondary high 29 bit) as virtual page address (
Referring to Fig. 2).The base address that the basic memory block of the entry for storage address conversion table is determined according to PID, uses virtual page address
The storage location that the entry of address translation table is determined in basic memory block, the data read from basic memory block turn as address
Change the entry of table at least partly, the first part (320) as physical address.Also use the part of logical address (for example, highest
32 bits) index extension storage block, the data read from the entry of extension storage block as address translation table entry again
A part, the second part (350) as physical address.
For example, with the storage location (a such as data cell) in 31 bit address extension storage blocks of logical address, with
And using other 3 bit of logical address as deviant, accessed data are determined in the data cell with deviant, from expansion
Second part of the data read in exhibition memory block as physical address.
Two parts for splicing and combining the address conversion table clause of reading, as physical address (360).The physical address indicates
The physical address of NVM chips used in the data cell that I/O Request is accessed.Optionally, also by the physical address with logically
Other bits (such as Physical Page bias internal) of location splice, to address the data in the data cell that I/O Request is accessed.
Still optionally, step 320 and step 350 may be performed simultaneously.
Embodiment three
Fig. 4 illustrates the flow chart that logical address is converted to physical address according to the embodiment of the present application three.Such as Fig. 4 institutes
Show, logical address, which is converted to physical address, includes：Logical address (410) is obtained from I/O Request.By the specified of logical address
Part is used as PID, and using another specified portions of logical address as virtual page address.Specifically, it is extracted from logical address
Specified portions (for example, 3 bit of highest) are used as PID (referring also to Fig. 2), and extract another specified portions (example from logical address
Such as, secondary high 29 bit) it is used as virtual page address (referring also to Fig. 2).The basis of the entry of storage address conversion table is determined according to PID
The base address of memory block determines the storage location of the entry of address translation table with virtual page address, from base in basic memory block
Part of the data that plinth memory block is read as the entry of address translation table, the first part (420) as physical address.From base
The size (for example, 32 bits) for the data that plinth memory block is read determines addressable memory space.
Identify the size (430) of the logical address space of current solid storage device.If logical address space size is little
In threshold value (threshold value is the addressable maximum memory space of size of the data for example read from basic memory block, such as 2TB), then
The data read from basic memory block have represented complete physical address, turn the data read from basic memory block as address
The physical address (440) of changing device output.Optionally, data are specified in the data filling also to be read from basic memory block, with full
The call format of sufficient physical address, for example, dosing one or more 0 before reading data.
If the size of the logical address space of current solid-state storage is more than threshold value (430), the part of logical address is also used
(for example, 32 bit of highest) indexes extension storage block, and the data read from the entry of extension storage block are as address translation table
Entry another part, the second part (450) as physical address.Splice and combine the entry of the address translation table of reading
Two parts, as physical address (460).NVM chips used in the data cell that physical address instruction I/O Request is accessed
Physical address.
Example IV
Address converting device be used to be converted to the logical address of I/O Request physics (page) address of NVM media.And show
Effect for the MMU (memory management unit) of CPU is that the virtual address of process is converted to memory physical page address (page frame
Location).According to an embodiment of the present application, promote turning for the physical address from the logical address of I/O Request to NVM media using MMU
Change process.
Fig. 5 illustrates the schematic diagram of the address converting device according to the embodiment of the present application four.
As shown in figure 5, the logical address 510 of I/O Request to be converted to the physical address 520 of NVM media with MMU, with reality
The function of existing address converting device.MMU includes page table and TLB (Translation Lookaside Buffer, the side of its management
Road translation cache).The mapping relations of virtual page address (virtual page number) and the physical page address of NVM media are had recorded in page table.
It is supplied to MMU to carry out query page using the virtual page address part of the logical address 510 of I/O Request as index in response to I/O Request
Table, using the physical page address found from page table as the output of MMU.It is updated in response to the entry of address translation table, in MMU
Page table in record updated virtual page address and the mapping relations of physical address, for subsequent inquiry.
The TLB of MMU has recorded the partial entry of page table.For example, recording the entry of page table being frequently used in TLB.TLB
With hardware realization, to relative to the faster response speed of memory access.Usually, the number of entries of TLB is less, with
Only accommodate the partial entry of page table and not all.It influences in I/O Request, in addition to the virtual page of the logical address 510 with I/O Request
Location partial query page table, MMU also concurrently use virtual page address partial query TLB.If having recorded the virtual page in the entry of TLB
Address, TLB provide response by rapid, and the physical page address for the entry that TLB outputs are hit, the physical page address is as MMU's
Output, the part as physical address.To which page table walks result need not be waited for again.If TLB miss, with looking into for page table
Result is ask as output.And optionally, the query result of page table is also used to replace the entry of TLB, to inquire TLB next time
When, TLB can be hit.
Optionally, page table and/or TLB are also the mapping relations that each process has recorded its virtual page and physical page address,
To which multiple processes can respectively monopolize complete virtual address space (for example, maximum 2GB).Process identifier is CPU, MMU, behaviour
Make system etc. for distinguishing identifier used in process.According to an embodiment of the present application, by the specified portions of logical address 510
As Process identifier (PID), another specified portions of logical address 510 are used as virtual page address (referring also to Fig. 2), so that
Use MMU.
In response to I/O Request, the Process identifier of logical address and virtual page address are all supplied to MMU.MMU is according to PID
Choose with the PID corresponding page table, be used in combination virtual page address inquiry with the PID corresponding page table, with obtain physical page address or
Physical page address is at least partly.And each entry of TLB also records the PID belonging to the entry, is only recorded when TLB entry
When PID is hit with virtual page address, which is just hit.When page table entries and TLB entry are updated, also identify
PID corresponding to entry.
Optionally, MMU obtains memory page address according to PID and virtual page address inquiry page table, according to storage page
The specified portions of location and logical address obtain storage address, access storage address and obtain the first part of physical address.
If PID and virtual page address have hit TLB, TLB output storage page address, according to memory page address with patrol
The specified portions for collecting address obtain storage address, access storage address and obtain the first part of the physical address.
Optionally, the virtual address space that the page table of MMU is presented is divided into multiple portions.It is generated according to from logical address
PID and virtual page address, access the first part of virtual address space；And the memory number to be accessed according to the program of operation
PID and virtual page address are generated according to address, accesses the second part of Virtual Space.To which program accesses storage in a uniform manner
Device data and the data in solid storage device.The Data Storage Models for simplifying information processing equipment, reduce program development
Complexity.
Still optionally, some I/O Requests indicate NSID (NameSpace ID, NameSpace identifier, for example,
It is defined in NVMe agreements).NSID is used as PID.To which MMU is that each NSID safeguards corresponding page table and/or TLB entry.
Further, specified according to the priority of NSID or user, the quantity of the resources such as TLB entry is distributed for each NSID, with for
NSID provides the service quality of differentiation.
In another embodiment, the size of the NVM page address of TLB entry record is not limited by data-bus width, from
And accommodate complete physical address 520.In response to TLB hit, TLB exports complete physical address 520 and is filled as address conversion
The address conversion result set.
In still another embodiment, the entry size of the first page table can not accommodate full physical address 520.For example,
Physical address 520 has 34 bits, and the entry size of the first page table is 32 bits to adapt to the width of data/address bus.By first page
The part for the physical address that the entry of table is recorded is known as base address (referring also to Fig. 2).MMU also safeguards the second page table.Second
Part (such as 2 ratios not accommodated by the entry of the first page table in each of page table program recording logical address and physical address
It is special) mapping relations of (being known as extended address, referring also to Fig. 2).In response to I/O Request, MMU is also looked into the logical address of I/O Request
The second page table is ask, to obtain with logical address corresponding extended address.Base address and extended address are combined as physical address
520。
Still optionally, MMU includes the 2nd TLB.2nd TLB caches the partial entry of the second page table, such as stores second
The entry being frequently used in page table.Article program recording extended address of 2nd TLB.Or and logical address is made to hit simultaneously
One TLB and the 2nd TLB or the first TLB and the 2nd TLB are not hit by and are advantageous.When the first TLB is replaced, also phase
Associatedly replace the 2nd TLB.
Embodiment five
Fig. 6 illustrates the flow chart that logical address is converted to physical address according to the embodiment of the present application five.
As shown in fig. 6, logical address be converted to physical address including：Logical address (610) is obtained from I/O Request.Point
The first part (base address) (620) (referring also to Fig. 2) of physical address is not obtained according to logical address, and according to logically
Location obtains the second part (extended address) (650) (referring also to Fig. 2) of physical address.For example, being looked into logical address or part thereof
Basic memory block is ask to obtain base address, and with logical address or part thereof query expansion memory block to obtain extended address.
And combine first part's (base address) of physical address with second part (extended address), it obtains same logical address and corresponds to
Physical address (660).And the NVM storage mediums of solid storage device are accessed with physical address.Wherein, step 620 and step
Rapid 650 can be executed in parallel.
The part of logical address is supplied to obtain the first part (620) of physical address according to the embodiment of Fig. 6
MMU.For example, the first part (referring also to Fig. 2, PID) of logical address is supplied to MMU as Process identifier, and by logic
The second part (referring also to Fig. 2, virtual page address) of address is supplied to MMU (630) as virtual page address.MMU is according to process
Identifier inquires page table, and the first part (basis by the output of page table as the physical address of NVM media with virtual page address
Address) (634).
MMU is additionally in response to receive PID and virtual page address, also inquires whether TLB hits (640).If the PID of logical address
TLB is hit with virtual page address, then the physical page address (642) for the program recording that TLB outputs are hit.MMU exports TLB
Physical page address as NVM media physical address first part (base address) (634), and ignore and inquired from page table
It is obtaining as a result, terminate page table query process.
If the PID of logical address and virtual page address miss TLB, optionally, TLB entry (644) is replaced.
Optionally, it includes that one or more entries of TLB are write back page table to replace TLB entry, idle to be generated in TLB
Entry entry corresponding with virtual page and fills the Empty Entry in TLB from load in page table with the PID of logical address.TLB is also
It exports and loads the physical page address (646) that entry corresponding with virtual page is recorded with the PID of logical address from page table.MMU
Using the physical page address of TLB outputs as the first part (base address) (634) of the physical address of NVM media.
Still optionally, it includes that one or more entries of TLB are write back page table to replace TLB entry (644), in TLB
Middle generation Empty Entry loads the entry corresponding with virtual page with the Process identifier of logical address from page table and fills TLB
In Empty Entry.TLB also export from page table load with the PID of logical address first memory page corresponding with virtual page
Location obtains first memory address according to the specified portions of first memory page address and logical address, accesses first memory
Address obtains the first part (base address) (634) of physical address.
Optionally or further, to obtain the second part (650) of physical address, also the part of logical address is provided
To MMU.
Optionally, using the specified portions extracted from logical address as extension storage block address, and by PID and extension storage
Block address is supplied to MMU.MMU is according to PID and extension storage block address from extension storage block output data unit.According to logically
Another specified portions of location obtain the second part of physical address from data cell.
Still optionally, specified portions are extracted as extension storage block address, and by PID and extension storage from logical address
Block address is supplied to MMU.The second page table that MMU is inquired according to PID and extension storage block address, obtains data cell, according to patrolling
Another specified portions of volume address obtain the second part of the physical address for the NVM media that MMU is exported from data cell.
Still optionally, while inquiring the second page table, the 2nd TLB is inquired according to PID and extension storage block address.If the
One TLB and the 2nd TLB are hit, then the physical page address of entry that the first TLB outputs are hit, and the as physical address
A part, the physical page address for the entry that the 2nd TLB outputs are hit, the second part as physical address.MMU combines NVM
The second part of the first part of the physical address of medium and the physical address of NVM media, to obtain physical address.
It should be understood that the combination of the frame of each frame and block diagram and flow chart of block diagram and flow chart can be respectively by including
The various devices of computer program instructions are implemented.These computer program instructions can be loaded into all-purpose computer, special meter
To generate machine on calculation machine or other programmable data control devices, in computer or other programmable data control devices
The instruction of upper execution creates for realizing the device for the function of being specified in one or more flow chart box.
These computer program instructions, which can also be stored in, can guide computer or other programmable data control devices
Computer-readable memory in working in a specific way, so as to using being stored in computer-readable memory
Instruction manufacture including the product for realizing the computer-readable instruction of specified function in one or more flow chart box.
Computer program instructions can also be loaded on computer or other programmable data control devices so that computer or its
A series of operation operation is executed on his programmable data control device, to generate computer implemented process, and then is being counted
The instruction executed on calculation machine or other programmable data control devices provides for realizing institute in one or more flow chart box
The operation of specified function.
Thus, the frame of block diagram and flow chart supports the combination of the device for executing specified function, for executing specified work(
The combination of the combination of the operation of energy and the program instruction means for executing specified function.It should also be understood that block diagram and flow chart
Each frame and the combination of the frame of block diagram and flow chart can specify functions or operations, hardware based special meters by executing
Calculation machine system is realized, or is realized by the combination of specialized hardware and computer instruction.
Although the example of present invention reference is described, it is intended merely to the purpose explained rather than to the limit of the present invention
System, the change to embodiment, increase and/or deletion can be made without departing from the scope of the present invention.
In field involved by these embodiments, benefiting from the description above with the introduction presented in associated attached drawing
Technical staff will be recognized that record here the present invention it is many change and other embodiment.It should therefore be understood that this hair
It is bright to be not limited to disclosed specific implementation mode, it is intended to will to change and other embodiment includes in the scope of the appended claims
It is interior.Although using specific term herein, them are used only on general significance and describing significance and not is
The purpose of limitation and use.
Claims (10)
1. a kind of storage device, including address converting device, described address conversion equipment includes basic memory block, basic memory block
At least partly, the entry of address translation table has recorded the mapping of logical address and physical address to the entry of storage address conversion table
Relationship.
2. storage device according to claim 1, which is characterized in that the logical address includes the process mark of non-overlapping copies
Know symbol and virtual page address, the Process identifier is used to determine the base address of the basic memory block, the virtual page address
For determine described address conversion table entry at least partially in the storage location in the basic memory block.
3. storage device according to claim 1 or 2, which is characterized in that the flash memory conversion equipment further includes that extension is deposited
Store up block；
The second part of the entry of the extension storage block storage described address conversion table；
The first part of the entry of described address conversion table is combined as the corresponding physics with the logical address with second part
Address.
4. storage device according to claim 3, which is characterized in that the logical address includes that the extension of non-overlapping copies is deposited
Block address and offset are stored up, the extension storage block address in the extension storage block for addressing data cell, the offset
For determining the second part in the data cell.
5. storage device according to claim 2, which is characterized in that the Process identifier is the logical address middle finger
Show the part of NameSpace identifier.
6. a kind of memory management unit, for logical address to be converted to physical address, which is characterized in that the memory management list
Member includes the first page table and the second page table；
The entry of first page table stores the base address of the physical address；The entry of second page table stores the object
Manage the extended address of address；
The base address and the extended address are combined as the corresponding physical address with the logical address.
7. a kind of address conversion method, which is characterized in that include the following steps：
In response to receiving I/O Request, logical address is obtained from the I/O Request；
The first part of physical address is obtained according to the logical address；
The second part of physical address is obtained according to the logical address；
The second part for combining the first part and the physical address of the physical address, obtains physical address.
8. address conversion method according to claim 7, which is characterized in that using the first part of the logical address as
Process identifier, and using the second part of the logical address as virtual page address；
The base address that the basic memory block of the table clause for storing flash memory conversion table is determined according to the Process identifier, according to
The virtual page address determines that the first part of the physical address stores storage location in the block on the basis, from the base
Plinth memory block reads the first part of the physical address.
9. address conversion method according to claim 7 or 8, which is characterized in that with the Part III of the logical address
Storage location in addressing extension memory block, and using the Part IV of the logical address as deviant；
According to the Part III of the logical address and Part IV the physical address is read from the extension storage block
Second part.
10. according to the address conversion method described in any one of claim 7-9, which is characterized in that further include：
Identify the space size of the logical address；
If the space size of the logical address is more than threshold value, the second part of physical address is obtained；Otherwise, by the physics
The first part of address is as the physical address.
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| PCT/CN2018/095995 WO2019128200A1 (en) | 2017-12-28 | 2018-07-17 | Address translation method and apparatus for mass storage device |
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| WO2019128200A1 (en) | 2019-07-04 |
| CN111061655B (en) | 2022-06-17 |
| CN108595349B (en) | 2020-01-31 |
| CN111061655A (en) | 2020-04-24 |
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