CN105005510A - Error correction protection architecture and method applied to resistive random access memory cache of solid state disk - Google Patents
Error correction protection architecture and method applied to resistive random access memory cache of solid state disk Download PDFInfo
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
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Abstract
The invention discloses an error correction protection architecture and method applied to the resistive random access memory cache of a solid state disk. The code length of a mapping table under coarse granularity management is the same as the code length of page cache data; in the data processing process, mapping table address information of which the access frequency is greater than a preset value in the mapping table under coarse granularity management is stored into a mapping table cache under fine granularity management; exchange data between the mapping table cache under fine granularity management and the mapping table under coarse granularity management is in units of pages; a page of mapping table information read out from the mapping table under coarse granularity management is completely put into the mapping table cache under fine granularity management, the posterior ten bits in an input logic address request are taken as offset bits, and the left bits in the input logic address are taken as index bits. According to the error correction protection architecture and method applied to the resistive random access memory cache of the solid state disk, the mapping table address information can be obtained and read out efficiently and reliably while the consumed redundant space is limited.
Description
Technical field
The invention belongs to nonvolatile memory resistance-variable storing device design field, relate to a kind of the error correction protection architecture and the method that are applied to solid state hard disc resistance-variable storing device buffer memory.
Background technology
Buffer memory in solid state hard disk system effectively can reduce the access of main frame to flash memory, the performance improving whole system is played an important role, there is large leakage current in traditional buffer memory based on dynamic RAM, power-off drop-out, the problems such as high quiescent dissipation, it is high that nonvolatile memory resistance-variable storing device has density, read or write speed is fast, the advantages such as low-power consumption, be considered to the desirable replacer of dynamic RAM in solid state hard disk system, but there is the problem of reliability in resistance-variable storing device, especially the resistance-variable storing device storer of cross array structure, along with the increase of array length, crosstalk can be increasing, integrity problem is more outstanding.
Along with the development of nonvolatile memory, nonvolatile memory is used to become practical as the buffer memory of External memory equipment, the user data of buffer memory is mainly deposited in typical buffer memory, other data such as map information (Physical page number is called for short PPN) and a small amount of firmware.
As everyone knows, memory devices only has user's bit error rate lower than 10
-15just can meet consumers' demand, although resistance-variable storing device buffer memory raw bit error rate is high, it can be made to meet the requirement of user's bit error rate by the protection of error correcting code.According to error correcting code encoding and decoding principle, code length more long code rate higher so error correcting code redundancy is less, and such as, bit error rate is 10
-4, adopt traditional galois field be 2 BCH encoding and decoding, need the redundancy of 30bit when code length is 4B, and same raw bit error rate, code length is that 4KB redundancy needs 416bit, so ecc code length its redundancy different differs greatly.
Summary of the invention
The object of the invention is to the shortcoming overcoming above-mentioned prior art; provide a kind of the error correction protection architecture and the method that are applied to solid state hard disc resistance-variable storing device buffer memory; this framework and method can obtain efficiently, reliably and read mapping table address information, and the redundant space consumed is limited.
For achieving the above object, the code length being applied to the mapping table of the management of coarseness in the error correction protection architecture of solid state hard disc resistance-variable storing device buffer memory of the present invention is identical with the code length of caching of page data, in data processing, mapping table address information access frequency in the mapping table of coarseness management being greater than preset value is stored in the mapping table buffer memory of fine granularity management, the entry of the mapping table of a coarseness management is spelled by 1024 address mapping table and is formed, each entry in the mapping table buffer memory of fine granularity management all comprises the error correcting code redundancy of a map information and a map information,
Exchange data between the mapping table that the mapping table buffer memory of fine granularity management and coarseness manage are in units of page, one page map information read in the mapping table managed from coarseness is all placed in the mapping table buffer memory of fine granularity management, wherein, one page map information is spliced by 1024 map information, using input logical address request in rear 10 as bits of offset, using input logical address in remaining bit as index bit.
The error correction guard method being applied to solid state hard disc resistance-variable storing device buffer memory of the present invention comprises the following steps:
The logical address request of input is divided into index bit and bits of offset, the mapping table buffer memory of fine granularity management is searched by index bit, when the logical address request inputted hits in the mapping table buffer memory that fine granularity manages, then from the page comprising request map information, read corresponding mapping table address information according to the offset address request of input; When the logical address request inputted does not hit in the mapping table buffer memory that fine granularity manages, then from the mapping table of coarseness management, find out the page comprising request map information, when the mapping table of fine granularity management is cached with space, then direct will in the mapping table managed from coarseness read comprise request map information page, and by read comprise request map information page by fine granularity operating strategy write fine granularity management mapping table buffer memory in; Space is not had in the mapping table buffer memory of fine granularity management, last page in the mapping table buffer memory then fine granularity managed according to coarse-grained policies writes back in the mapping table of coarseness management, and then the page comprising request map information is write in the mapping table buffer memory of fine granularity management according to fine granularity operating strategy, finally from the page comprising request map information, read corresponding mapping table address information according to offset address request.
The mapping table buffer memory of fine granularity management can the mapping table address information of buffer memory multiple pages, wherein, the mapping table address information of every one page is flash memory physical address corresponding to 1024 continuous logic addresses, and the logical address that first flash memory physical address in the mapping table address information of every one page is corresponding is the logical address index of this page;
When the logical address request of accessing hits in the mapping table buffer memory that fine granularity manages, then obtain required address map information position according to the first address of storage address map information, the size of each address information entry and page bias internal in call number corresponding to index bit, resistance-variable storing device, wherein, the size of size × 1024 × call number+page bias internal × each address information entry of first address+each address information entry of storage address map information in required address map information position=resistance-variable storing device.
The size of each address information entry is made up of with the error correcting code of this address mapping information is superfluous an address mapping information.
Directory entry is stored into the static RAM of solid state hard disk system, cached data mapping table and mapping table buffer memory index array are stored in the SRAM of solid state hard disk system, and address mapping table information is stored in the outer buffer memory resistance-variable storing device of sheet of solid state hard disk system.
The present invention has following beneficial effect:
Of the present invention be applied to solid state hard disc resistance-variable storing device buffer memory error correction protection architecture and method when operating; the code length of the mapping table of coarseness management is identical with the code length of caching of page data; and mapping table address information larger for access frequency is stored in the mapping table of fine granularity management; the loss of great minimizing error correction redundancy, ensures the speed of mapping table access simultaneously.In addition, the entry of the mapping table of a coarseness management is spelled by 1024 address mapping table and is formed, exchange data between the mapping table simultaneously managed in mapping table buffer memory and the coarseness of fine granularity management are in units of page, one page map information is spliced by 1024 map information simultaneously, thus effectively improves the hit rate of mapping table buffer memory.To sum up, The present invention reduces error correcting code redundant space loss in mapping table and in turn ensure that speed, have remarkable lifting to overall solid state hard disk system performance.
Further, the logical address that first flash memory physical address in the mapping table address information of every one page is corresponding is the logical address index of this page, and the effective speed improving index, reduces the error rate of index.
Accompanying drawing explanation
Fig. 1 is structural drawing of the present invention;
Fig. 2 is process flow diagram of the present invention;
Fig. 3 is the management structure figure of the mapping table buffer memory of fine granularity management in the present invention;
Fig. 4 is the hybrid error correction protection solid state hard disk system Organization Chart of index array on sheet.
Embodiment
Below in conjunction with accompanying drawing, the present invention is described in further detail:
With reference to figure 1, the code length being applied to the mapping table of the management of coarseness in the error correction protection architecture of solid state hard disc resistance-variable storing device buffer memory of the present invention is identical with the code length of caching of page data, in data processing, mapping table address information access frequency in the mapping table of coarseness management being greater than preset value is stored in the mapping table buffer memory of fine granularity management, the entry of the mapping table of a coarseness management is spelled by 1024 address mapping table and is formed, each entry in the mapping table buffer memory of fine granularity management all comprises the error correcting code redundancy of a map information and a map information, exchange data between the mapping table that the mapping table buffer memory of fine granularity management and coarseness manage are in units of page, one page map information read in the mapping table managed from coarseness is all placed in the mapping table buffer memory of fine granularity management, wherein, one page map information is spliced by 1024 map information, using input logical address request in rear 10 as bits of offset, using input logical address in remaining bit as index bit.
With reference to figure 2, the error correction guard method being applied to solid state hard disc resistance-variable storing device buffer memory of the present invention comprises the following steps:
The logical address request of input is divided into index bit and bits of offset, the mapping table of fine granularity management is searched by index bit, when the logical address request inputted hits in the mapping table buffer memory that fine granularity manages, then from the page comprising request map information, read corresponding mapping table address information according to the offset address request of input; When the logical address request inputted does not hit in the mapping table buffer memory that fine granularity manages, then from the mapping table of coarseness management, find out the page comprising request map information, when the mapping table of fine granularity management is cached with space, then direct will in the mapping table managed from coarseness read comprise request map information page, and by read comprise request map information page by fine granularity operating strategy write fine granularity management mapping table buffer memory in; Space is not had in the mapping table buffer memory of fine granularity management, last page in the mapping table buffer memory then fine granularity managed according to coarse-grained policies writes back in the mapping table of coarseness management, and then the page comprising request map information is write in the mapping table buffer memory of fine granularity management according to fine granularity operating strategy, finally from the page comprising request map information, read corresponding mapping table address information according to offset address request.
With reference to figure 3, the mapping table buffer memory of fine granularity management can the mapping table address information of buffer memory multiple pages, wherein, the mapping table address information of every one page is flash memory physical address corresponding to 1024 continuous logic addresses, and the logical address that first flash memory physical address in the mapping table address information of every one page is corresponding is the logical address index of this page, when the logical address request of accessing hits in the mapping table buffer memory that fine granularity manages, then corresponding according to index bit call number, the first address of storage address map information in resistance-variable storing device, the size of each address information entry, and page bias internal obtains required address map information position, wherein, the size of size × 1024 × call number+page bias internal × each address information entry of first address+each address information entry of storage address map information in required address map information position=resistance-variable storing device, the size of each address information entry is made up of the error correcting code redundancy of an address mapping information and this address mapping information.
With reference to figure 4, directory entry is stored into the static RAM of solid state hard disk system, cached data mapping table and mapping table buffer memory index array are stored in the SRAM of solid state hard disk system, and address mapping table information is stored in the outer buffer memory resistance-variable storing device of sheet of solid state hard disk system.
Claims (5)
1. one kind is applied to the error correction protection architecture of solid state hard disc resistance-variable storing device buffer memory, it is characterized in that, the code length of the mapping table of coarseness management is identical with the code length of caching of page data, in data processing, mapping table address information access frequency in the mapping table of coarseness management being greater than preset value is stored in the mapping table buffer memory of fine granularity management, the entry of the mapping table of a coarseness management is spliced by 1024 address mapping table, each entry in the mapping table buffer memory of fine granularity management all comprises the error correcting code redundancy of a map information and a map information,
Exchange data between the mapping table that the mapping table buffer memory of fine granularity management and coarseness manage are in units of page, one page map information read in the mapping table managed from coarseness is all placed in the mapping table buffer memory of fine granularity management, wherein, one page map information is spliced by 1024 map information, using input logical address request in rear 10 as bits of offset, using input logical address in remaining bit as index bit.
2. be applied to an error correction guard method for solid state hard disc resistance-variable storing device buffer memory, it is characterized in that, based on the error correction protection architecture being applied to solid state hard disc resistance-variable storing device buffer memory according to claim 1, comprise the following steps:
The logical address request of input is divided into index bit and bits of offset, the mapping table buffer memory of fine granularity management is searched by index bit, when the logical address request inputted hits in the mapping table buffer memory that fine granularity manages, then from the page comprising request map information, read corresponding mapping table address information according to the offset address request of input; When the logical address request inputted does not hit in the mapping table buffer memory that fine granularity manages, then from the mapping table of coarseness management, find out the page comprising request map information, when the mapping table of fine granularity management is cached with space, then direct from coarseness management mapping table read comprise request map information page, and by read comprise request map information page by fine granularity operating strategy write fine granularity management mapping table buffer memory in; Space is not had in the mapping table buffer memory of fine granularity management, last page in the mapping table buffer memory then fine granularity managed according to coarse-grained policies writes back in the mapping table of coarseness management, and then the page comprising request map information is write in the mapping table buffer memory of fine granularity management according to fine granularity operating strategy, finally from the page comprising request map information, read corresponding mapping table address information according to offset address request.
3. the error correction guard method being applied to solid state hard disc resistance-variable storing device buffer memory according to claim 2, is characterized in that,
The mapping table buffer memory of fine granularity management can the mapping table address information of buffer memory multiple pages, wherein, the mapping table address information of every one page is flash memory physical address corresponding to 1024 continuous logic addresses, and the logical address that first flash memory physical address in the mapping table address information of every one page is corresponding is the logical address index of this page;
When the logical address request of accessing hits in the mapping table buffer memory that fine granularity manages, then obtain required address map information position according to the first address of storage address map information, the size of each address information entry and page bias internal in call number corresponding to index bit, resistance-variable storing device, wherein, the size of size × 1024 × call number+page bias internal × each address information entry of first address+each address information entry of storage address map information in required address map information position=resistance-variable storing device.
4. the error correction guard method being applied to solid state hard disc resistance-variable storing device buffer memory according to claim 3, is characterized in that, the size of each address information entry is made up of the error correcting code redundancy of an address mapping information and this address mapping information.
5. the error correction guard method being applied to solid state hard disc resistance-variable storing device buffer memory according to claim 2; it is characterized in that; directory entry is stored into the static RAM of solid state hard disk system; cached data mapping table and mapping table buffer memory index array are stored in the SRAM of solid state hard disk system, and address mapping table information is stored in the outer buffer memory resistance-variable storing device of sheet of solid state hard disk system.
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| CN201510382445.5A CN105005510B (en) | 2015-07-02 | 2015-07-02 | Error correction protection architecture and method applied to solid state disk resistance-variable storing device caching |
| PCT/CN2015/098137 WO2017000517A1 (en) | 2015-07-02 | 2015-12-21 | Error correction protection architecture and method applied to resistive random access memory cache of solid state disk |
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| CN201510382445.5A CN105005510B (en) | 2015-07-02 | 2015-07-02 | Error correction protection architecture and method applied to solid state disk resistance-variable storing device caching |
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| CN113450863A (en) * | 2021-07-09 | 2021-09-28 | 上海交通大学 | Method for resisting hard failure error of resistive symmetric memory |
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| WO2017000517A1 (en) * | 2015-07-02 | 2017-01-05 | 西安交通大学 | Error correction protection architecture and method applied to resistive random access memory cache of solid state disk |
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| CN113450863A (en) * | 2021-07-09 | 2021-09-28 | 上海交通大学 | Method for resisting hard failure error of resistive symmetric memory |
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Also Published As
| Publication number | Publication date |
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| WO2017000517A1 (en) | 2017-01-05 |
| CN105005510B (en) | 2018-07-17 |
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