CN102279803A - Spare area distribution method for enhancing storage reliability of multilayer unit NAND-Flash - Google Patents
Spare area distribution method for enhancing storage reliability of multilayer unit NAND-Flash Download PDFInfo
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Abstract
The invention discloses a spare area distribution method for enhancing the storage reliability of multilayer unit NAND-Flash. In the method, spare areas of the multilayer unit NAND-Flash are redistributed by using different error rates of a most significant bit (MSB) page and a least significant bit (LSB) page, and the MSB page has high error rate and needs more spare areas for correcting errors, so that all spare areas of the MSB page are used for storing error correction codes, a small number of spare areas are used for storing error correction codes in the LSB page, management information of the MSB page and the LSB page is stored in the spare areas of the LSB page, and the storage data reliability of the multilayer unit NAND-Flash is enhanced.
Description
Technical field
The present invention relates to the NAND-Flash technical field, be specifically related to a kind of spare area allocation method that improves multilevel-cell NAND-Flash memory reliability.
Background technology
NAND-Flash is a kind of storage medium that is used to store data.A NAND-Flash is made up of data block, and each data block is made up of page group again.In general, each page of page group is made up of n byte data district and m byte spare area.In addition on data storage logic, the n byte data district of each page can be decomposed into s sector (SECTOR), wherein each sector (SECTOR) comprises n/s byte data district, be used for corresponding error correcting code and other management information at each sector (SECTOR) m/s byte with storage in m byte spare area in addition, wherein n, m and s are positive integer, and n is greater than m, and n and m are the integral multiple of s in addition.
Though the charge energy of NAND-Flash is forever preserved the state of electric crystal, but because these electric charge oxide layers separate in order to keep a stable status, and these oxide skin(coating)s are to disappear with what use along with the time, therefore finally can cause the Flash Memory inefficacy of NAND-Flash.This has also just caused NAND-Flash can produce bad piece in production and use.Bad piece is meant this piece institute, and data storage errors takes place in one page or multipage when the storage data therein.And the probability that occurs along with the bad piece of increase of service time in the NAND-Flash use, can cause the very big wasting of resources if simply abandon bad piece so also increasing.
So,, must adopt certain correcting data error algorithm in order to improve the reliability of NAND-FLASH storage.Behind the correcting data error algorithm, have one group of error correction redundancy sign indicating number and be attached to page spare area.Early stage NAND-Flash technology is based on single layer cell, and the error probability of unit data piece is less, and the error correcting code that the correcting data error algorithm produces is enough stored in the spare area in its storage array.For present NAND-Flash main flow technology multilevel-cell, each cell stores two bits, because the increase of density causes the data block error probability to increase, the needed error correcting capability of data block is much larger than the requirement of single layer cell technology, and this has just caused the reduction of storage data reliability.
Summary of the invention
In order to overcome the deficiency that above-mentioned prior art exists, the object of the present invention is to provide a kind of spare area allocation method that improves multilevel-cell NAND-Flash memory reliability, by utilizing the different error rates of high significance bit MSB page or leaf and low order LSB page or leaf, redistribute multilevel-cell NAND-Flash spare area, the error rate of high significance bit MSB page or leaf is higher, need more spare area to be used for error correction, therefore, whole spare areas of high significance bit MSB page or leaf are used to store error correcting code, low order LSB page or leaf is used less spare area storage error correcting code, management information (the erase block management information of high significance bit MSB page or leaf and low order LSB page or leaf, wear leveling management information etc.) all be stored in the spare area of low order LSB page or leaf, improved error correcting capability greatly and improved storage data reliability.
In order to achieve the above object, the technical solution adopted in the present invention is:
A kind of spare area allocation method that improves multilevel-cell NAND-Flash memory reliability, at first the n byte data that has of the high significance bit MSB page or leaf in the data block of multilevel-cell NAND-Flash is divided into the first sector data of s branch, the size of each first sector data branch is n/s, the m byte spare area of this high significance bit MSB page or leaf is divided into one by one s first ECC sign indicating number district data branch corresponding to s first sector data branch, the size of each first ECC sign indicating number district data branch is m/s, and the n byte data that has of the low order LSB page or leaf in the data block of multilevel-cell NAND-Flash is divided into s tail fan district data branch, the size of each tail fan district data branch is n/s, the m byte spare area of this low order LSB page or leaf is divided into one by one s tail ECC sign indicating number district data branch and management information area data branch corresponding to s tail fan district data branch, the size of each tail ECC sign indicating number district data branch is less than the size of each first ECC sign indicating number district data branch, and management information area data branch is used to deposit management information (the erase block management information of high significance bit MSB page or leaf and low order LSB page or leaf, wear leveling management information etc.).Wherein n, m and s are positive integer, and n is greater than m, and n and m are the integral multiple of s in addition.
When will be when high significance bit MSB page or leaf and low order LSB page or leaf write data, 4 tail fan district data branches of 4 first sector data branches of at first high significance bit MSB page or leaf and low order LSB page or leaf receive the corresponding required data that write, pass through error correcting algorithm (BCH respectively according to the size of each first ECC sign indicating number district data branch and the size of each tail ECC sign indicating number district data branch simultaneously, RS) the ECC sign indicating number of the first sector data of each of derivation correspondence branch data and the ECC sign indicating number of each tail fan district data branch, and the ECC sign indicating number of each first sector data branch data and the ECC sign indicating number of each tail fan district data branch deposited into each corresponding first ECC sign indicating number district data branch and each tail ECC sign indicating number district data branch, simultaneously with management information (the erase block management information of high significance bit MSB page or leaf and low order LSB page or leaf, wear leveling management information etc.) deposit into management information area data branch.
When will be to high significance bit MSB page or leaf and low order LSB page or leaf sense data, at first distinguish high significance bit MSB page or leaf and low order LSB page or leaf, read the ECC sign indicating number of the first sector data of corresponding each branch data and the ECC sign indicating number of each tail fan district data branch respectively according to the size of the size of each first ECC sign indicating number district data branch and each tail ECC sign indicating number district data branch then, isolate the management information of high significance bit MSB page or leaf and low order LSB page or leaf simultaneously, at last according to the ECC sign indicating number of the ECC sign indicating number of each first sector data branch data and each tail fan district data branch come to each first sector data branch and each tail fan district data branch data execution error correct algorithm (BCH, RS).
By utilizing the different error rates of high significance bit MSB page or leaf and low order LSB page or leaf, redistribute multilevel-cell NAND-Flash spare area, the error rate of high significance bit MSB page or leaf is higher, need more spare area to be used for error correction, therefore, whole spare areas of high significance bit MSB page or leaf are used to store error correcting code, low order LSB page or leaf is used less spare area storage error correcting code, management information (the erase block management information of high significance bit MSB page or leaf and low order LSB page or leaf, wear leveling management information etc.) all be stored in the spare area of low order LSB page or leaf, improved the reliability of multilevel-cell NAND-Flash storage data.
Description of drawings
Fig. 1 is the one of four states coding of multilevel-cell NAND-Flash storage unit.
Fig. 2 is high significance bit MSB page or leaf of multilevel-cell NAND-Flash and low order LSB page data storage organization.
Embodiment
The present invention will be described in more detail below in conjunction with drawings and Examples.
As shown in Figure 1, the one of four states coding that is respectively high significance bit MSB and low order LSB of multilevel-cell NAND FLASH storage unit, be respectively 11 states 201,01 state 202,00 state 203 and 10 states 204, because the voltage difference between adjacent two states of multilevel-cell is very little, be highly susceptible to makeing mistakes, compare with low order LSB like this, high significance bit MSB is easier to make mistakes, high significance bit MSB may be in 11 states 201 and 202 conversions of 01 state, also may be in 00 state 203 and 204 conversions of 10 states, and low order LSB only may be in 01 state 202 and 203 conversions of 00 state.Therefore, 205 with 206 high significance bit MSB and low order LSB to belong to high significance bit MSB page or leaf also different with the error rate of low order LSB page or leaf, the error rate of high significance bit MSB page or leaf is two times of low order LSB page or leaf.
As shown in Figure 2, improve the spare area allocation method of multilevel-cell NAND-Flash memory reliability, at first the 2K byte data district 301A that has with the high significance bit MSB page or leaf in the data block of multilevel-cell NAND-Flash is divided into 4 first sector data (SEC0 of branch, SEC1, SEC2, SEC3), the size of each first sector data branch is 512 bytes, 64 byte spare area 301B of this high significance bit MSB page or leaf are divided into one by one 4 (ECC0 of first ECC sign indicating number district data branch corresponding to 4 first sector data branches, ECC1, ECC2, ECC3), the size of each first ECC sign indicating number district data branch is 16 bytes, and the 2K byte data district 302A that has of the low order LSB page or leaf in the data block of multilevel-cell NAND-Flash is divided into the (SEC0 of 4 tail fan district data branches, SEC1, SEC2, SEC3), the size of each tail fan district data branch is 512 bytes, 64 byte spare areas of this low order LSB page or leaf are divided into one by one 4 tail ECC sign indicating number district 302B of data branch and the management information area data 302C of branch corresponding to 4 tail fan district data branches, the size of each tail ECC sign indicating number district data branch is 12 bytes, and management information area data branch is used to deposit management information (the erase block management information of high significance bit MSB page or leaf and low order LSB page or leaf, wear leveling management information etc.).Therefore, whole spare areas of high significance bit MSB page or leaf are used to store error correcting code, low order LSB page or leaf is used less spare area storage error correcting code, and the management information of high significance bit MSB page or leaf and low order LSB page or leaf (erase block management information, wear leveling management information etc.) all is stored in the spare area of low order LSB page or leaf.
When will be when high significance bit MSB page or leaf and low order LSB page or leaf write data, 4 tail fan district data branches of 4 first sector data branches of at first high significance bit MSB page or leaf and low order LSB page or leaf receive the corresponding required data that write, pass through error correcting algorithm (BCH respectively according to the size of each first ECC sign indicating number district data branch and the size of each tail ECC sign indicating number district data branch simultaneously, RS) the ECC sign indicating number of the first sector data of each of derivation correspondence branch data and the ECC sign indicating number of each tail fan district data branch, and the ECC sign indicating number of each first sector data branch data and the ECC sign indicating number of each tail fan district data branch deposited into each corresponding first ECC sign indicating number district data branch and each tail ECC sign indicating number district data branch, simultaneously the management information of high significance bit MSB page or leaf and low order LSB page or leaf is deposited into management information area data branch.
When will be to high significance bit MSB page or leaf and low order LSB page or leaf sense data, at first distinguish high significance bit MSB page or leaf and low order LSB page or leaf, read the ECC sign indicating number of the first sector data of corresponding each branch data and the ECC sign indicating number of each tail fan district data branch respectively according to the size of the size of each first ECC sign indicating number district data branch and each tail ECC sign indicating number district data branch then, isolate the management information of high significance bit MSB page or leaf and low order LSB page or leaf simultaneously, at last according to the ECC sign indicating number of the ECC sign indicating number of each first sector data branch data and each tail fan district data branch come to each first sector data branch and each tail fan district data branch data execution error correct algorithm (BCH, RS).
By utilizing the different error rates of high significance bit MSB page or leaf and low order LSB page or leaf, redistribute multilevel-cell NAND-Flash spare area, the error rate of high significance bit MSB page or leaf is higher, need more spare area to be used for error correction, therefore, whole spare areas of high significance bit MSB page or leaf are used to store error correcting code, low order LSB page or leaf is used less spare area storage error correcting code, the management information of high significance bit MSB page or leaf and low order LSB page or leaf all is stored in the spare area of low order LSB page or leaf, has improved error correcting capability greatly and has improved storage data reliability.
Claims (1)
1. improve the spare area allocation method of multilevel-cell NAND-Flash memory reliability, it is characterized in that: at first the n byte data that has of the high significance bit MSB page or leaf in the data block of multilevel-cell NAND-Flash is divided into the first sector data of s branch, the size of each first sector data branch is n/s, the m byte spare area of this high significance bit MSB page or leaf is divided into one by one s first ECC sign indicating number district data branch corresponding to s first sector data branch, the size of each first ECC sign indicating number district data branch is m/s, and the n byte data that has of the low order LSB page or leaf in the data block of multilevel-cell NAND-Flash is divided into s tail fan district data branch, the size of each tail fan district data branch is n/s, the m byte spare area of this low order LSB page or leaf is divided into one by one s tail ECC sign indicating number district data branch and management information area data branch corresponding to s tail fan district data branch, the size of each tail ECC sign indicating number district data branch is less than the size of each first ECC sign indicating number district data branch, and management information area data branch is used to deposit the management information of high significance bit MSB page or leaf and low order LSB page or leaf.When will be when high significance bit MSB page or leaf and low order LSB page or leaf write data, 4 tail fan district data branches of 4 first sector data branches of at first high significance bit MSB page or leaf and low order LSB page or leaf receive the corresponding required data that write, pass through error correcting algorithm (BCH respectively according to the size of each first ECC sign indicating number district data branch and the size of each tail ECC sign indicating number district data branch simultaneously, RS) the ECC sign indicating number of the first sector data of each of derivation correspondence branch data and the ECC sign indicating number of each tail fan district data branch, and the ECC sign indicating number of each first sector data branch data and the ECC sign indicating number of each tail fan district data branch deposited into each corresponding first ECC sign indicating number district data branch and each tail ECC sign indicating number district data branch, simultaneously the management information of high significance bit MSB page or leaf and low order LSB page or leaf is deposited into management information area data branch.When will be to high significance bit MSB page or leaf and low order LSB page or leaf sense data, at first distinguish high significance bit MSB page or leaf and low order LSB page or leaf, read the ECC sign indicating number of the first sector data of corresponding each branch data and the ECC sign indicating number of each tail fan district data branch respectively according to the size of the size of each first ECC sign indicating number district data branch and each tail ECC sign indicating number district data branch then, isolate the management information of high significance bit MSB page or leaf and low order LSB page or leaf simultaneously, at last according to the ECC sign indicating number of the ECC sign indicating number of each first sector data branch data and each tail fan district data branch come to each first sector data branch and each tail fan district data branch data execution error correct algorithm (BCH, RS).Wherein n, m and s are positive integer, and n is greater than m, and n and m are the integral multiple of s in addition.
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| CN105786412A (en) * | 2013-11-05 | 2016-07-20 | 威盛电子股份有限公司 | Method of operating a non-volatile memory device |
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| CN107395214A (en) * | 2017-07-12 | 2017-11-24 | 华中科技大学 | A kind of method that LDPC decoding latencies are reduced based on Hash memory pages error property |
| CN107391299A (en) * | 2017-07-17 | 2017-11-24 | 华中科技大学 | A kind of method for lifting flash-memory storage system reading performance |
| CN107423159A (en) * | 2017-07-11 | 2017-12-01 | 华中科技大学 | A kind of method based on flash memory error pattern lifting LDPC decoding performances |
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| CN111290970A (en) * | 2018-12-06 | 2020-06-16 | 爱思开海力士有限公司 | Memory system and operating method thereof |
| CN111290970B (en) * | 2018-12-06 | 2023-04-07 | 爱思开海力士有限公司 | Memory system and operating method thereof |
| CN112992256A (en) * | 2019-12-16 | 2021-06-18 | 中国科学院微电子研究所 | Error rate balancing method and device |
| CN112992256B (en) * | 2019-12-16 | 2022-12-09 | 中国科学院微电子研究所 | Error rate balancing method and device |
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