CN106354669B - Memory with hierarchical structure - Google Patents
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- CN106354669B CN106354669B CN201510410351.4A CN201510410351A CN106354669B CN 106354669 B CN106354669 B CN 106354669B CN 201510410351 A CN201510410351 A CN 201510410351A CN 106354669 B CN106354669 B CN 106354669B
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Abstract
The invention discloses a memory with a hierarchical structure, which comprises: l pages with the same size, wherein L1 pages form a first data area for storing valid data; the remaining L2 pages form a first shadow area for extending the function of memory reliability; each page comprises M data units with the same size, wherein M1 data units form a second data area for storing valid data; the rest M2 data units form a second shadow area for expanding the function of the reliability of the memory; each data unit comprises N bytes, wherein N1 bytes form a third data area for storing valid data, and the remaining N2 bytes form a third shadow area for expanding the function of the reliability of the memory; wherein, L-L1 + L2, M-M1 + M2, N-N1 + N2; l, L1, L2, M, M1, M2, N, N1 and N2 are all positive integers greater than 1.
Description
Technical Field
The invention relates to the technical field of storage, in particular to a memory with a hierarchical structure.
Background
With the progress and development of the times and technologies, electronic products not only need to meet the basic requirements of availability, but also draw great attention and attention to the differentiated characteristics of high safety, high performance, low power consumption and high reliability. As important parts memory therein, in addition to the conventional requirements, higher requirements are put on high reliability, high security, and the like. To meet these demands, industry has successively proposed a number of methods, and efficient implementation of these methods relies on improving conventional memory structures.
With the rapid development of integrated circuits, the integration level and capacity of memories are higher and higher, and particularly in the sensitive fields of finance and the like, the high reliability and the high security of the memories are important factors for determining the security level of products. How to ensure that the memory does not make mistakes in the using process even under attack, and error reporting or self-correction is carried out when errors occur; how to manage the service life, foresee the limit of erasing times of the memory in advance, make data backup and replacement, and prolong the overall service time; how to adopt the power fail safeguard technology to protect the memory, under the condition of unexpected power fail, the user data can be recovered by oneself. These are challenges for new types of memory.
Disclosure of Invention
In order to meet the new challenges of memory technology, the present invention is expected to provide a memory with a hierarchical structure, which can meet the requirements of high reliability, high security, high access speed, etc. of the memory.
The technical scheme of the embodiment of the invention is realized as follows:
an embodiment of the present invention provides a memory having a hierarchical structure, where the memory includes:
l pages of the same size, wherein,
the L1 pages form a first data area for storing valid data; the remaining L2 pages form a first shadow area for extending the function of memory reliability;
each page comprises M Data units with the same size, wherein M1 Data units form a second Data area for storing valid Data; the rest M2 data units form a second shadow area for expanding the function of the reliability of the memory;
each data unit comprises N bytes, wherein N1 bytes form a third data area for storing valid data, and the remaining N2 bytes form a third shadow area for expanding the function of the reliability of the memory;
wherein, L-L1 + L2, M-M1 + M2, N-N1 + N2; l, L1, L2, M, M1, M2, N, N1 and N2 are all positive integers greater than 1.
In the foregoing solution, the first shadow area includes:
and the backup page is used for backing up the information stored in the page of the first data area so as to replace a bad page or carry out power failure protection.
In the foregoing solution, the second shadow area includes:
and the service life management data unit is used for recording the service life information of the page.
In the foregoing solution, the second shadow area includes:
and the power failure protection data unit is used for recording the address information of the backup page of the page.
In the foregoing solution, the second shadow area includes:
and the verification data unit is used for recording verification information of the page.
In the foregoing solution, the second shadow area includes:
and the backup data unit is used for backing up information stored in the data unit of the second data area so as to replace the error data unit or carry out power failure protection.
In the foregoing solution, the third shadow area includes:
and the check byte is used for storing the check information of the data unit.
In the above scheme, each byte includes:
and the check bit is used for storing the check information of the byte.
According to the memory with the hierarchical structure, shadow areas for assisting memory management are arranged in each level of storage structure, so that the memory can realize various memory management functions in a hierarchical manner, and further, the requirements of high reliability, high safety and high access speed of the memory can be met.
For example, to implement error reporting or self-error correction when an error occurs in the memory, the invention adds check/error correction bits to a plurality of data units, for example, a memory with a page size of 512Byte and a data unit size of 32bit, and adds check/error correction bits to 2 data units, that is, 64 bit. In the existing technical scheme, a mode of adding a verification/error correction bit behind each Page is adopted, and a value obtained after certain operation is carried out on data of the whole Page is stored in the verification/error correction bit; when reading out, the same operation is carried out on the Page data, the obtained value is compared with the value stored in the check/error correction bit, and if the inconsistency is found, an alarm is given or the error is corrected automatically. Compared with the prior technical scheme: while the whole page (128 data units) needs to be read out differently when reading 1 data unit each time, the invention only needs to read 2 data units, thereby greatly reducing the read data amount and improving the whole read-out speed. On the other hand, the complexity and time for operating the whole page are much higher than those for operating 2 data units, and the operating time overhead is greatly reduced.
For example, in order to realize the memory life management, the invention sets a life management data unit in the second shadow area for each page, and the life management data unit is used for recording whether the page is close to the life limit. For example, the number of times that data has been erased is recorded in the lifetime management data unit for each erasure, 1 is added for each erasure, and a backup or replacement scheme is initiated when the number of times approaches a predetermined value. Or after each erasing and writing, the read-back is tightened, if the read-back is not tightened, the service life limit is approached, the mark is recorded in the service life management data unit, and a backup or replacement scheme is started during subsequent erasing and writing. The prior technical scheme is as follows: the data to be written into the memory is firstly written into the RAM, after the data writing action of the target memory is completed, the data of the two memories are compared, if the data are inconsistent, the address space of the memory is abandoned, and the data are written into the RAM again by replacing the other section of address space. Compared with the technical scheme, if power failure occurs when the data of the memory and the RAM are inconsistent, the data to be written will be lost if the data of the RAM disappears after the power failure because the value of the memory is wrong. In addition, the scheme is backup or replacement after the real failure of the memory, and compared with the early warning mode of the invention, the reliability and the adopted method of the invention are more flexible.
For example, in order to realize data recovery of the memory in unexpected power failure, the invention sets a power failure protection data unit in the shadow area for each page, and adds a plurality of backup pages. The power-down protection data unit is used for storing information such as the address of the page and the like, is used for power-down protection control, and the backup page is used for power-down protection alternation. The hardware-level automatic power-down protection strategy is transparent to software and users, reduces the complexity of user development, and improves the performance by more than 2 times compared with the software level.
In summary, it is noted that, in the memory with a hierarchical structure provided by the present invention, since each level is provided with a shadow area, the requirements of high reliability, high security and high access speed of the memory can be realized by combining a certain memory management method according to the requirement.
Drawings
FIG. 1 is a schematic structural diagram of a memory with a hierarchical structure according to the present invention.
Detailed Description
In order to more clearly illustrate the embodiments and technical solutions of the present invention, the technical solutions of the present invention will be described in more detail with reference to the accompanying drawings and embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without inventive step, are within the scope of the present invention.
Fig. 1 is a schematic structural diagram of a memory having a hierarchical structure according to the present invention, as shown in fig. 1, the memory includes: l pages (pages) of the same size, wherein,
the L1 pages form a first data area for storing valid data; the remaining L2 pages form a first shadow area for extending the function of memory reliability;
each page comprises M Data units with the same size, wherein M1 Data units form a second Data area for storing valid Data; the rest M2 data units form a second shadow area for expanding the function of the reliability of the memory;
each data unit comprises N bytes, wherein N1 bytes form a third data area for storing valid data, and the remaining N2 bytes form a third shadow area for expanding the function of the reliability of the memory;
here, L-L1 + L2, M-M1 + M2, N-N1 + N2; l, L1, L2, M, M1, M2, N, N1 and N2 are all positive integers greater than 1.
Further, in the above memory, the first shadow area includes:
and the backup page is used for backing up the information stored in the page of the first data area so as to replace a bad page or carry out power failure protection.
Further, in the above memory, the second shadow area may include:
and the service life management data unit is used for recording the service life information of the page.
Further, in the above memory, the second shadow area may include:
and the power failure protection data unit is used for recording the address information of the backup page of the page.
Further, in the above memory, the second shadow area may include:
and the verification data unit is used for recording verification information of the page.
Further, in the above memory, the second shadow area may include:
and the backup data unit is used for backing up information stored in the data unit of the second data area so as to replace the error data unit or carry out power failure protection.
All or part of the life management data unit, the power failure protection data unit, the verification data unit and the backup data unit can be simultaneously contained in the second shadow area, and the number of each type of data unit can be one or more than one.
Further, in the above memory, the third shadow area may include:
and the check byte is used for storing the check information of the data unit.
The third shadow area may include one or more check bytes.
Further, in the above memory, each byte includes:
and the check bit is used for storing the check information of the byte.
One or more check bits may be included in each byte.
According to the memory with the hierarchical structure, shadow areas for assisting memory management are arranged in each level of storage structure, so that the memory can realize various memory management functions in a hierarchical manner, and further, the requirements of high reliability, high safety and high access speed of the memory can be met.
For example, to implement error reporting or self-error correction when an error occurs in the memory, the invention adds check/error correction bits to a plurality of data units, for example, a memory with a page size of 512Byte and a data unit size of 32bit, and adds check/error correction bits to 2 data units, that is, 64 bit. In the existing technical scheme, a mode of adding a verification/error correction bit behind each Page is adopted, and a value obtained after certain operation is carried out on data of the whole Page is stored in the verification/error correction bit; when reading out, the same operation is carried out on the Page data, the obtained value is compared with the value stored in the check/error correction bit, and if the inconsistency is found, an alarm is given or the error is corrected automatically. Compared with the prior technical scheme: while the whole page (128 data units) needs to be read out differently when reading 1 data unit each time, the invention only needs to read 2 data units, thereby greatly reducing the read data amount and improving the whole read-out speed. On the other hand, the complexity and time for operating the whole page are much higher than those for operating 2 data units, and the operating time overhead is greatly reduced.
For example, in order to realize the memory life management, the invention sets a life management data unit in the second shadow area for each page, and the life management data unit is used for recording whether the page is close to the life limit. For example, the number of times that data has been erased is recorded in the lifetime management data unit for each erasure, 1 is added for each erasure, and a backup or replacement scheme is initiated when the number of times approaches a predetermined value. Or after each erasing and writing, the read-back is tightened, if the read-back is not tightened, the service life limit is approached, the mark is recorded in the service life management data unit, and a backup or replacement scheme is started during subsequent erasing and writing. The prior technical scheme is as follows: the data to be written into the memory is firstly written into the RAM, after the data writing action of the target memory is completed, the data of the two memories are compared, if the data are inconsistent, the address space of the memory is abandoned, and the data are written into the RAM again by replacing the other section of address space. Compared with the technical scheme, if power failure occurs when the data of the memory and the RAM are inconsistent, the data to be written will be lost if the data of the RAM disappears after the power failure because the value of the memory is wrong. In addition, the scheme is backup or replacement after the real failure of the memory, and compared with the early warning mode of the invention, the reliability and the adopted method of the invention are more flexible.
For example, in order to realize data recovery of the memory in unexpected power failure, the invention sets a power failure protection data unit in the shadow area for each page, and adds a plurality of backup pages. The power-down protection data unit is used for storing information such as the address of the page and the like, is used for power-down protection control, and the backup page is used for power-down protection alternation. The hardware-level automatic power-down protection strategy is transparent to software and users, reduces the complexity of user development, and improves the performance by more than 2 times compared with the software level.
In summary, it is noted that, in the memory with a hierarchical structure provided by the present invention, since each level is provided with a shadow area, the requirements of high reliability, high security and high access speed of the memory can be realized by combining a certain memory management method according to the requirement.
Any of the memories provided by the present invention can be implemented by a storage medium such as FLASH or EEPROM.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of a hardware embodiment, a software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.
Claims (8)
1. A memory having a hierarchical structure, the memory comprising: l pages of the same size, wherein,
the L1 pages form a first data area for storing valid data; the rest L2 pages form a first shadow area, which is used for backing up the information stored in the pages of the first data area to replace bad pages or carry out power failure protection, thereby expanding the function of memory reliability;
each page comprises M Data units with the same size, wherein M1 Data units form a second Data area for storing valid Data; the rest M2 data units form a second shadow area for backing up the information stored in the data units of the second data area and recording the service life information and/or the check information of the page, thereby expanding the function of the reliability of the memory;
each data unit comprises N bytes, wherein N1 bytes form a third data area for storing valid data, and the remaining N2 bytes form a third shadow area for storing the verification information of the data unit, so that the reliability function of the memory is expanded; wherein, L-L1 + L2, M-M1 + M2, N-N1 + N2; l, L1, L2, M, M1, M2, N, N1 and N2 are all positive integers greater than 1.
2. The memory of claim 1, wherein the first shadow area comprises:
and the backup page is used for backing up the information stored in the page of the first data area so as to replace a bad page or carry out power failure protection.
3. The memory of claim 1, wherein the second shadow area comprises:
and the service life management data unit is used for recording the service life information of the page.
4. The memory of claim 2, wherein the second shadow area comprises:
and the power failure protection data unit is used for recording the address information of the backup page of the page.
5. The memory of claim 1, wherein the second shadow area comprises:
and the verification data unit is used for recording verification information of the page.
6. The memory of claim 1, wherein the second shadow area comprises:
and the backup data unit is used for backing up information stored in the data unit of the second data area so as to replace the error data unit or carry out power failure protection.
7. The memory of claim 1, wherein the third shadow area comprises:
and the check byte is used for storing the check information of the data unit.
8. The memory of claim 1, wherein each byte comprises:
and the check bit is used for storing the check information of the byte.
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