CN101833510A - Address translation method for flash storage FTL - Google Patents
Address translation method for flash storage FTL Download PDFInfo
- Publication number
- CN101833510A CN101833510A CN 201010133944 CN201010133944A CN101833510A CN 101833510 A CN101833510 A CN 101833510A CN 201010133944 CN201010133944 CN 201010133944 CN 201010133944 A CN201010133944 A CN 201010133944A CN 101833510 A CN101833510 A CN 101833510A
- Authority
- CN
- China
- Prior art keywords
- physical
- page
- page table
- physical block
- level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 24
- 238000006243 chemical reaction Methods 0.000 claims description 24
- 238000010586 diagram Methods 0.000 description 6
- 230000008901 benefit Effects 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000033772 system development Effects 0.000 description 1
Images
Abstract
The invention provides an address translation method for a flash storage FTL, which comprises the following steps of: acquiring a corresponding logic block number and an in-block index according to a logic page number; acquiring a physical block array and a root physical page number according to the logic block number; acquiring a physical page number of a first level page table according to the root physical page number, the in-block index and the physical block array; acquiring a physical page number of a second level page table according to the first level page table, the physical block array and the in-block index; and finding the physical page number corresponding to the logic page number from the two level page table according to the in-block index. In the embodiment of the invention, for each logic block, the physical pages corresponding to the all logic pages can be found just by recording one physical page number, so that the address translation method can effectively increase the FTL address translation speed and reduce the complexity of the calculation.
Description
Technical field
The present invention relates to computing machine and electronic information technical field, the address conversion method of particularly a kind of flash storage FTL (flash translation layer (FTL)).
Background technology
Because exist between the speed of disk and internal memory, the CPU speed than big-difference, the performance issue of disk progressively becomes one of main bottleneck that hinders the computer system development.Flash memory claims flash storer (flash memory) again, has physical stabilities such as power consumption is low, performance is high, antidetonation and plugs advantages such as mobile by force and conveniently.In recent years, be that the solid state hard disc capacity of medium progressively increases with the flash memory, price progressively descends, and the existing disk that replaces becomes the trend of new main flow external memory medium, and may cause the once change of storage system.Because flash memory can not upgrade on the spot, for the traditional file systems compatibility, flash memory need be packaged into a block device, and offer the function that file system can be upgraded on the spot.In order to offer the function that file system is upgraded on the spot, need carry out address translation to the visit of flash memory, the logical address of traditional file systems use soon is transformed into the physical address on the physical flash.At present, this address translation feature is finished by FTL.
FTL is keeping the transitional information of logical address and physical address.When the capacity of flash memory increased, keep the needed internal memory of conversion also increased thereupon.The method of address translation can be divided three classes: the conversion of piece level, the conversion of page or leaf level, mixing conversion.The conversion of piece level does not need too big internal memory, and therefore early stage method is used the conversion of piece level more.And the low capacity flash memory generally adopts a page level conversion.Mix conversion method and can between efficiency of erasing and memory consumption, reach balance.
The shortcoming that prior art exists is that these conversion methods all exist the shortcoming that slewing rate is slow, computing is complicated.
Summary of the invention
Purpose of the present invention is intended to solve above-mentioned technological deficiency, particularly solves the shortcoming of the slow and computing complexity of present FTL address translation speed.
For achieving the above object, one aspect of the present invention proposes a kind of address conversion method of flash storage FTL, may further comprise the steps: obtain index in corresponding logical block number (LBN) and the piece according to logical page number (LPN); Obtain physical block array and root physical page number according to described logical block number (LBN); Obtain one-level page table place physical page number according to described physical page number, described interior index and described physical block array; Obtain secondary page table place physical page number according to described one-level page table, described physical block array and described interior index; From the secondary page table, find this logical page number (LPN) corresponding physical page number according to described interior index.
In one embodiment of the invention, describedly obtain one-level page table place physical page number according to index in root physical page number, the piece and physical block array and comprise: the page directory that finds the two-stage page table according to described physical page number; Obtain one-level page table place physical page number according to index in described page directory, physical block array, the piece.
In one embodiment of the invention, also comprise: all physical blocks are divided into groups, and each logical block is associated with its corresponding physical piece array; Make up page directory, one-level page table and the secondary page table of two-stage page table, and each logical block is associated with a root physical page number.
In one embodiment of the invention, described all physical blocks are divided into groups to comprise: all physical blocks are divided into the physical block array that size is 63 physical blocks, wherein record physical block number in each physical block array, and the physical block number in each physical block array does not repeat.
In one embodiment of the invention, the page directory of described structure two-stage page table, one-level page table and secondary page table comprise: utilize 28 bytes in the spare area of flash memory Physical Page, in conjunction with the physical block array, make up page directory, one-level page table and the secondary page table of the two-stage page table of all logical page (LPAGE)s in the logical block.
In one embodiment of the invention, the page directory, one-level page table and the secondary page table that utilize 28 bytes in the spare area of flash memory Physical Page to make up the two-stage page table comprise: described 28 bytes are divided into three parts, wherein first is a page directory, second portion is the one-level page table, and third part is the secondary page table.
In one embodiment of the invention, wherein, first is preceding 6 bytes, and second portion is middle 6 bytes, and third part is back 16 bytes.
In one embodiment of the invention, wherein, described first is made up of 4 items, preceding 6 bits of each are represented the subscript of a physical block group, utilize the corresponding physical block number of subscript, obtain the address of corresponding one-level page table according to back 6 bits of described physical block number and this, 4 items of described first are to there being 4 one-level page tables.
In one embodiment of the invention, wherein, described second portion is made up of 4 items, preceding 6 bits of each are represented the subscript of a physical block group, utilize the corresponding physical block number of subscript, obtain the address of corresponding secondary page table according to back 6 bits of described physical block number and this, 4 items of described second portion are to there being 4 secondary page tables.
In one embodiment of the invention, wherein, described third part is made up of 4 items, and each represents a physical page number.
Pass through the embodiment of the invention, for each logical block, as long as physical page number of record just can find the wherein pairing Physical Page of all logical page (LPAGE)s, therefore the embodiment of the invention can improve FTL address translation speed effectively, and can reduce the complexity of computing.
Aspect that the present invention adds and advantage part in the following description provide, and part will become obviously from the following description, or recognize by practice of the present invention.
Description of drawings
Above-mentioned and/or additional aspect of the present invention and advantage are from obviously and easily understanding becoming the description of embodiment below in conjunction with accompanying drawing, wherein:
Fig. 1 is the address conversion method process flow diagram of the flash storage FTL of the embodiment of the invention;
Fig. 2 is the synoptic diagram of the physical block array of the embodiment of the invention;
Fig. 3 is the synoptic diagram that utilizes the two-stage page table of Physical Page spare area structure in the embodiment of the invention;
Fig. 4 is the address translation schematic flow sheet of the embodiment of the invention.
Embodiment
Describe embodiments of the invention below in detail, the example of described embodiment is shown in the drawings, and wherein identical from start to finish or similar label is represented identical or similar elements or the element with identical or similar functions.Below by the embodiment that is described with reference to the drawings is exemplary, only is used to explain the present invention, and can not be interpreted as limitation of the present invention.
As shown in Figure 1, the address conversion method process flow diagram for the flash storage FTL of the embodiment of the invention may further comprise the steps:
Step S101 divides into groups to all physical blocks.In one embodiment of the invention, all physical blocks can be divided into the physical block array that size is 63 physical blocks, as shown in Figure 2, synoptic diagram for the physical block array of the embodiment of the invention, in this physical block array, writing down the physical block number of each physical block, and do not repeating between the physical block number in each physical block array.Certainly need to prove in this embodiment; it is that the physical block array of 63 physical blocks is optimal ways of the present invention that all physical blocks are divided into size; but those skilled in the art also can select the physical block of quantity to divide into groups, and these all should be included within protection scope of the present invention.
Step S102 is associated each logical block with its corresponding physical piece array.
Step S103, page directory, one-level page table and the secondary page table of structure two-stage page table.Particularly, in embodiments of the present invention, can utilize 28 bytes in the spare area of flash memory Physical Page, in conjunction with the physical block array, construct the two-stage page table of each logical block, be one-level page table and secondary page table,, can find all logical page (LPAGE) corresponding physical pages or leaves in the logical block very soon according to this two-stage page table.More specifically, as shown in Figure 3, synoptic diagram for the two-stage page table that utilizes Physical Page spare area structure in the embodiment of the invention, 28 bytes of Physical Page spare area can be divided into 3 parts: preceding 6 bytes are first, middle 6 bytes are second portion, back 16 bytes are third part, and this dividing mode is the preferred embodiments of the present invention certainly, and those skilled in the art also can select other dividing mode.Wherein, first's (preceding 6 bytes) is a page directory, form by 4 items, wherein each is 12 bits, preceding 6 bits of each are represented the subscript of a physical block group, utilize subscript can in a physical block group, find a physical block number, so just can Physical Page of correspondence according to back 6 bits of this physical block number and this, this Physical Page is exactly the address of an one-level page table.Therefore, in other words, 4 items of first's page directory have pointed to 4 one-level page tables.Second portion (middle 6 bytes) is the one-level page table, and it is made up of 4 items, and wherein each is 12 bits.Preceding 6 bits of each are represented the subscript of a physical block group, utilize this subscript can in a physical block group, find a physical block number, according to back 6 bits of this physical block number and this, can corresponding Physical Page, this Physical Page is exactly the address of a secondary page table.So 4 items of one-level page table point to 4 secondary page tables.Third part (back 16 bytes) is the secondary page table, is made up of 4 items, and wherein each is 4 bytes, represents a physical page number.Like this to each logical block, the Physical Page that writes down its root directory place with and corresponding physical piece group number, just can find all logical page (LPAGE) corresponding physical pages or leaves in this piece.
Step S104 is associated each logical block with a root physical page number, the spare area of the Physical Page of each root physical page number indication is the page directory of this logical block.
After finishing above-mentioned setting, can be from logical page number (LPN), physics array and root physical page number according to this logical page number (LPN), this logical page number (LPN) place logical block, find this logical page (LPAGE) corresponding physical page number, can be with reference to shown in Figure 4, address translation schematic flow sheet for the embodiment of the invention specifically may further comprise the steps:
Step S105 obtains index in corresponding logical block number (LBN) and the piece according to logical page number (LPN).
Step S106 obtains physical block array and root physical page number according to logical block number (LBN).
Step S107 finds the page directory of two-stage page table according to the root physical page number.
Step S108 obtains one-level page table place physical page number according to index in page directory, physical block array, the piece.
Step S109 obtains secondary page table place physical page number according to index in one-level page table, physical block array, the piece.
Step S110 finds this logical page number (LPN) corresponding physical page number from the secondary page table.
Pass through the embodiment of the invention, for each logical block, as long as physical page number of record just can find the wherein pairing Physical Page of all logical page (LPAGE)s, therefore the embodiment of the invention can improve FTL address translation speed effectively, and can reduce the complexity of computing.
Although illustrated and described embodiments of the invention, for the ordinary skill in the art, be appreciated that without departing from the principles and spirit of the present invention and can carry out multiple variation, modification, replacement and modification that scope of the present invention is by claims and be equal to and limit to these embodiment.
Claims (10)
1. the address conversion method of a flash storage FTL is characterized in that, may further comprise the steps:
Obtain index in corresponding logical block number (LBN) and the piece according to logical page number (LPN);
Obtain physical block array and root physical page number according to described logical block number (LBN);
Obtain one-level page table place physical page number according to described physical page number, described interior index and described physical block array;
Obtain secondary page table place physical page number according to described one-level page table, described physical block array and described interior index;
From the secondary page table, find this logical page number (LPN) corresponding physical page number according to described interior index.
2. the address conversion method of flash storage FTL as claimed in claim 1 is characterized in that, describedly obtains one-level page table place physical page number according to index in root physical page number, the piece and physical block array and comprises:
Find the page directory of two-stage page table according to described physical page number;
Obtain one-level page table place physical page number according to index in described page directory, physical block array, the piece.
3. the address conversion method of flash storage FTL as claimed in claim 2 is characterized in that, also comprises:
All physical blocks are divided into groups, and each logical block is associated with its corresponding physical piece array;
Make up page directory, one-level page table and the secondary page table of two-stage page table, and each logical block is associated with a root physical page number.
4. the address conversion method of flash storage FTL as claimed in claim 3 is characterized in that, described all physical blocks is divided into groups to comprise:
All physical blocks are divided into the physical block array that size is 63 physical blocks, wherein record physical block number in each physical block array, and the physical block number in each physical block array does not repeat.
5. as the address conversion method of claim 3 or 4 described flash storage FTLs, it is characterized in that the page directory of described structure two-stage page table, one-level page table and secondary page table comprise:
Utilize 28 bytes in the spare area of flash memory Physical Page,, each logical block is made up page directory, one-level page table and the secondary page table of its two-stage page table in conjunction with the physical block array.
6. the address conversion method of flash storage FTL as claimed in claim 5 is characterized in that, the page directory, one-level page table and the secondary page table that utilize 28 bytes in the spare area of flash memory Physical Page to make up the two-stage page table comprise:
Described 28 bytes are divided into three parts, and wherein first is a page directory, and second portion is the one-level page table, and third part is the secondary page table.
7. the address conversion method of flash storage FTL as claimed in claim 6 is characterized in that, wherein, first is preceding 6 bytes, and second portion is middle 6 bytes, and third part is back 16 bytes.
8. the address conversion method of flash storage FTL as claimed in claim 7, it is characterized in that, wherein, described first is made up of 4 items, preceding 6 bits of each are represented the subscript of a physical block group, utilize the corresponding physical block number of subscript, obtain the address of corresponding one-level page table according to described physical block number and this back 6 bits, 4 items of described first are to there being 4 one-level page tables.
9. the address conversion method of flash storage FTL as claimed in claim 7, it is characterized in that, wherein, described second portion is made up of 4 items, preceding 6 bits of each are represented the subscript of a physical block group, utilize the corresponding physical block number of subscript, obtain the address of corresponding secondary page table according to described physical block number and this back 6 bits, 4 items of described second portion are to there being 4 secondary page tables.
10. the address conversion method of flash storage FTL as claimed in claim 7 is characterized in that, wherein, described third part is made up of 4 items, and each represents a physical page number.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010133944A CN101833510B (en) | 2010-03-29 | 2010-03-29 | Address translation method for flash storage FTL |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010133944A CN101833510B (en) | 2010-03-29 | 2010-03-29 | Address translation method for flash storage FTL |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101833510A true CN101833510A (en) | 2010-09-15 |
| CN101833510B CN101833510B (en) | 2012-10-10 |
Family
ID=42717586
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201010133944A Expired - Fee Related CN101833510B (en) | 2010-03-29 | 2010-03-29 | Address translation method for flash storage FTL |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101833510B (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102495766A (en) * | 2011-11-30 | 2012-06-13 | 清华大学 | Consistency detection system of equipment specification and equipment behavior |
| CN102521144A (en) * | 2011-12-22 | 2012-06-27 | 清华大学 | Flash translation layer system |
| CN102819496A (en) * | 2012-08-16 | 2012-12-12 | 无锡紫芯集成电路系统有限公司 | Address translation method of flash FTL (Flash Translation Layer) |
| CN103176916A (en) * | 2013-03-07 | 2013-06-26 | 中国科学院苏州纳米技术与纳米仿生研究所 | Flash memory and address transfer approach thereof |
| CN103440206A (en) * | 2013-07-25 | 2013-12-11 | 记忆科技(深圳)有限公司 | Solid state hard disk and mixed mapping method of solid state hard disk |
| CN103019958B (en) * | 2012-10-31 | 2015-11-18 | 香港应用科技研究院有限公司 | Usage data attribute manages the method for the data in solid-state memory |
| CN108595349A (en) * | 2017-12-28 | 2018-09-28 | 贵阳忆芯科技有限公司 | The address conversion method and device of mass-memory unit |
| WO2020015133A1 (en) * | 2018-07-20 | 2020-01-23 | 江苏华存电子科技有限公司 | Relational garbage data collection method |
| US20210004272A1 (en) * | 2018-03-09 | 2021-01-07 | Samsung Electronics Co., Ltd | Electronic device and method for controlling same |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101169751A (en) * | 2006-10-25 | 2008-04-30 | 三星电子株式会社 | System with flash memory device and data recovery method thereof |
| US20080126684A1 (en) * | 2006-11-23 | 2008-05-29 | Genesys Logic, Inc. | Caching method for nand flash translation layer |
| US20080183955A1 (en) * | 2007-01-25 | 2008-07-31 | Genesys Logic, Inc. | Flash translation layer apparatus |
| CN101673581A (en) * | 2008-06-13 | 2010-03-17 | 三星电子株式会社 | Memory system and method of accessing a semiconductor memory device |
-
2010
- 2010-03-29 CN CN201010133944A patent/CN101833510B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101169751A (en) * | 2006-10-25 | 2008-04-30 | 三星电子株式会社 | System with flash memory device and data recovery method thereof |
| US20080126684A1 (en) * | 2006-11-23 | 2008-05-29 | Genesys Logic, Inc. | Caching method for nand flash translation layer |
| US20080183955A1 (en) * | 2007-01-25 | 2008-07-31 | Genesys Logic, Inc. | Flash translation layer apparatus |
| CN101673581A (en) * | 2008-06-13 | 2010-03-17 | 三星电子株式会社 | Memory system and method of accessing a semiconductor memory device |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102495766A (en) * | 2011-11-30 | 2012-06-13 | 清华大学 | Consistency detection system of equipment specification and equipment behavior |
| CN102521144B (en) * | 2011-12-22 | 2015-03-04 | 清华大学 | Flash translation layer system |
| CN102521144A (en) * | 2011-12-22 | 2012-06-27 | 清华大学 | Flash translation layer system |
| CN102819496A (en) * | 2012-08-16 | 2012-12-12 | 无锡紫芯集成电路系统有限公司 | Address translation method of flash FTL (Flash Translation Layer) |
| CN102819496B (en) * | 2012-08-16 | 2015-02-18 | 常州新超电子科技有限公司 | Address translation method of flash FTL (Flash Translation Layer) |
| CN103019958B (en) * | 2012-10-31 | 2015-11-18 | 香港应用科技研究院有限公司 | Usage data attribute manages the method for the data in solid-state memory |
| CN103176916A (en) * | 2013-03-07 | 2013-06-26 | 中国科学院苏州纳米技术与纳米仿生研究所 | Flash memory and address transfer approach thereof |
| CN103176916B (en) * | 2013-03-07 | 2016-03-09 | 中国科学院苏州纳米技术与纳米仿生研究所 | The address conversion method of flash memory and flash memory |
| CN103440206A (en) * | 2013-07-25 | 2013-12-11 | 记忆科技(深圳)有限公司 | Solid state hard disk and mixed mapping method of solid state hard disk |
| CN103440206B (en) * | 2013-07-25 | 2016-06-01 | 记忆科技(深圳)有限公司 | A kind of solid state hard disc and mixed-use developments method thereof |
| CN108595349A (en) * | 2017-12-28 | 2018-09-28 | 贵阳忆芯科技有限公司 | The address conversion method and device of mass-memory unit |
| CN108595349B (en) * | 2017-12-28 | 2020-01-31 | 贵阳忆芯科技有限公司 | Address translation method and device for mass storage device |
| US20210004272A1 (en) * | 2018-03-09 | 2021-01-07 | Samsung Electronics Co., Ltd | Electronic device and method for controlling same |
| WO2020015133A1 (en) * | 2018-07-20 | 2020-01-23 | 江苏华存电子科技有限公司 | Relational garbage data collection method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101833510B (en) | 2012-10-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101833510B (en) | Address translation method for flash storage FTL | |
| CN100573476C (en) | Flash memory medium data management method | |
| TWI506430B (en) | Method of recording mapping information method, and memory controller and memory storage apparatus using the same | |
| EP2319047B1 (en) | Multiple performance mode memory system | |
| EP2519880B1 (en) | Micro-update architecture for address tables | |
| CN101320594B (en) | Physical operation method of flash memory chip | |
| CN102841851B (en) | Flash memory management method and flash memory device | |
| US20140372685A1 (en) | Memory system, data storage device, user device and data management method thereof | |
| US20100070688A1 (en) | Flash memory device and method for writing data thereto | |
| US9021218B2 (en) | Data writing method for writing updated data into rewritable non-volatile memory module, and memory controller, and memory storage apparatus using the same | |
| CN104102585A (en) | Mapping information recording method, memory controller and memory storage device | |
| CN102142277A (en) | Memory and memory read-write control method and system | |
| US20140019670A1 (en) | Data writing method, memory controller, and memory storage device | |
| CN101556555B (en) | Block managing method for flash memory as well as controller and storage system thereof | |
| CN104424103A (en) | Management method for cache in solid state storage device | |
| CN105278875A (en) | Hybrid heterogeneous NAND solid state device | |
| CN102214143A (en) | Method and device for managing multilayer unit flash memory, and storage equipment | |
| TW201945927A (en) | Data writing method, memory control circuit unit and memory storage apparatus | |
| CN104679440A (en) | Flash memory array management method and device | |
| CN101425338B (en) | Writing method for nonvolatile memory and controller using the method | |
| CN102096679A (en) | Method and device for merging and writing index segments in disk | |
| CN103034586B (en) | By method and the system thereof of flash translation layer (FTL) identification upper layer application | |
| CN101324899B (en) | Method for rapidly writing NAND type FLASH | |
| CN103309619A (en) | NAND Flash memory data storage method | |
| CN102763070B (en) | The management method of disk buffering and device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20121010 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |