JP2010243776A - Lcd driver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an LCD (Liquid Crystal Display) driver capable of preventing deterioration in image quality on the vision of displayed images even if a transfer error occurs in image data transferred at high speed. <P>SOLUTION: An error detection part 1 uses error check data EC added to R, G and B data of each pixel of received image data converted from a serial form to a parallel form by a serial/parallel conversion part 100 to detect the transfer error of the received image data by a pixel unit. A latch 2 stores the received image data for one line by a pixel unit. When the transfer error is detected by the error detection part 1, a latch pulse control part 3 suppresses the transmission of a latch pulse to the latch corresponding to the pixel from which the transfer error is detected so as not to store the data of the pixel into the latch 2. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an LCD driver.

  In recent years, with an LCD (liquid crystal display) used in a display device such as a TV, the transfer speed of image data transferred from a video processing unit has increased as the screen size has increased. However, when performing high-speed data transfer, the amount of high-speed operation is easily affected by accidental signal level fluctuations or transmission timing fluctuations, and transfer errors are likely to occur. The current LCD driver converts the received digital image data into analog data and transmits it to the LCD. Therefore, if the image data in which a transfer error has occurred is displayed as it is, the difference between adjacent pixels is noticeable and the image quality is low. The problem of deterioration occurs.

  Conventionally, for such a transfer error problem of image data, error detection data is added for each line of image data, and whether or not there is an error in the received image data using this error detection data, When an error is detected, an image display apparatus has been proposed that does not write the data of the line to the frame memory and requests the transmission side to retransmit the data of the line (see, for example, Patent Document 1).

  In this proposed image display apparatus, it is possible to receive image data in which no error is detected by repeating transmission of the same image data. However, in the case of a TV broadcast display or the like, it is necessary to display the image data transferred at high speed immediately in order, and the above-described conventional data processing method has a problem that the image display cannot be performed in time.

JP 2006-191188 A (page 10-12, FIG. 1)

  SUMMARY OF THE INVENTION An object of the present invention is to provide an LCD driver that can prevent deterioration in visual image quality of a displayed image even if a transfer error occurs in image data transferred at high speed.

  According to one aspect of the present invention, using error check data added to each pixel of received image data, error detection means for detecting a transfer error of the received image data in units of pixels, and latch pulses in units of pixels And a means for controlling the transmission of the latch pulse in pixel units with respect to the latch, wherein the transfer error is detected by the error detecting means. And a latch pulse control means for suppressing transmission of a latch pulse to the latch corresponding to the pixel so that the latch does not store the data of the pixel in which the transfer error is detected when detected. An LCD driver is provided.

  According to the present invention, even when a transfer error occurs in image data that is transferred at high speed, it is possible to prevent deterioration in visual image quality of a display image.

The figure which shows the structure of the image data for 1 pixel. 1 is a block diagram showing an example of the configuration of an LCD driver according to Embodiment 1 of the present invention. The block diagram which shows the example of a structure of the error detection part of the Example of this invention. The block diagram which shows the example of a structure of the latch pulse control part of the Example of this invention. The wave form diagram which shows the example of operation | movement of the latch pulse control part of the Example of this invention. The figure which shows the example of the output data of the latch at the time of error detection. FIG. 6 is a block diagram showing an example of the configuration of an LCD driver according to Embodiment 2 of the present invention. The figure which shows the relationship between the value of the upper bit of image data, and AD conversion output. FIG. 10 is a block diagram showing an example of the configuration of an LCD driver according to Embodiment 3 of the present invention. The figure which shows the example of the data transfer by a mini-LVDS format. FIG. 9 is a block diagram showing an example of the configuration of an LCD driver according to Embodiment 4 of the present invention.

  In the case of display of TV broadcasting, etc., statistically, adjacent pixels have a high correlation of pixel data, and there is a high probability that they will be the same color or close colors. Therefore, in the present invention, the presence or absence of a transfer error in the received image data is detected for each pixel, and when a transfer error is detected, pixel data of the same pixel column one line before is output.

  In order to detect a transfer error for each pixel, in the present invention, error check data is added to the pixel data transmitted to the LCD driver.

  FIG. 1 shows an example of the configuration of pixel data transmitted to the LCD driver of the present invention.

  In the pixel data transmitted to the LCD driver of the present invention, error check data EC for R, G, B data is added to each R, G, B data for one pixel. As an error check method, CRC or parity check is used.

  Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated.

  FIG. 2 is a block diagram illustrating an example of the configuration of the LCD driver according to the first embodiment of the present invention.

  The LCD driver of this embodiment uses error check data EC added to R, G, and B data for each pixel of received image data converted from the serial format to the parallel format by the serial-parallel converter 100. When a transfer error is detected by the error detector 1 that detects the transfer error of the received image data in units of pixels, a latch 2 that stores the received image data for one line in units of pixels, and the error detector 1 And a latch pulse control unit 3 that suppresses transmission of the latch pulse to the latch that stores the data of the pixel in which the transfer error is detected.

  The error detection unit 1 generates error check data EC0 for each pixel from the received image data, and compares them with the error check data EC added to each pixel of the received image data. It is determined that a transfer error has been detected.

  The latch 2 stores the received image data for one line in pixel units according to the latch pulse in pixel units. That is, assuming that m pixels are included in one line, the latch 2 is configured by latches LT1 to LTm that store R, G, and B data of each pixel.

  The latch 2 output is converted into a gradation voltage to be output to the LCD by a DA converter (not shown).

  The latch pulse control unit 3 receives input of CK1 to CKm, which are basic latch pulses for the latches LT1 to LTm constituting the latch 2, and controls generation of latch pulses CP1 to CPm to be supplied to the latches LT1 to LTm. To do.

  At that time, when a transfer error is detected by the error detection unit 1, the latch pulse is transmitted to the latch corresponding to the pixel in units of pixels so that the latch does not store the data of the pixel in which the transfer error is detected. Deter.

  However, when the Line 1 signal indicating that the received image data is the image data of the first line is input, the latch pulse transmission is not suppressed.

  FIG. 3 shows an example of the internal configuration of the error detection unit 1.

  In the example illustrated in FIG. 3, the error detection unit 1 includes an error check data generation unit 11 that generates error check data EC0 from R, G, and B data output from the serial-parallel conversion unit 100, and an error check data generation unit. 11 includes a comparison unit 12 that compares the error check data EC0 generated by the error check data EC0 output from the serial-parallel conversion unit 100.

  The comparison unit 12 outputs the comparison result as an error detection signal ERR. Here, when EC0 ≠ EC, that is, when there is a transfer error in R, G, B data, the error detection signal ERR = '0' (with transfer error) is output, and when EC0 = EC Output an error detection signal ERR = “1” (no transfer error).

  FIG. 4 shows an example of the internal configuration of the latch pulse control unit 3. Here, when the received image data is the image data of the first line, Line1 = ‘1’ is input.

  The latch pulse control unit 3 includes basic latch pulses CK1 to CKm for the OR gate OR1 to which the error detection signal ERR and the Line1 signal output from the error detection unit 1 are input, and the latches LT1 to LTm constituting the latch 2, respectively. AND gates AN1 to ANm to which outputs of the OR gate OR1 are respectively input.

  The outputs of the AND gates AN1 to ANm become latch pulses CP1 to CPm supplied to the latches LT1 to LTm, respectively.

  The OR gate OR1 outputs “1” when Line1 = “1”, that is, when the received image data is the image data of the first line. Accordingly, at this time, the basic latch pulses CK1 to CKm are output as they are to the outputs CP1 to CPm of the AND gates AN1 to ANm.

  On the other hand, when Line1 = “0”, that is, when the received image data is image data for the second and subsequent lines, the output of the OR gate OR1 changes depending on the value of the error detection signal ERR.

  At this time, when the error detection signal ERR = “1” (no transfer error), the output of the OR gate OR1 = “1”. Therefore, in this case, the basic latch pulses CK1 to CKm are output as they are to the outputs CP1 to CPm of the AND gates AN1 to ANm.

  On the other hand, when the error detection signal ERR = “0” (there is a transfer error), the output of the OR gate OR1 = “0”. In this case, the outputs CP1 to CPm of the AND gates AN1 to ANm are “0”, and the transmission of the latch pulses CK1 to CKm to the latches LT1 to LTm is suppressed.

  When the latch pulses CP1 to CPm are “0”, data rewriting to the latches LT1 to LTm does not occur.

  FIG. 5 is a waveform diagram showing an example of the operation of the latch pulse control unit 3.

  Line1 = “1”, that is, when the received image data is the image data of the first line, for example, even if an error is detected in the image data of the second pixel and “0” is output to the error detection signal ERR The basic latch pulse CK2 is output as it is as the latch pulse CP2 for the latch LT2 of the second pixel.

  Therefore, in this case, pixel data with a transfer error is written in the latch LT2 of the second pixel, but the first line is the upper end of the screen, and even if there is an error in the image data, There is almost no problem visually.

  On the other hand, when Line1 = “0”, that is, when the received image data is the image data of the second line and thereafter, for example, an error is detected in the image data of the second pixel, and “0” is output to the error detection signal ERR. Suppose that In this case, as for the latch pulse CP2 for the latch LT2 of the second pixel, transmission of the basic latch pulse CK2 is suppressed, and “0” is output.

  Therefore, in this case, writing of pixel data having a transfer error to the latch LT2 of the second pixel does not occur. In this case, the pixel data written before is held in the latch LT2 of the second pixel as it is.

  FIG. 6 shows an output state of the latch 2 when a transfer error as described above is detected.

Now, when the pixel data D1 _{n to} Dmn of the _{nth line} are written in the latches LT1 to LTm of the latch 2, the image data D1 _{n + 1 to} Dmn _{+ 1 of the} ( _{n + 1} ) _th line is received, and the pixel of the second pixel transfer error in the data D2 n _{+ 1} is to have been detected.

In this case, the the second pixel latch LT2, not performed the writing of the pixel data _{D2 n + 1,} pixel data D2 _n of one line before is held as it is.

That is, the second pixel of the output of the (n + 1) th line of the latch 2, transmission error instead of the pixel data D2 n _{+ 1,} which is detected, the pixel data D2 _n of one line before is output.

In general, since the correlation between the pixel data between the upper and lower pixels is high, the display image quality is deteriorated when the pixel data D2 _n one line before is displayed rather than the pixel data D2 _{n + 1} in which the transfer error is detected. Can be prevented.

  According to the present embodiment, the presence / absence of a transfer error is detected for each pixel of the received image data, and when the occurrence of the transfer error is detected, the latch pulse is transmitted to the latch for storing the pixel data. Deter. As a result, the pixel data of the previous line is held in the latch. As a result, the pixel data of the previous line having high correlation with the pixel data of the current line can be output instead of the pixel data in which the transfer error has occurred, and the visual image quality of the display image can be prevented from deteriorating.

  Further, even if a transfer error occurs, it is only necessary to control the latch pulse, and it is not necessary to retransmit the image data. Therefore, high-speed operation such as TV broadcast display can be performed.

  FIG. 7 is a block diagram illustrating an example of the configuration of the LCD driver according to the second embodiment of the present invention.

  In this embodiment, each of the latches LT1 to LTm of the latch 2 is divided into upper bit side latches LT1U to LTmU and lower bit side latches LT1L to LTmL.

  For example, when the R, G, B data of each pixel is 8 bits ([7: 0]), the upper 4 bits ([7: 4]) are stored in the upper bit side latches LT1U to LTmU, The lower 4 bits ([3: 0]) are stored in the lower bit latches LT1L to LTmL.

  At this time, only the latch pulses supplied to the upper bit side latches LT1U to LTmU are CP1 to CPm output from the latch pulse control unit 3, and the latch pulses supplied to the lower bit side latches LT1L to LTmL are the basic latch pulses. CK1 to CKm.

  Therefore, in this embodiment, when a transfer error occurs in the received image data, data rewriting to LT1U to LTmU of the upper bit side latch does not occur, but data rewriting to the lower bit side latches LT1L to LTmL occurs. To do.

  As a result, there is a possibility that error data is written to the lower bit side latches LT1L to LTmL. However, since the grayscale output voltage after DA conversion has the display data value approximately determined by the higher-order bits, the influence of the error of the lower-order bit data on the image quality is small and does not cause a visual problem.

  FIG. 8 is a graph showing the relationship between the higher-order bits and the gradation output voltage when the image data is 8 bits.

  As shown in FIG. 8, since the grayscale output voltage after DA conversion is substantially determined by the upper bits, the value of the display data is determined. Therefore, if countermeasures against transfer errors are applied only to the upper bits, that is, the pixel data of the previous line. If this is maintained, it is possible to prevent visual image quality deterioration.

  According to the present embodiment, the latch pulse control unit 3 only needs to supply the latch pulse to the upper bit side latches LT1U to LTmU, so that the output load is reduced and there is a margin for high-speed operation. it can.

  When the number of bits of R, G, and B data of each pixel is large, when the error check data EC is generated from all the bits, the number of bits of the error check data EC also increases. As a result, the scale of the circuit that performs error checking increases and the amount of transfer data also increases. When the amount of transfer data increases, it is necessary to further increase the transfer speed, leading to an increase in current consumption.

  However, as shown in FIG. 8, the magnitude of the gradation voltage is largely determined by the upper bits. Therefore, the quality of the display image can be ensured only by detecting the transfer error of the higher-order bits of the R, G, B data.

  Therefore, in this embodiment, it is assumed that the error check data EC added for each pixel of the received image data is generated from the upper bits of the pixel data.

  FIG. 9 is a block diagram illustrating an example of the configuration of the LCD driver according to the third embodiment of the present invention.

  In the present embodiment, the error check data EC added to each pixel of the received image data is generated from the higher-order bits of the pixel data, and the data input to the error detection unit 1 is the pixel data Only the upper bit data. For example, if the R, G, B data of each pixel is 10 bits ([9: 0]), only the upper 5 bits ([9: 5]) data is input to the error detection unit 1. The

  The error detector 1 generates error check data EC0 from the 5-bit data, and compares it with the error check data EC output from the serial-parallel converter 100, thereby detecting a transfer error.

  FIG. 10 shows an example of data transfer in the mini-LVDS format that is often used for image data transfer to the LCD. In mini-LVDS, a clock and image data are transmitted as a differential signal with a small amplitude.

When transferring 10 bits of R, G, B data and a total of 30 bits with this mini-LVDS, using 4 differential terminals, D0 +/−, D1 +/−, D2 +/−, D3 +/−, 1 In general, a pixel is handled as 32-bit data. Therefore, 2 free bits are generated for 30 bits of R, G, B data.
Normally, dummy data is inserted into these 2 bits, but in this embodiment, error check data EC1 and EC2 are inserted into these 2 bits.

Thereby, the error check data EC can be transmitted without increasing the number of bits of the transfer data. According to this embodiment, the error check data EC is generated from the upper bits of the pixel data. Thus, the number of bits of the error check data EC can be reduced. For example, data can be efficiently transferred by utilizing the free bits of the mini-LVDS.

  FIG. 11 is a block diagram illustrating an example of the configuration of the LCD driver according to the fourth embodiment of the present invention.

  In this embodiment, the latch 2 of the LCD driver of the third embodiment is divided into upper bit side latches LT1U to LTmU and lower bit side latches LT1L to LTmL as in the second embodiment, and upper bit side latches LT1U to LTmU. The latch pulses to be supplied to CP1 to CPm output from the latch pulse control unit 3 and the latch pulses to be supplied to the lower bit side latches LT1L to LTmL are basic latch pulses CK1 to CKm.

  Thereby, the LCD driver of the present embodiment can have the effect of the LCD driver of the second embodiment in addition to the effect of the LCD driver of the third embodiment.

DESCRIPTION OF SYMBOLS 1 Error detection part 2 Latch 3 Latch pulse control part 11 Error check data generation part 12 Comparison part AN1-ANm AND gate OR1 OR gate

Claims (5)

Using error check data added to each pixel of the received image data, error detection means for detecting a transfer error of the received image data in units of pixels;
A latch for storing the received image data for one line in pixel units in response to a latch pulse in pixel units;
Means for controlling transmission of the latch pulse in pixel units to the latch,
When the transfer error is detected by the error detection means, the latch pulse is transmitted to the latch corresponding to the pixel in units of pixels so that the latch does not store the data of the pixel in which the transfer error is detected. An LCD driver comprising latch pulse control means for inhibiting. The error detection means is
Generate error check data for each pixel from the received image data,
Compared with the error check data added for each pixel of the received image data,
2. The LCD driver according to claim 1, wherein it is determined that the transfer error is detected when the two do not match. 3. The LCD according to claim 2, wherein the error check data added to each pixel of the received image data and the error check data generated by the error detection means are generated from upper bits of the pixel data. driver. The latch pulse control means;
4. The LCD driver according to claim 1, wherein transmission of the latch pulse is suppressed only for a latch that stores upper bits of pixel data. 5. The latch pulse control means;
5. The LCD driver according to claim 1, wherein when the received image data of the first line of the display line is received, transmission of the latch pulse is not suppressed. 6.

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