CN114002581B - Method for detecting interconnection condition of inside of flip chip of focal plane array detector - Google Patents
Method for detecting interconnection condition of inside of flip chip of focal plane array detector Download PDFInfo
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- CN114002581B CN114002581B CN202111288180.4A CN202111288180A CN114002581B CN 114002581 B CN114002581 B CN 114002581B CN 202111288180 A CN202111288180 A CN 202111288180A CN 114002581 B CN114002581 B CN 114002581B
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- 238000000034 method Methods 0.000 title claims abstract description 36
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 12
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- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 6
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Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
- G01R31/2836—Fault-finding or characterising
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
- G01N21/84—Systems specially adapted for particular applications
- G01N21/88—Investigating the presence of flaws or contamination
- G01N21/95—Investigating the presence of flaws or contamination characterised by the material or shape of the object to be examined
- G01N21/956—Inspecting patterns on the surface of objects
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N23/00—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00
- G01N23/22—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00 by measuring secondary emission from the material
- G01N23/225—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00 by measuring secondary emission from the material using electron or ion
- G01N23/2251—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00 by measuring secondary emission from the material using electron or ion using incident electron beams, e.g. scanning electron microscopy [SEM]
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
Abstract
The invention relates to a detection method of interconnection condition inside a flip chip of a focal plane array detector, which comprises the steps of respectively drawing a first mark and a second mark at positions corresponding to blemishes on two sides of the chip; forming a first scribing channel at the detector end of the chip to be inspected and forming a second scribing channel at the reading circuit end by taking a connecting line of the trace of the first mark and the trace of the second mark as a scribing track; placing the chip to be inspected on a cooling clamp for fixing, and pouring liquid nitrogen to enable the position of the chip to be inspected along the scribing channel to form a neat chip fracture surface; the state of bump connection in the chip is checked by chip breaking surface using a microscope or SEM. According to the invention, the chip anatomical position and the flaw position in the electrical performance test can be subjected to pixel-level correspondence, and the method can be suitable for positioning and dissecting of focal plane chips with the bump pitches of 10 mu m; can provide an effective means for the quality technical analysis of the reverse welding process of the micron-sized interval focal plane chip, so as to be beneficial to the improvement of the reverse welding interconnection quality.
Description
Technical Field
The invention belongs to the technical field of semiconductor photoelectrons, and relates to a detection method for internal interconnection conditions of a flip chip of a focal plane array detector.
Background
The flaw point (i.e. blind pixel) of the focal plane detector chip is easy to position the position of the flaw on the chip according to the coordinate position of the flaw in the imaging test process, but after the positioning, the difficulty is high when the observation of the bump interconnection condition is further carried out on the appointed position inside the chip. In the prior art, inspection is generally performed according to the output condition of an electric signal, or perspective inspection is performed by X-ray and ultrasonic waves. However, the former is limited by the circuit structure and is not applicable to all flip chips, the latter is limited by the resolution of the device, and for chips with array pitches below the order of 100 μm, the image is almost black-painted, and it is difficult to obtain a clear image of the internal bumps. Therefore, for chips with bump pitches of 100 μm or less, it is necessary to analyze the inside of the chip by means of dissection.
With the development of focal plane detector technology, the positional accuracy of chip dissection requires increasingly accurate. In general, the optimal solution area of the focal plane chip is a blank area between the bumps, and at present, the bump pitch of the focal plane device is reduced to be less than 10 μm, and the size of the blank area between the bumps is only less than 3 μm. The traditional dissection method adopts a thinning process to thin the chip according to the required thickness from the side surface of the chip, the method has small damage to the internal structure of the chip, but the processing time is long, the process efficiency is extremely low, the processing time of one chip is generally more than 4 hours, the thinning precision is difficult to control, and the shutdown inspection is continuously carried out when the chip is close to the position of the target thickness so as to ensure that the dissection surface is positioned at the accurate position; the accuracy of the pixel level is difficult to ensure, and the pixel level positioning requirement of the 10 mu m bump pitch device cannot be met. Therefore, the method of using conventional chip dissection is very difficult.
Disclosure of Invention
In view of the above, the present invention is directed to a method for detecting interconnection conditions inside a flip chip of a focal plane array probe.
In order to achieve the above purpose, the present invention provides the following technical solutions:
a detection method for internal interconnection condition of a flip chip of a focal plane array detector comprises the following steps:
s1, determining the position of a flaw on a chip to be checked by power-up measurement;
s2, respectively marking a first mark and a second mark at positions corresponding to the defects on the two sides of the chip by using a laser point light source;
s5, the detector end of the chip to be inspected is upwards, the central positions of the marks of the first mark and the second mark are respectively used as alignment mark positions, the connecting lines of the two alignment mark positions on the detector unit are used as scribing tracks, a scribing machine is used for scribing, a first scribing channel is formed, and the depth of the first scribing channel is smaller than the thickness of the detector unit;
s6, taking the central positions of marks of the first mark and the second mark as alignment mark positions, taking a connecting line of the two alignment mark positions on the reading circuit unit as a scribing track, and scribing by using a scribing machine to form a second scribing channel, wherein the depth of the second scribing channel is smaller than the thickness of the reading circuit unit;
s7, placing the chip to be inspected on a cooling clamp for fixing, pouring liquid nitrogen into the clamp injection hole, and enabling the chip to be inspected to form a neat chip fracture surface along the position of the scribing channel under the action of internal stress;
s8, checking the bump connection state in the chip through chip fracture surface by adopting a microscope or SEM.
Further, the array pitch of the chip to be inspected is greater than or equal to 10 μm.
Further, the first mark and the second mark are through grooves vertically penetrating through the side face of the chip to be inspected.
Further, the groove widths of the first mark and the second mark are smaller than 0.1mm.
Further, after the step S2 is performed, the following steps are performed:
s3, enabling the detector end of the chip to be inspected to face upwards, and using a laser point light source to mark a third mark within a range of 0.5-1.0 pixel interval from the flaw;
s4, respectively taking the central positions of the marks of the first mark and the second mark on the detector unit as alignment mark positions, connecting the two alignment mark positions, and executing a step S5 if the connecting line passes through a third mark; otherwise, the step S2 is executed back.
Further, the third mark is a dot-shaped pit, and the radius of the pit is 2-3 μm.
Further, in the step S5, the dicing rotational speed of the dicing saw is 3500 to 4000 revolutions and the feeding speed is 0.5mm/S.
Further, in the step S5, the dicing blade height of the dicing saw is set according to the following formula:
h1＝d2+D1
wherein h1 represents the set height of the dicing blade when dicing on the detector unit; d2 represents the thickness of the readout circuit unit; d1 represents the thickness of the detector unit after dicing, and the value range is 0.1 mm-0.15 mm.
Further, in the step S6, the dicing rotational speed of the dicing saw is 3500 to 4000 revolutions and the feeding speed is 0.8m/S.
Further, in the step S6, the height of the dicing blade of the dicing machine is set according to the following formula:
h2＝d1+D2
wherein h2 represents the set height of the dicing blade when dicing on the read-out circuit unit; d1 represents the thickness of the detector unit; d2 represents the thickness of the read-out circuit unit after dicing, and the value range is 0.15 mm-0.18 mm.
According to the invention, through sample preparation of the flip chip, pixel-level correspondence can be carried out on the anatomical position of the chip and the flaw position in the electrical property test, so that the method is applicable to positioning and dissection of focal plane chips with the bump pitches of 10 mu m; after the dissection is finished, the bump interconnection condition at the flaw position can be accurately observed to judge whether the flaw caused by cold joint, off-joint or other non-interconnection exists at the interconnection position; the method can provide an effective means for the quality technical analysis of the reverse welding process of the micron-scale interval focal plane chip, so as to be beneficial to the improvement of the reverse welding interconnection quality.
Drawings
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in the following preferred detail with reference to the accompanying drawings, in which:
FIG. 1 is a flow chart of a method for detecting interconnection in a flip chip of a focal plane array probe according to a preferred embodiment of the present invention.
Fig. 2 is a schematic diagram after forming a first mark and a second mark on a chip to be inspected.
FIG. 3 is a schematic view of a third mark, a pixel bump, and a defect point corresponding bump.
Fig. 4 is a schematic view of a first scribe lane and a second scribe lane.
In the figure: 1. the image sensor comprises a detector unit, a read-out circuit unit, a pixel array, a first scribing channel, a first mark, a second mark, a third mark, a second scribing channel, a pixel bump and a defect point, wherein the pixel array is arranged in the first scribing channel, the first mark, the second mark, the third mark, the second scribing channel, the pixel bump and the defect point correspond to the bump.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention. It should be noted that the illustrations provided in the following embodiments merely illustrate the basic idea of the present invention by way of illustration, and the following embodiments and features in the embodiments may be combined with each other without conflict.
As shown in fig. 1, a preferred embodiment of a method for detecting interconnection conditions inside a flip chip of a focal plane array detector according to the present invention includes the following steps:
s1, determining the position of a flaw on a chip to be checked through power-up measurement. Wherein the array pitch of the chip to be inspected is greater than or equal to 10 μm. As shown in fig. 2, the flip chip of the focal plane array detector comprises a detector unit 1 and a readout circuit unit 2, wherein the detector unit 1 is provided with a pixel array 3; since the blemish cannot produce a photoelectric effect, the location of the blemish can be clearly found from the array of picture elements 3 after power-up.
S2, respectively marking a first mark 11 and a second mark 12 at positions corresponding to the defects on the two sides of the chip to be inspected by using a laser point light source, and using the first mark and the second mark as guiding marks for subsequent scribing and positioning. As shown in fig. 2, it is preferable to use a laser point light source to respectively scribe through grooves vertically penetrating through corresponding sides on two sides of a chip to be inspected as a first mark 11 and a second mark 12; the groove widths of the first mark 11 and the second mark 12 are preferably less than 0.1mm.
S3, as shown in FIG. 3, the detector end of the chip to be inspected is upward, and a laser point light source is used for describing a third mark 13 within a range of 0.5-1.0 pixel interval (the pixel interval is the interval between two pixel center points) from the flaw point so as to conveniently inspect whether the position selection of the first mark 11 and the second mark 12 is proper or not; the third mark 13 is preferably a dot-shaped pit marked by a laser point light source, and the radius of the pit is preferably 2-3 μm.
S4, respectively taking the central positions of the marks of the first mark 11 and the second mark 12 as alignment mark positions on the detector unit 1, connecting lines (shown by dotted lines in fig. 2 and 3) along the two alignment mark positions, and if the connecting lines pass through the third mark 13, indicating that the positions of the first mark 11 and the second mark 12 are properly selected, and executing the step S5; otherwise, the positions of the first mark 11 and the second mark 12 are not properly selected, and the step S2 is performed again to reselect the positions of the first mark 11 and the second mark 12. By arranging the third mark 13, whether the position selection of the first mark 11 and the second mark 12 is proper or not can be judged in advance, so that the situation that the connection condition of the corresponding salient point 32 of the flaw point cannot be observed on the chip fracture surface or the current connection situation of the corresponding salient point 32 of the flaw point is damaged in the process of forming the chip fracture surface due to the deviation of the positions of the first mark 11 and the second mark 12 is avoided.
S5, as shown in FIG. 4, the probe end of the chip to be inspected is upward, the central positions of the marks of the first mark 11 and the second mark 12 are respectively used as alignment mark positions, the connecting lines of the two alignment mark positions on the probe unit are used as scribing tracks, a scribing machine is used for scribing, and a first scribing channel 10 is formed, wherein the depth of the first scribing channel 10 is smaller than the thickness of the probe unit 1. During dicing, the dicing rotating speed of the dicing saw is 3500-4000 revolutions, and the feeding speed is 0.5mm/s. And the dicing blade height of the dicing saw (i.e., the clearance below the dicing blade) is set according to the following formula:
h1＝d2+D1
wherein h1 represents the set height of the dicing blade at the time of dicing on the detector unit 1; d2 denotes the thickness of the readout circuit unit 2; d1 represents the thickness of the detector unit 1 after dicing, and the value range is 0.1 mm-0.15 mm, preferably 0.15mm; leaving the detector unit 1 to be 0.15mm thick after dicing.
S6, taking the central positions of the marks of the first mark 11 and the second mark 12 as alignment mark positions and the connecting lines of the two alignment mark positions on the reading circuit unit as scribing tracks, and scribing by using a scribing machine to form a second scribing channel 20, wherein the depth of the second scribing channel 20 is smaller than the thickness of the reading circuit unit 2. During dicing, the dicing rotating speed of the dicing saw is 3500-4000 revolutions, and the feeding speed is 0.8m/s. And the dicing blade height of the dicing saw is set according to the following formula:
h2＝d1+D2
wherein h2 represents the set height of the dicing blade at the time of dicing on the readout circuit unit 2; d1 denotes the thickness of the detector unit 1; d2 represents the remaining thickness of the read-out circuit unit 2 after dicing, and the value range is 0.15mm to 0.18mm, preferably 0.18mm; so that the read-out circuit unit 2 remains 0.18mm thick after dicing.
S7, placing the chip to be inspected on a cooling clamp for fixing, pouring liquid nitrogen into the clamp injection hole, and enabling the chip to be inspected to form a finished and tidy chip fracture surface with indium columns along the position of the scribing channel under the action of internal stress. The specific principle is as follows:
the low temperature of the liquid nitrogen is conducted to the chip to be inspected by the clamp, and internal stress is generated in the chip to be inspected due to the fact that the thermal expansion coefficients of the chip to be inspected and the clamp are not matched; under the continuous action of internal stress, the chip forms a finished and tidy chip fracture surface along the position of the scribing channel. The whole scribing and cleavage process is free from contact with the inside of the chip, the connection state of the inside of the chip is reserved to the maximum extent, the state of bump interconnection in the chip can be effectively obtained, the positioning precision of the dissection method is high (less than or equal to 3 mu m), and the requirements of pixel-level defect analysis, which are required by the flip chip of the focal plane bump array with the distance of 10 mu m, are met.
S8, a microscope or SEM is adopted to directly check the connection state of the pixel convex points 31 and the convex points 32 corresponding to the flaw points in the chip through the fracture surface of the chip, so as to analyze the failure cause. Therefore, an effective means is provided for the quality technical analysis of the reflow process, so that the reflow interconnection quality in the chip manufacturing process is improved.
In the embodiment, the laser positioning method is adopted for pre-positioning, and a positioning reference with the precision within +/-3 mu m is provided for subsequent anatomical processing, so that the consistency of the anatomical section and the target position to be analyzed is ensured. In the cutting process, a double-sided cutting method is adopted, and the upper surface and the lower surface of the chip form complete cutting lines by restraining the rotating speed of the dicing blade and the height of the dicing blade, so that the internal salient points are not damaged. And finally, the final chip separation is completed through liquid nitrogen quenching and through the internal thermal mismatch stress of the chip. Thus, the chip dissection is completed at the designated position on the chip, and the ideal joint section of the target position is obtained. The chip is dissected by the method, the whole process does not contact with the internal convex points, the internal connection state of the chip is reserved to the maximum extent, and a perfect reverse welding chip section is finally formed by cleavage, and the chip can be directly observed by a microscope or SEM, so that the amplification factor and the acquired image quality are greatly improved. The method has strong applicability to the flip chip, can be completed by utilizing conventional equipment of a semiconductor process line, is simple to operate and is convenient to popularize and apply.
Finally, it is noted that the above embodiments are only for illustrating the technical solution of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications and equivalents may be made thereto without departing from the spirit and scope of the present invention, which is intended to be covered by the claims of the present invention.
Claims (10)
1. The method for detecting the interconnection condition of the inside of the flip chip of the focal plane array detector is characterized by comprising the following steps of:
s1, determining the position of a flaw on a chip to be checked by power-up measurement;
s2, respectively marking a first mark and a second mark at positions corresponding to the defects on the two sides of the chip by using a laser point light source;
s5, the detector end of the chip to be inspected is upwards, the central positions of the marks of the first mark and the second mark are respectively used as alignment mark positions, the connecting lines of the two alignment mark positions on the detector unit are used as scribing tracks, a scribing machine is used for scribing, a first scribing channel is formed, and the depth of the first scribing channel is smaller than the thickness of the detector unit;
s6, taking the central positions of marks of the first mark and the second mark as alignment mark positions, taking a connecting line of the two alignment mark positions on the reading circuit unit as a scribing track, and scribing by using a scribing machine to form a second scribing channel, wherein the depth of the second scribing channel is smaller than the thickness of the reading circuit unit;
s7, placing the chip to be inspected on a cooling clamp for fixing, pouring liquid nitrogen into the clamp injection hole, and enabling the chip to be inspected to form a neat chip fracture surface along the position of the scribing channel under the action of internal stress;
s8, checking the bump connection state in the chip through chip fracture surface by adopting a microscope or SEM.
2. The method for detecting the interconnection condition of the flip chip of the focal plane array detector according to claim 1, wherein the array pitch of the chip to be inspected is greater than or equal to 10 μm.
3. The method for detecting the interconnection condition of the flip chip of the focal plane array detector according to claim 1, wherein the first mark and the second mark are through grooves vertically penetrating through the side surface of the chip to be inspected.
4. The method for detecting interconnection of flip chip of focal plane array detector according to claim 3, wherein the groove widths of the first mark and the second mark are each smaller than 0.1mm.
5. The method for detecting interconnection between flip chips of a focal plane array probe according to claim 1, wherein after step S2 is performed, the following steps are performed:
s3, enabling the detector end of the chip to be inspected to face upwards, and using a laser point light source to mark a third mark within a range of 0.5-1.0 pixel interval from the flaw;
s4, respectively taking the central positions of the marks of the first mark and the second mark on the detector unit as alignment mark positions, connecting the two alignment mark positions, and executing a step S5 if the connecting line passes through a third mark; otherwise, the step S2 is executed back.
6. The method for detecting interconnection of flip chip of focal plane array detector according to claim 5, wherein the third mark is a dot-shaped pit, and the radius of the pit is 2-3 μm.
7. The method for detecting interconnection conditions in a flip chip of a focal plane array probe according to claim 1, wherein in the step S5, the dicing speed of the dicing machine is 3500-4000 revolutions and the feeding speed is 0.5mm/S.
8. The method for detecting interconnection of flip chip of focal plane array probe according to claim 1, wherein in the step S5, the height of the dicing blade of the dicing machine is set according to the following formula:
h1＝d2+D1
wherein h1 represents the set height of the dicing blade when dicing on the detector unit; d2 represents the thickness of the readout circuit unit; d1 represents the thickness of the detector unit after dicing, and the value range is 0.1 mm-0.15 mm.
9. The method for detecting interconnection of flip chips of focal plane array probe according to claim 1, wherein in the step S6, the dicing speed of the dicing machine is 3500-4000 turns, and the feeding speed is 0.8m/S.
10. The method for detecting interconnection of flip chip of focal plane array probe according to claim 1, wherein in the step S6, the height of a dicing blade of a dicing saw is set according to the following formula:
h2＝d1+D2
wherein h2 represents the set height of the dicing blade when dicing on the read-out circuit unit; d1 represents the thickness of the detector unit; d2 represents the thickness of the read-out circuit unit after dicing, and the value range is 0.15 mm-0.18 mm.
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