CN113998664A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN113998664A
CN113998664A CN202111212038.1A CN202111212038A CN113998664A CN 113998664 A CN113998664 A CN 113998664A CN 202111212038 A CN202111212038 A CN 202111212038A CN 113998664 A CN113998664 A CN 113998664A
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layer
etching
back cavity
forming
opening
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王续博
刘悦
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Shanghai Jiaotong University
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Shanghai Jiaotong University
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
    • B81C1/00523—Etching material
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B06—GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS IN GENERAL
    • B06B—METHODS OR APPARATUS FOR GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS OF INFRASONIC, SONIC, OR ULTRASONIC FREQUENCY, e.g. FOR PERFORMING MECHANICAL WORK IN GENERAL
    • B06B1/00—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency
    • B06B1/02—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency making use of electrical energy
    • B06B1/06—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency making use of electrical energy operating with piezoelectric effect or with electrostriction
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/02—Microstructural systems; Auxiliary parts of microstructural devices or systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00023—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems without movable or flexible elements
    • B81C1/00047—Cavities
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
    • B81C1/00523—Etching material
    • B81C1/00531—Dry etching
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
    • B81C1/00555—Achieving a desired geometry, i.e. controlling etch rates, anisotropy or selectivity
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
    • H04R19/00—Electrostatic transducers
    • H04R19/005—Electrostatic transducers using semiconductor materials
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2201/00—Specific applications of microelectromechanical systems
    • B81B2201/02—Sensors
    • B81B2201/0257—Microphones or microspeakers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2201/00—Specific applications of microelectromechanical systems
    • B81B2201/02—Sensors
    • B81B2201/0271—Resonators; ultrasonic resonators

Abstract

The application discloses a semiconductor structure and a forming method thereof, wherein the forming method of the semiconductor structure comprises the following steps: providing a substrate, wherein the substrate comprises a supporting layer, a stopping layer positioned on the surface of one side of the supporting layer and a device layer positioned on the surface of the stopping layer; forming a patterned mask layer on the other side surface of the supporting layer, wherein a plurality of back cavity openings with different sizes are formed in the patterned mask layer; and carrying out first etching along each back cavity opening to etch the supporting layer to the corresponding position of each back cavity opening, and then stopping after the stopping layer is exposed, thereby forming a plurality of back cavities with different sizes in the supporting layer. The above method reduces process complexity.

Description

Semiconductor structure and forming method thereof
Technical Field
The present application relates to the field of MEMS technology, and more particularly, to a semiconductor structure and a method for forming the same.
Background
An ultrasonic piezoelectric transducer can vibrate under the action of a driving voltage, and the vibration can be transmitted through a medium (such as water, a human body and the like). As a reverse application, the sound waves acting on the ultrasonic piezoelectric transducer can also generate an electrical signal, which can be read and recognized to reproduce the sound waves acting on the ultrasonic transducer. Based on the principle, the ultrasonic piezoelectric transducer can perform bidirectional conversion of electrical and acoustic signals and is widely applied to the fields of microphones, loudspeakers, gesture recognition, ultrasonic imaging, fingerprint recognition and the like.
Piezoelectric ultrasonic transducers obtained based on micromachining techniques are often referred to as PMUT (piezoelectric micromachined ultrasonic transducer). Fig. 1 is a schematic structural diagram of a back cavity PMUT in the prior art. The PMUT structurally generally comprises a support layer 11 having a back cavity 10 therein, a first electrode 12, a piezoelectric layer 13 and a second electrode 14 stacked in sequence on the support layer, the piezoelectric layer 13 being located between the first electrode 12 and the second electrode 14. Due to the existence of the back cavity 10, the layers above the supporting layer 11 work in a flextensional mode, and under the action of ultrasonic waves, the piezoelectric layer 13 vibrates to generate an electric signal, and the electric signal is output through the first electrode 12 and the second electrode 14.
PMUT devices need to have a large bandwidth in order to perform device functions, such as ultrasonic imaging. To achieve a larger bandwidth, one effective solution is to connect several sets of PMUT devices with different center frequencies in series to form a wideband array. Considering that the center frequency of the device is related to the diameter of the vibrating plate, i.e. to the diameter of the back cavity, devices with larger back cavity diameters generally have lower operating frequencies. Thus, a broadband array is typically implemented by connecting PMUT cells having different diameter back cavities in series, as shown in fig. 2, which is an equivalent schematic diagram of a broadband array of PMUT devices. The PMUT cells 21 to 24 with different back cavity diameters, i.e., different center frequencies, are connected in series by the interconnect structure 20, so that the operating bandwidth of the PMUT can cover the operating bandwidths of PMUT21 to PMUT 24.
In the prior art, to form a broadband array, back cavities with various diameters need to be formed, the process steps are complex, and how to reduce the process difficulty is a problem to be solved urgently at present.
Disclosure of Invention
Accordingly, the present application provides a semiconductor structure and a method for forming the same to reduce the process difficulty.
The application provides a semiconductor structure forming method, which comprises the following steps: providing a substrate, wherein the substrate comprises a supporting layer, a stopping layer positioned on the surface of one side of the supporting layer and a device layer positioned on the surface of the stopping layer; forming a patterned mask layer on the other side surface of the supporting layer, wherein a plurality of back cavity openings with different sizes are formed in the patterned mask layer; and carrying out first etching along each back cavity opening to etch the supporting layer to the corresponding position of each back cavity opening, and then stopping after the stopping layer is exposed, thereby forming a plurality of back cavities with different sizes in the supporting layer.
Optionally, the first etching includes: and after etching to the stop layer at the opening position of one back cavity, continuously utilizing the notch effect of the etching process to perform transverse etching until the back cavities at other positions are etched completely.
Optionally, at least one of the back cavities has a notch extending along a surface of the stop layer at a position near a bottom of the stop layer, the notch being caused by a notch effect etching of the etching process.
Optionally, a through hole opening is further formed in the patterned mask layer, and the size of the through hole opening is larger than that of the back cavity opening.
Optionally, the first etching further includes: etching the supporting layer to the stopping layer along the through hole opening; performing second etching along the through hole opening, and etching the stop layer to the device layer; and continuing the first etching, and simultaneously etching the supporting layer and the device layer to form a back cavity penetrating through the supporting layer and a through hole penetrating through the substrate.
Optionally, the method further includes: and the etching selectivity of the second etching to the stop layer is greater than that to the support layer.
Optionally, the first etching and the second etching both adopt a deep reactive ion etching process.
Optionally, the method further includes: and in the first etching process, performing end point detection and judging whether the etching reaches the stop layer.
Optionally, the endpoint detection method includes: vertically irradiating the bottom of the etched pattern by adopting parallel light to obtain a reflected light spot; and judging whether the etching reaches the stop layer or not according to the light spot pattern.
Optionally, the method further includes: forming a plurality of sensing units on the surface of the device layer; the back cavity opening position is opposite to the piezoelectric sensing unit position.
Optionally, an electrode layer connected to the sensing unit is further formed on the device layer, and the through hole penetrates through the substrate to expose the electrode layer; the forming method further includes: and filling a conductive material in the through hole to form a conductive column, wherein the conductive column is electrically connected with the electrode layer.
Optionally, the sensing unit comprises an ultrasonic piezoelectric sensing unit.
Embodiments of the present invention also provide a semiconductor structure, comprising: the substrate comprises a supporting layer, a stopping layer positioned on the surface of one side of the supporting layer and a device layer positioned on the surface of the stopping layer; and a plurality of back cavities with different sizes penetrating through the supporting layer to the stopping layer, wherein at least one back cavity is provided with a notch extending along the surface of the stopping layer at the position close to the bottom of the stopping layer, and the notch is formed by etching with a notch effect.
Optionally, the top openings of the plurality of differently sized cavities are differently sized.
Optionally, the back cavity further comprises a through hole penetrating through the substrate, and the size of the cross section of the through hole along the surface direction of the substrate is more than twice the size of the top opening of the back cavity.
Optionally, the device further comprises a plurality of sensing units located on the surface of the device layer, and the sensing units correspond to the back cavities one by one.
Optionally, an electrode layer connected to the sensing unit is further formed on the device layer; the through hole penetrates through the substrate to expose the electrode layer; and the through hole is filled with a conductive column, and the conductive column is electrically connected with the electrode layer.
Optionally, the sensing unit comprises an ultrasonic piezoelectric sensing unit.
According to the forming method of the semiconductor structure, the supporting layer is etched by utilizing the non-ideal effect of the etching process, such as the deep reactive ion etching process, specifically comprising the lag (lag) effect and the notch (notch) effect, and the back cavities and the through holes with different diameters are etched simultaneously in the synchronous etching process, so that the forming method of the semiconductor structure is simple in process steps and easy to realize.
Furthermore, in the etching process, an optical detection mode is used for detecting the etching end point, the area of an etched pattern and the limitation of a machine table are not limited, the method is easy to realize, and the detection accuracy is high.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of a prior art ultrasonic transducer;
FIG. 2 is a schematic diagram of a broadband array of prior art ultrasonic transducers;
fig. 3 to 9 are schematic structural diagrams illustrating a process of forming a semiconductor structure according to an embodiment of the present application.
Detailed Description
As described in the background art, if an ultrasonic piezoelectric transducer in the prior art needs to support a wide range of working bandwidths, back cavities with various diameters need to be formed, and at present, the back cavities with various diameters need to be formed by respective etching or matching with bonding, thinning and other process steps, which has the problems of complex process, high requirement on equipment and the like.
The inventors have further found that, since the control electrodes of the ultrasound transducer device are distributed on the upper surface of the device, i.e. in line with the ultrasound emission direction, such a configuration requires bonding of the control electrodes to the integrated circuit chip by means of wire bonding or the like, which is disadvantageous for the integration of the device with the back-end circuitry, especially for applications where the device is volume and parasitic parameters sensitive. The method for improving the problem is to vertically connect the ultrasonic piezoelectric transducer with the integrated circuit chip, lead out the electrode to the back of the supporting structure through the vertical interconnection structure, and vertically connect with the integrated circuit chip. The vertical interconnect structure typically requires separate processing, adding process steps and complexity.
In view of the above problems, the inventors propose a new semiconductor structure and a method for forming the same.
The technical solutions in the embodiments of the present application are clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. The following embodiments and their technical features may be combined with each other without conflict.
Fig. 3 to 9 are schematic structural diagrams illustrating a forming process of a semiconductor structure according to an embodiment of the invention.
Referring to fig. 3, a substrate 100 is provided, where the substrate 100 includes a support layer 101, a stop layer 102 on a side surface of the support layer 101, and a device layer 103 on a surface of the stop layer 102; a patterned mask layer 120 is formed on the other side surface of the support layer 101, and a plurality of back cavity openings with different sizes are formed in the patterned mask layer 120.
The support layer 101 material may include silicon (Si), such as crystalline Si, polycrystalline silicon, or amorphous Si. In some embodiments, the support layer 101 may comprise other semiconductor materials, such as germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP), among others. The supporting layer 101 is used for forming a back cavity, and the supporting layer 101 with a specific thickness can be selected according to the depth requirement of the back cavity to be formed. In some embodiments, the thickness of the support layer 101 ranges from 0.1mm to 0.5mm, and may be 0.3mm, for example.
The stop layer 102 and the support layer 101 are made of different materials, so that the two have different etching selectivity in the etching process, and the stop layer 102 can be used as an etching stop layer in the etching process of the support layer 101. The material of the stop layer 102 may be silicon nitride, silicon oxide, silicon oxynitride, or other materials commonly used in various semiconductor processes.
The material of the device layer 103 may also include semiconductor materials such as crystalline Si, polysilicon, amorphous Si, germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP), among others.
In this embodiment, the substrate 100 is an SOI substrate, the support layer 101 is a bulk silicon layer of the SOI substrate, the stop layer 102 is a buried oxide layer of the SOI substrate, and the device layer 103 is a thin silicon layer on a top layer of the SOI layer.
In order to enable the stop layer 102 to have a sufficient etching stop effect during the subsequent etching of the support layer 101, the thickness of the stop layer 102 cannot be too small. In some embodiments, the thickness of the support layer 101 is above 200 nm. In other embodiments, a person skilled in the art may reasonably set the thickness of the support layer 101 according to the etching process parameters to be used subsequently and the etching selection ratio between the support layer 101 and the stop layer 102.
The material of the patterned mask layer 120 includes at least one of mask materials such as silicon nitride, silicon oxide, silicon oxynitride, amorphous carbon, etc., and may have a single-layer or multi-layer structure. A plurality of back cavity openings of different sizes are formed in the patterned mask layer 120. In fig. 3 of this embodiment, three different sizes of back cavity openings 121c, 121b, and 121a are exemplified. The size of the back cavity opening may be defined as the area of the cross-section of the back cavity opening in the direction along the surface of the substrate 100. In this embodiment, the cross section of the back cavity openings 121c, 121b and 121a is circular, and the size can also be defined as the diameter of the back cavity openings, specifically, the sizes of the back cavity openings 121c, 121b and 121a increase in sequence. The position and size of the back cavity opening is used to define the position and size of a back cavity subsequently formed in the support layer 101. In other embodiments, the cross-section of the cavity back opening 121 a-121 c may also be oval, rectangular with rounded corners, polygonal, and other shapes.
In other embodiments, the number, size and location of the back cavity openings may be set as desired.
In this embodiment, a through hole opening 122 is further formed in the patterned mask layer 120, and the size of the through hole opening 122 is larger than the size of all the back cavity openings. The through-hole openings 122 are circular in cross-section and have a diameter greater than the diameter of the respective back cavity opening. Preferably, the size of the through hole opening 122 is more than 2 times of the size of the maximum size of the back cavity opening.
In this embodiment, forming a plurality of sensing units 106 on the surface of the device layer 103; the back cavity openings 121a to 121c are opposite to the sensing units, and a back cavity formed by etching the supporting layer 101 along each back cavity opening 121a to 121c is located below the corresponding sensing unit 106. In this embodiment, the sensing unit 106 is a piezoelectric transducing sensing unit. In other embodiments, the sensing unit 106 may also be other types of sensing units that need to sense by deformation, such as a magnetic or electric force transducer sensing unit.
In some embodiments, the size of each sensing cell 106 may be related to the size of the corresponding back cavity opening, with the larger the back cavity opening size, the larger the size of the sensing cell 106. In other embodiments, the sensing units 106 are all the same size and shape.
In this embodiment, an isolation layer 104 and an electrode layer 105 formed on a surface of the isolation layer 104 are further formed between the sensing unit 106 and the substrate 100, and the sensing unit 106 includes a piezoelectric material layer formed on a surface of the sensing unit 106. At least a part of the sensing units 106 can be connected in series, for example, in rows and columns, by properly designing the specific layout of the electrode layer 105. In other embodiments, the sensing units 106 may be independent of each other, and the electrode layer 105 between each sensing unit 106 is also independent of each other.
In fig. 3, the sensing unit 106 is only a simple illustration, and a person skilled in the art can form a sensing unit 106 with a reasonable structure according to the specific structure and design requirements of the sensing unit 106.
The sensing unit 106 may be formed after the patterned mask layer 120 is formed; alternatively, the sensing unit 106 may be formed first, and then the patterned mask layer 120 may be formed.
Referring to fig. 4, a first etching is performed along each of the back cavity openings to etch the support layer 101.
The first etching is performed with the patterned mask layer 120 as an etching mask. Preferably, the first etching is a dry etching process, and preferably, a Deep Reactive Ion Etching (DRIE) process may be selected, which has a high aspect ratio etching capability, and performs physical etching and chemical etching on the support layer 101 at the same time. The first etching process comprises two sub-cycle processes of etching and passivating. During etching, an etching gas, such as SF, is introduced into the reaction chamber6Performing physical and chemical etching on the supporting layer 101 to form an etching pattern; during passivation, a reactive gas, such as C, is introduced into the reaction chamber4F8And forming a polymer film through chemical reaction to protect the side wall of the etched pattern and reduce the transverse etching, thereby realizing the high aspect ratio etching and keeping the side wall of the etched pattern relatively vertical.
Further, different from the etching process in the general semiconductor process, which is to avoid some adverse effects that may cause etching non-uniformity and affect etching directionality as much as possible, the first etching of the present application needs to utilize an etching lag (lag) effect and an etching notching (notching) effect in the etching process to finally form back cavities of different sizes, and therefore, special consideration needs to be given to process parameters adopted in the first etching process.
In some embodiments, in the etching process of the first etching, the power range of the coil is 600W-800W, so as to ensure that etching plasma can be effectively generated; the power of the flat plate is 15W-30W, so that the lateral etching caused by the etching notch effect is ensured to be carried out at a controllable speed; pressure of 30-50 mtorr, etching gas such as SF6The flow rate of the etching solution is 100sccm to 200sccm, so that the longitudinal etching speed is controllable; the temperature is 18-40 ℃, the higher the temperature is, the higher the etching speed is, the controllable etching speed needs to be ensured, and the mask selection ratio is not obviously changed; the single execution time of the etching process is 5-12 s, the short step time can cause abnormal plasma starting, and the long step time can increase the roughness of the side wall of the back cavity. Etching ofIn the process, F2, Cl2, Br2 and I2 can be selected as simple substances or compound gases containing at least one element of F, Cl, Br and I, such as CF4、CHF3Or Cl2、Br2Etc. may be used as the etchant for silicon.
In the passivation process of the first etching, the power range of the coil is 600W-800W, so that reactive plasma can be effectively generated; the power of the flat plate is 0, so that the bombardment effect is avoided; the pressure range is 10-33 mtorr, the flow of the reaction gas is 50-100 sccm, the deposition effect of the passivation layer formed on the side wall in the back cavity etching process is uniform, and the deposition speed is controllable; the temperature range is 18-40 ℃, the improvement of the temperature is beneficial to improving the uniformity of deposition, but the deposited passivation layer is not decomposed at high temperature; the single execution time ranges from 5s to 10s, the plasma starting abnormality can be caused by too short step time, and the roughness of the side wall and the bottom surface of the back cavity can be increased by too long step time.
In one embodiment of the invention, during the etching process of the first etching, the power range of the coil is 600W, the power of the flat plate is 20W, the pressure is 37mtorr, and etching gas SF6The flow rate of (1) is 100-200 sccm, the temperature is 25 ℃, and the single time is 12 s; in the passivation process, the power range of the coil is 600W, the power of the flat plate is 0, the pressure intensity is 19mtorr, and the reaction gas C4F8At a flow rate of 85sccm and a temperature of 25 ℃ for a single time of 7 s.
In other embodiments, the process parameters may be adjusted reasonably based on the above considerations and goals of parameter settings according to the equipment of the particular machine.
The dry etching process, especially the high aspect ratio etching process, has an etching lag (lag) effect, because as the depth of the etching groove or hole increases, the plasma participating in the etching process is more and more difficult to contact the etching surface during the transmission process, the by-products generated during the etching process are more and more difficult to come out, and the exchange rate of the etching gas and the by-product gas is slower in the etching pattern with smaller size, which results in that the etching rate is larger and larger when the size of the opening of the mask pattern is larger under the same etching time and condition. In this embodiment, the opening sizes of the via opening 122 and the back cavity openings 121a, 121b, and 121c are sequentially decreased, and the etching rate for the support layer 101 at the corresponding positions is also sequentially decreased, so that the support layer 101 etched along the via opening 122 with the largest size reaches the stop layer 102 first.
In the first etching process, periodic endpoint detection can be performed, and whether the pattern is etched to the stop layer or not can be detected. In this embodiment, optical detection is used in conjunction with optical interference and image recognition techniques to perform endpoint detection. Specifically, parallel light is adopted to vertically irradiate the bottom of an etched pattern, and reflection light spots are obtained; and judging whether the etching reaches the stop layer 102 or not according to the light spot pattern. Since the etching end point is the stop layer 102 with a specific thickness, in this embodiment, a silicon oxide layer, the material of the stop layer can generate an optical interference phenomenon under the irradiation of parallel light, so as to generate reflected light with a specific wavelength; for the underetched state, the silicon oxide layer in the back cavity and the silicon structure of the supporting layer 101 left thereon can generate annular interference patterns under the irradiation of light, the morning reading of the underetched state is different, and the number of the rings is also different; for the over-etching state, the brightness and the size of the interference pattern can be obviously changed, and through the ex-situ detection mode, the stage of the back cavity etching process is judged by identifying the interference pattern of the reflection light spot, so that the nondestructive detection of the etching end point is realized. And the detection accuracy of the optical detection mode is not limited by the etching size area.
Please refer to fig. 5a, which is a schematic diagram of an interference pattern obtained under different etching states. Under the etching state, the reflection light spots form multiple circular ring patterns, in the critical state of completely exposing the stop layer, the reflection light spots form single circular ring patterns, and in the over-etching state, the outer circular ring patterns are not formed, and the brightness is obviously increased. In fig. 5a, which is only an illustration, the actual number of circles and the actual size of the back cavity and the etching degree are related, and the closer the etching is to the stop layer, the higher the brightness of the reflected light spot is, and the fewer the number of circles is. The stop layer 102 is made of a different material and the interference pattern of the reflected light spot is different in different cases.
Referring to FIG. 5b, a microscope photograph of an interference pattern according to an embodiment of the invention is shown.
The first behavior is a picture taken by a microscope, the second behavior corresponds to a black-and-white image of the picture, and from left to right, the first behavior is an underetched state, a critical etched state and an overetched state, and the first behavior corresponds to patterns of multiple circular rings, single circular rings and no circular rings.
In other embodiments, the etching endpoint can be detected by detecting byproducts and other means, but under the condition of small etching area ratio, the detection effect is affected due to the low concentration of the byproducts, and the detection effect is limited by the machine and the etching area ratio to a certain extent.
Referring to fig. 6, after the supporting layer 101 is etched to the stop layer 102 along the through hole opening 122, a second etching is performed along the through hole opening 122 to etch the stop layer 102 to the device layer 103.
In the first etching process, after the etching pattern at the through hole opening 122 is judged to be etched to the stop layer 102 through the end point detection, the etching parameters are switched to perform the second etching. The etching selectivity of the second etching to the stop layer 102 is greater than the etching selectivity to the support layer 101, so that the etching rate to the stop layer 102 is greater than the etching rate to the support layer 101 in the second etching process. Since the size of the via opening 122 is larger than the size of the back cavity opening, the etch pattern of the back cavity has not yet reached the end of the etch when the via is etched to the stop layer 102.
The second etching also adopts a dry etching process, for example, a Deep Reactive Ion Etching (DRIE) process is adopted, the reaction gas is gas containing fluorine (F) base, the flow is 30-50sccm, the pressure is 10-30mtorr, and the controllable etching speed is ensured; the power is 100-800W, and the effective generation of plasma is required to be ensured; the reactant gas may also include other fluorine (F) -group containing gases, such as CF4HF, etc.
In one embodiment, the reactant gas is CHF3The flow rate is 30sccm, the process pressure is 1.3Pa, and the power is 90W.
In other embodiments, appropriate etch parameters may be set depending on the specific material of the stop layer 102.
In the process of etching the stop layer 102, the support layer 101 at the bottom of the back cavity is also etched at the same time, and the second etching is stopped after the pattern at the through hole opening 122 is etched to the device layer 103. The etching end point position can be detected by the above optical detection method.
Referring to fig. 7, the first etching is continued while the support layer 101 and the device layer 103 are etched.
After the stop layer 102 at the via pattern is etched through, the first etching is continued, and the etching is continued along the back cavity opening and the via opening 122, including continuing to etch the support layer 101 along the back cavity openings 121a to 121c, and etching the device layer 103 along the via opening 122.
In the etching process, the bottom of the back cavity at the back cavity opening 121a first reaches the stop layer 102, and at this time, the first etching is continued; while the back cavity depth at other positions continues to increase, lateral etching is generated at the bottom of the back cavity 201a corresponding to the back cavity opening 121a due to an etching notch effect; then the bottom of the back cavity 122b at the back cavity opening 121b also reaches the stop layer 102, and lateral etching is generated under the effect of the notch effect; until the smallest sized back cavity 122c is etched to the surface of the stop layer 102. Lateral etching due to the notch effect causes the back cavity to have a notch extending along the surface of the stop layer 102 near the bottom of the stop layer. The larger the opening size of the back cavity is, the larger the lateral etching degree of the bottom of the formed back cavity is, and the larger the lateral size of the bottom of the finally formed back cavity is.
The notch effect occurs because the etching plasma builds up a local positive field at the insulating surface of the stop layer 102. This local positive field deflects the incident ions towards both ends, causing lateral etching of the sidewalls of the support layer 101 at the interface. Due to the insulating nature of the stop layer 102, the accumulation of ionic charges is inevitable, as is the notching phenomenon. The switching frequency of the etching process and the passivation process and the panel power can be increased, and the duration of the turn-off of the panel bias voltage in the passivation process can be reduced, so that the dissipation of charges accumulated near the stop layer 102 can be reduced, and the notch effect is more remarkable.
Since the patterned mask layer 120 has back cavity openings with different sizes, the supporting layer 101 is etched along the back cavity openings with different sizes until the stopping layer 102 is exposed in sequence, and then the etching is stopped, so that a plurality of back cavities with different sizes can be formed in the supporting layer 101. Due to the different etching degrees, the diameter of the back cavity near the bottom of the stop layer 102 may be smaller than the size of the corresponding back cavity opening 121c, such as the back cavity 201c, or equal to the size of the back cavity opening 121b, such as the back cavity 201 b; and may be larger than the size of the back cavity opening, such as back cavity 201 a.
Meanwhile, in the process of etching the back cavity, the device layer 103 is further continuously etched until a through hole 202 penetrating the substrate 100 is formed, and the first etching is stopped. In this embodiment, since the through hole 123 is used to form a conductive pillar connected to the electrode layer 105, the through hole 202 also penetrates through the insulating layer 104 to expose the bottom electrode layer 105.
By the method, the sensing unit arrays with different back cavity sizes can be formed. When the sensing unit is a piezoelectric sensing unit, the back cavities have different sizes, so that the working frequencies of ultrasonic energy conversion are different. By forming different sized back cavities, a broadband array ultrasonic transducer can be formed.
Referring to fig. 8, a conductive material is filled in the via 202 to form a conductive pillar 203.
After the mask layer 120 is removed, the conductive material is filled.
The conductive material may include copper, tungsten, aluminum, polysilicon, TiN, TaN, etc. In some embodiments, a diffusion barrier layer, such as a TiN layer, a TaN layer, or the like, may also be formed between the conductive pillars 203 and the via sidewalls. The electrode layer 105 at the bottom of the sensing unit 106 is electrically connected to the conductive pillar 203.
In order to avoid filling the conductive cavities with a conductive material during the process of forming the conductive pillars 203, a protective layer may be filled in each of the back cavities first, and then the protective layer may be removed after forming the conductive pillars 203.
Referring to fig. 9, a semiconductor structure according to another embodiment of the invention is shown.
In this embodiment, while the back cavities 740 (only one back cavity is taken as an illustration) are formed in the support layer 101 of the substrate by the above method, first and second through holes penetrating through the substrate are formed, and first conductive pillars 731 and second conductive pillars 732 are formed in the first through holes and the second through holes.
In this embodiment, a sensing unit 106, a bottom electrode layer 712 connected to the sensing unit 106, and a top electrode layer 711 connected to the sensing unit 106 are formed on the device layer 103 and electrically connected to the upper and lower surfaces of the sensing unit 106, respectively. And an insulating layer 713 is further formed between the top electrode layer 711 and the bottom electrode layer 712 to form electrical isolation.
The first conductive pillar 731 is electrically connected to the bottom electrode layer 712, the second conductive pillar 732 is electrically connected to the top electrode layer 711, and the bottom electrode layer 712 and the top electrode layer 711 are electrically led out to the other side surface of the supporting layer 101 through the first conductive pillar 731 and the second conductive pillar 732, respectively.
The semiconductor structure is stacked and bonded on a substrate 720, and the substrate 720 may be a PCB, an Asic chip, or the like. The contact points 721 on the substrate 720 are electrically connected to the first conductive pillars 731 and the second conductive pillars 721 through soldering or metal bonding.
In the above embodiment, the supporting layer is etched by using an etching process, for example, the non-ideal effect of the deep reactive ion etching process, specifically including the hysteresis (lag) effect and the notch (notch) effect, so that etching of the back cavities and the through holes with different diameters is simultaneously realized in the synchronous etching process, and the process is simple in steps and easy to implement.
Embodiments of the present application also provide a semiconductor structure formed by the above method.
Fig. 8 is a schematic structural diagram of a semiconductor structure according to an embodiment of the invention.
The semiconductor structure includes: a substrate 100, wherein the substrate 100 comprises a support layer 101, a stop layer 102 positioned on one side surface of the support layer 101, and a device layer 103 positioned on the surface of the stop layer 102; a plurality of back cavities with different sizes penetrating through the support layer 101 to the stop layer 102, at least one back cavity having a notch extending along the surface of the stop layer at a position near the bottom of the stop layer, the notch being caused by etching by a notch effect of the etching.
In this embodiment, back cavities 201c, 201b, and 201a having different sizes are formed in the substrate 100. Wherein the back cavity 201a has a laterally extending notch near the bottom of the stop layer 102. The top openings of the various back cavities all have different sizes.
In this embodiment, the semiconductor structure further includes a through hole penetrating through the substrate, and a cross-sectional dimension of the through hole in a substrate surface direction is more than twice a dimension of the top opening of the back cavity. The via holes are filled with conductive pillars 203.
In this embodiment, the semiconductor structure further includes a plurality of sensing units 106 located on the surface of the device layer, and the sensing units 106 are opposite to the back cavities. Specifically, an isolation layer 104 is formed on the surface of the device layer 103, the sensing layer 106 is located on the isolation layer 104, an electrode layer 105 is further formed at the bottom of the sensing layer 106, and the electrode layer 105 can realize series connection or parallel connection among a plurality of sensing units.
The conductive post 203 penetrates the substrate 100 and the isolation layer 104, and is electrically connected to the electrode layer 105.
In some embodiments, the sensing unit 106 comprises an ultrasonic piezoelectric sensing unit.
The above-mentioned embodiments are only examples of the present application, and not intended to limit the scope of the present application, and all equivalent structures or equivalent flow transformations made by the contents of the specification and the drawings, such as the combination of technical features between the embodiments and the direct or indirect application to other related technical fields, are also included in the scope of the present application.

Claims (16)

1. A method for forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a supporting layer, a stopping layer positioned on the surface of one side of the supporting layer and a device layer positioned on the surface of the stopping layer;
forming a patterned mask layer on the other side surface of the supporting layer, wherein a plurality of back cavity openings with different sizes are formed in the patterned mask layer;
and carrying out first etching along each back cavity opening to etch the supporting layer to the corresponding position of each back cavity opening, and then stopping after the stopping layer is exposed, thereby forming a plurality of back cavities with different sizes in the supporting layer.
2. The forming method according to claim 1, wherein the first etching includes: and after etching to the stop layer at the opening position of one back cavity, continuously utilizing the notch effect of the etching process to perform transverse etching until the back cavities at other positions are etched completely.
3. The method of claim 2, wherein at least one of the cavities has a notch extending along a surface of the stop layer at a location near a bottom of the stop layer, the notch resulting from a notch effect etch of the etch process.
4. The forming method according to claim 1, wherein a via opening is further formed in the patterned mask layer, and the via opening has a size larger than that of the cavity-back opening; the first etching further includes: etching the supporting layer to the stopping layer along the through hole opening; performing second etching along the through hole opening, and etching the stop layer to the device layer; and continuing the first etching, and simultaneously etching the supporting layer and the device layer to form a back cavity penetrating through the supporting layer and a through hole penetrating through the substrate.
5. The method of forming as claimed in claim 4, further comprising: the etching selectivity of the second etching to the stop layer is larger than that to the support layer; and/or the first etching and the second etching both adopt a deep reactive ion etching process.
6. The forming method according to claim 1 or 4, further comprising: and in the first etching process, performing end point detection and judging whether the etching reaches the stop layer.
7. The forming method of claim 6, wherein the method of endpoint detection comprises: vertically irradiating the bottom of the etched pattern by adopting parallel light to obtain a reflected light spot; and judging whether the etching reaches the stop layer or not according to the light spot pattern.
8. The method of forming as claimed in claim 4, further comprising: forming a plurality of sensing units on the surface of the device layer; the back cavity opening position is opposite to the piezoelectric sensing unit position.
9. The method as claimed in claim 8, wherein an electrode layer connected to the sensing unit is further formed on the device layer, and the through hole penetrates through the substrate to expose the electrode layer; the forming method further includes: and filling a conductive material in the through hole to form a conductive column, wherein the conductive column is electrically connected with the electrode layer.
10. The method of forming as defined in claim 8, wherein the sensing unit comprises an ultrasonic piezoelectric sensing unit.
11. A semiconductor structure, comprising:
the substrate comprises a supporting layer, a stopping layer positioned on the surface of one side of the supporting layer and a device layer positioned on the surface of the stopping layer;
and a plurality of back cavities with different sizes penetrating through the supporting layer to the stopping layer, wherein at least one back cavity is provided with a notch extending along the surface of the stopping layer at the position close to the bottom of the stopping layer, and the notch is formed by etching with a notch effect.
12. The semiconductor structure of claim 11, wherein the top openings of the plurality of differently sized cavities are differently sized.
13. The semiconductor structure of claim 12, further comprising: and the through hole penetrates through the substrate, and the size of the cross section of the through hole along the surface direction of the substrate is more than twice of the size of the top opening of the back cavity.
14. The semiconductor structure of claim 12, further comprising: and the sensing units are positioned on the surface of the device layer and correspond to the back cavities one by one.
15. The semiconductor structure according to claim 14, wherein an electrode layer connected to the sensing unit is further formed on the device layer; the through hole penetrates through the substrate to expose the electrode layer; and the through hole is filled with a conductive column, and the conductive column is electrically connected with the electrode layer.
16. The semiconductor structure of claim 14, wherein the sensing unit comprises an ultrasonic piezoelectric sensing unit.
CN202111212038.1A 2021-10-18 2021-10-18 Semiconductor structure and forming method thereof Pending CN113998664A (en)

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