JP2018098591A - Capacitive transducer and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a capacitive transducer capable of restraining deterioration in transmission efficiency and reception sensitivity by restraining deterioration in membrane utilization efficiency, and a method of manufacturing the capacitive transducer.SOLUTION: A capacitive transducer includes one or more elements 104 each having a cell 101 including a structure supporting a vibration film at least including a second electrode 205 provided facing a first electrode 210 with an air gap 203 in between. The cell 101 of an element 104 is electrically connected with an adjacent cell with wiring 102 linked to the second electrode 205. The shape of the second electrode 205 in plan view viewed from above is nearly the same as the shape of the air gap 203.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a capacitive transducer used as an ultrasonic transducer, a manufacturing method thereof, and the like.

  In recent years, with the development of microfabrication technology, various micromechanical elements processed with micrometer order accuracy have been realized. Development of a capacitive transducer (for example, CMUT: Capacitive-Micromachined-Ultrasonic-Transducer) has been actively performed using such a technique. The CMUT has a configuration in which a pair of electrodes are provided in layers facing each other with a gap (cavity) interposed therebetween. It is an ultrasonic device that transmits and receives ultrasonic waves by vibrating the membrane-like thin film, and has excellent broadband characteristics in liquid and air. For this reason, it is possible to perform measurement with higher resolution than an ultrasonic device made of a piezoelectric element that has been used in the past.

  In general, the CMUT is driven in a state in which a plurality of cell structures on the order of micrometers are assembled. In that case, in order to obtain the above excellent characteristics, it is required that the diameter and thickness of the membrane and the gap distance (void thickness) are substantially uniform in a plurality of cell structures. As a manufacturing method for realizing it, a method of forming a void under the membrane by providing a sacrificial layer in advance in a region constituting a void portion of the cell, forming a membrane structure of the cell, and then removing the sacrifice layer (See Patent Document 1).

JP 2008-85246 A

  However, when the electrode area on the upper layer of the membrane when the device is viewed from above is located on the inner side of the gap area (that is, the electrode area is smaller than the gap area), the use efficiency of the membrane decreases and the ultrasonic wave The transmission efficiency and reception sensitivity of the device may decrease. Further, when a step is formed between the electrode included in the cell membrane and the wiring that electrically connects the cells, step coverage may be deteriorated. As a result, wiring resistance increases, and transmission efficiency and reception sensitivity may decrease.

  In view of the above problems, a capacitive transducer according to an aspect of the present invention includes a cell including a structure in which a vibration film including at least a second electrode provided with a gap between the first electrode and a first electrode is supported. 1 or more element, and the cell of the element is a capacitive transducer that is electrically connected to an adjacent cell by a wiring connected to the second electrode, and is seen in plan view from above The shape of the second electrode substantially matches the shape of the gap.

  In addition, in view of the above problems, the capacitive transducer manufacturing method according to another aspect of the present invention supports a vibrating membrane including at least a second electrode provided with a gap between the first electrode and the first electrode. A method for manufacturing a capacitive transducer including one or more elements each having a cell including a structure. And at least a step of forming a sacrificial layer on the first electrode, a step of forming a first insulating layer on the sacrificial layer, and the second electrode on the first insulating layer. A step of forming, a step of forming a second insulating layer on the second electrode, a step of removing the sacrificial layer to form the gap, and a third insulating layer on the second insulating layer And a step of sealing the opening used for removing the sacrificial layer, and using the mask shape for forming the second electrode in the step of removing the sacrificial layer and forming the gap Then, etching is performed up to a position including the sacrificial layer located in the lower region of the second electrode.

  According to the present invention, an electrode can be formed in almost all of the membrane region corresponding to the void region when the cell is viewed in plan view from above. It is possible to suppress a decrease in transmission efficiency and reception sensitivity.

The top view which shows the structure of the capacitive transducer which concerns on embodiment of this invention. FIG. 3 is a cross-sectional view taken along the line AB, showing the configuration of the capacitive transducer of FIG. CD sectional drawing which shows the structure of the capacitive transducer of FIG. Sectional drawing which shows the process of the manufacturing method of the capacitive transducer of FIG. Sectional drawing which shows the process of the manufacturing method of the capacitive transducer of FIG. CD sectional drawing which shows the connection with the power supply of the capacitive transducer of FIG. Sectional drawing which shows the detail of the manufacturing process of an electrostatic capacitance type transducer. Sectional drawing which shows the detail of the manufacturing process of an electrostatic capacitance type transducer. The figure which shows the probe containing the capacitive transducer which concerns on embodiment of this invention. The block diagram of the information acquisition apparatus containing a probe. Sectional drawing which shows the undercut in the manufacturing method of an electrostatic capacitance type transducer. FIG. 6 is a cross-sectional view of the capacitive transducer A-B having an undercut. CD sectional drawing of a capacitive transducer with an undercut. The top view of the structure of the capacitive transducer which concerns on other embodiment of this invention.

  According to one aspect of the present invention, in the capacitive transducer, electrodes are formed in substantially all of the membrane region corresponding to the void region when the cell is viewed from above. On the other hand, according to the other aspect of this invention, the following manufacturing method is provided. That is, in this manufacturing method, after forming the second insulating layer on the second electrode formed on the first insulating layer formed on the sacrificial layer on the first electrode, the sacrificial layer is removed. To form voids. Then, when forming the gap, the mask shape for forming the second electrode is commonly used, and etching is performed to a position including the sacrificial layer located in the lower region of the second electrode. The capacitive transducer having the above-described configuration can be manufactured by this manufacturing method.

[Embodiment 1]
An embodiment for carrying out the present invention will be described with reference to the drawings. FIG. 1 is a top view illustrating the capacitive transducer according to the first embodiment. The electrostatic capacity type transducer is formed by collecting one or more elements 104 each having a cell 101 on which a vibrating membrane (membrane) including one electrode of a pair provided with a gap or gap is supported so as to vibrate. ing. The cell 101 is electrically connected to the adjacent cell 101 by a wiring 102 and is electrically connected to a lead-out wiring region 105 that collects signals of each element 104 including the plurality of cells 101. At the end of the lead-out wiring area 105, there is an opening 106 used for wiring to an external substrate. The opening 106 is an area where the wiring area 105 is exposed by removing later-described layers 206 and 207 formed on the wiring area 105. Etching holes 103 used for removing a sacrificial layer, which will be described later, may be arranged 1: 1 for each cell 101 as shown in FIG. 1, or arranged so as to be one for a plurality of cells. It doesn't matter.

  Although only one element 104 is shown in FIG. 1, the number of elements may be one or more, and any number is possible. Any number of cells 101 may be included in the element 104. The arrangement of the cells 101 may be any arrangement such as a lattice arrangement or a staggered arrangement. In the present embodiment, the shape of the cell 101 viewed from above when viewed from above is a circle, and the shape of the vibrating membrane portion is a circle, but it may be a square, a rectangle, a polygon, or the like.

  The layer structure of one cell 101 will be described with reference to FIGS. 2 is a cross-sectional view of the cell 101 taken along the line AB in FIG. 1, and FIG. 3 is a cross-sectional view of the cell 101 taken along the line CD in FIG. The cell 101 includes a first electrode 201 (lower electrode), an insulating layer 202, a void or void layer 203, an insulating layer 204 (first insulating layer), a second electrode 205 (upper electrode), and an insulating layer 206 (first electrode). A second insulating layer), an insulating layer 207 (third insulating layer), and an etching hole 208. Each layer constituting the cell 101 will be described in detail below.

  The lower electrode 201 is disposed on a silicon substrate (not shown) on which a thermal oxide film is formed, and is used for applying a bias voltage. The membrane part including the upper electrode 205 receives electrostatic attraction from the lower electrode 201 by this bias voltage. The lower electrode 201 can be selected from W, Ti, Al, or an alloy of a material whose main component is any one of these. Since the lower electrode 201 in the cell is formed by laminating a plurality of films thereon, the base film has high flatness, sufficient heat resistance in the subsequent process, and low electrical resistance. Is required. Other metals can be used as long as these conditions are satisfied. In order to reduce unnecessary parasitic capacitance between the lower electrode 201 and the upper electrode 205, it is preferable to reduce the formation area of the lower electrode in a region other than the region where the element 104 exists.

  The insulating layer 202 is disposed on the lower electrode 201. This layer 202 is typically formed of silicon oxide or silicon nitride. The insulating layer 202 is preferably made of a material different from that of the upper insulating layer 204 when manufacturing a capacitive transducer. The reason will be described later. If the insulating layer 204 is formed of a SiN compound, the insulating layer 202 is formed of silicon oxide. However, the insulating layer 202 may be omitted as long as a manufacturing margin can be ensured and further insulation between the upper electrode 205 and the lower electrode 201 can be ensured. The void 203 under the membrane is disposed in the upper layer of the insulating layer 202. The void 203 under the membrane is formed by removing the sacrificial layer 209 after forming the membrane structure as will be described later.

  The insulating layer 204 constituting the membrane is disposed on the upper layer of the gap layer 203. As a constituent material of the membrane and a material positioned between the upper electrode 205 and the lower electrode 201, a silicon oxide, a silicon nitride, or a combination of these is generally used, and the reason will be described below.

  First, the membrane constituting the membrane structure can be adjusted to a weak tensile stress as a whole, the membrane can be prevented from warping, and the void structure can be maintained. Next, it is because the insulating property of the material located between the upper electrode 205 and the lower electrode 201 can be increased, charge injection into the film during driving can be suppressed, and charging of the membrane can be suppressed. Since device characteristics drift when charging occurs, it is required to suppress charging in order to prevent it. This is because the surface of each layer constituting the membrane can be formed flat. The thickness (height) of the void under the membrane is on the order of nanometers, and it is necessary to ensure the desired void and not hinder the movement of the membrane. Next, silicon oxide and silicon nitride are generally widely used materials, and can be conformally and densely formed, and have high workability. Next, as a material constituting the membrane movable part, the density can be reduced and the Young's modulus can be increased. This contributes to the realization of CMUT broadband. Considering these comprehensively, the membrane material and configuration are determined, but it is preferable that the membrane is mainly composed of silicon nitride.

  Subsequently, the second electrode 205 (upper electrode) is disposed in the upper layer of the insulating layer 204. The second electrode 205 also serves as an upper electrode of the cell 101, a wiring 102 that electrically connects adjacent cells, and a signal input / output wiring (arranged in the lead-out wiring region 105) of the element 104. For the second electrode 205, W, Ti, Al, Au, or an alloy of a material mainly containing any one of them can be selected. Since a plurality of films are stacked also over the second electrode 205, high flatness, sufficient heat resistance in a subsequent process, and low electrical resistance are required. Other metals can be used as long as these conditions are satisfied.

  The insulating layer 206 is disposed on the second electrode 205. It plays the role of forming the opening (103, 208) when etching the sacrificial layer 209, taking the membrane structure. Generally, a silicon nitride film is used, but other materials can be used as long as they satisfy the design characteristics. The insulating layer 207 is disposed on the insulating layer 206. It is necessary for the film thickness to satisfy a condition that allows the etching hole to be sealed and the vibration characteristics of the membrane. In general, a silicon nitride film is used, but other materials can be used as long as they satisfy these characteristics.

  The feature of the cell 101 in the present embodiment is that the shapes of the upper electrode 205, the insulating layer 204, and the gap 203 are substantially the same as viewed from above the cell. That is, in all directions, the edges of these layers coincide with each other or are drawn in parallel with a minute equidistant distance (see FIG. 6D described later). The reason why the upper electrode 205 is desired to be disposed in substantially the entire region of the gap 203 will be described.

  The membrane part of this embodiment is mainly composed of an insulating layer 204, an upper electrode 205, an insulating layer 206, and an insulating layer 207. The generation of ultrasonic waves by the CMUT is realized by deforming the membrane at a speed having a frequency in the MHz band by electrostatic attraction, and giving displacement to the medium in contact with the membrane. In order to generate a larger ultrasonic wave, it is necessary to greatly displace the membrane. For this purpose, it is preferable to generate an electrostatic attractive force in the entire region of the membrane and apply the force to the membrane. Therefore, it is preferable to arrange the upper electrode in substantially the entire region of the membrane.

  The ultrasonic wave reception sensitivity is proportional to the time change (current) of the charge generated by the change in the capacitance of the CMUT. For this reason, it is preferable that electrodes be arranged in the entire region of the membrane, since charges generated in the region where the membrane is displaced can be used without any loss, and reception sensitivity can be increased.

  In the present embodiment, the diameter of the CMUT cell 101 may be about 50 μm to 100 μm at the maximum, but in order to maintain the broadband property that is a characteristic of the CMUT, a range of about 5 μm to 40 μm is often selected. In the prior art, the shape of the sacrificial layer 209 and the shape of the upper electrode 205 are manufactured by separate alignment processes. In that case, it is necessary to design the shape of the upper electrode 205 to be smaller than the shape of the sacrificial layer 209 by allowing for various errors. Therefore, the area of the upper electrode 205 can be 80% to 90% with respect to the area of the gap layer 203, and in some cases only about 70%. According to the present embodiment, the upper electrode 205 can be disposed up to approximately 100% of the area of the membrane, which contributes to improvement in transmission / reception efficiency.

  Next, each process of the manufacturing method of the capacitive transducer according to this embodiment will be described with reference to the drawings. 4A and 4B show the progress of the manufacturing process at the cross-sectional position of the cell 101 in FIG. Here, the characteristics of the manufacturing method in the present embodiment will be mainly described. FIG. 4A shows a cross section in which a lower electrode 201, an insulating layer 202, a sacrificial layer 209, an insulating layer 204, and an upper electrode 205 are formed on a semiconductor substrate (not shown) on which a thermal oxide film is formed. Indicates. In general, physical vapor deposition, physical sputtering film formation, or CVD (mainly PE-CVD (plasma-enhanced chemical vapor deposition)) is used as a method for forming each layer. Any film forming means may be used as long as items such as film physical properties, film formation unevenness, and flatness fall within the design specifications.

  FIG. 4B shows a process in which a photoresist pattern 501 is disposed in order to etch the shape of the second electrode 205. In the present embodiment, using the photoresist pattern 501 for processing the second electrode 205, the insulating layer 204 and the sacrificial layer 209 located at the lower layer are processed at once. By doing so, it is possible to transfer the shape of the second electrode 205 defined by the shape of the photoresist pattern 501 to the insulating layer 204 and the sacrificial layer 209 while substantially maintaining the shape. Depending on the total thickness of the upper electrode 205, the insulating layer 204, and the sacrificial layer 209, if all the layers are processed by plasma etching, a general positive resist is about 3 μm to 4 μm in view of the etching selectivity. The thickness of is required.

  FIG. 4C is a cross-sectional view of the step of etching the second electrode 205 using the photoresist pattern 501. Plasma etching using a chlorine-based gas is generally used to process the electrode material. However, wet etching may be used as long as processing accuracy is mainly acceptable. Of course, depending on the electrode material, etching by only physical sputtering such as Ar gas is possible.

FIG. 4D is a cross-sectional view of a process in which the insulating layer 204 is continuously etched using the photoresist pattern 501. By processing the photoresist pattern 501 as it is, it is possible to form substantially the same shape as the second electrode 205 (a shape that substantially overlaps in plan view as viewed from above). When a silicon nitride film is selected as the insulating layer 204, etching is performed by switching to a fluorine-based gas (such as SF ₆ or CF ₄ ). In the etching of the second electrode 205, when etching is performed with a chlorine-based gas, it is preferable to perform the etching continuously without releasing the substrate to the atmosphere in order to prevent the corrosion of the second electrode 205. In that case, an environment where chlorine-based gas and fluorine-based gas can be used in the same etching apparatus is required.

  FIG. 4E is a cross-sectional view of a process in which the sacrificial layer 209 is continuously etched using the photoresist pattern 501. In this process as well, the photoresist pattern 501 is processed as it is, so that substantially the same shape as the second electrode 205 can be formed. If a silicon-based material (a-Si, p-Si) is used as the sacrificial layer 209, plasma etching can be performed using a chlorine-based or fluorine-based gas. When etching with a chlorine-based gas, an etching selectivity can be ensured by forming a silicon oxide film (insulating layer 202) as a base for the sacrificial layer 209. Therefore, since the insulating layer 202 functions as an etching stop layer, it is preferable from the viewpoint of manufacturing. Needless to say, the insulating layer 202 below the sacrificial layer 209 may be omitted as long as the etching selectivity can be secured.

  FIG. 4B is a cross-sectional view in which the structure manufactured in the previous step is covered with an insulating layer 206 and an opening (etching hole 208) for removing the sacrificial layer 209 is formed. The insulating layer 206 is preferably formed by a vapor deposition method such as CVD or PE-CVD in order to uniformly cover the structure of the previous process without any gaps and without gaps. The etching hole 208 is formed by etching the insulating layer 206, etching the exposed second electrode 205, and etching the lower insulating layer 204, thereby exposing the sacrificial layer 209. In view of processing accuracy, it is preferable to continuously process with one photoresist pattern. In general, plasma etching is performed while switching to an optimum gas type for each layer.

FIG. 4G is a cross-sectional view in which the sacrificial layer 209 is removed from the structure manufactured in the previous step, and the gap 203 is formed. The material used for the sacrificial layer 209 is generally amorphous silicon (a-Si), poly silicon (p-Si), chromium (Cr), molybdenum (Mo), or the like. If it is a-Si or p-Si, it can be selectively removed by dry etching using XeF ₂ gas. The etching selectivity is high with respect to a-Si and p-Si, and silicon oxide, silicon nitride, and a combination of these are commonly used materials. The advantage of removing the sacrificial layer 209 by dry etching is that it can prevent sticking of the membrane in the voids that may occur during wet etching. This manufacturing method is often used with the recent development of manufacturing apparatuses.

  FIG. 5 is a cross-sectional view in which the gap 203 of each cell 101 is sealed under reduced pressure by forming an insulating layer 207. In order to seal the etching hole 208, the insulating layer 207 is preferably formed by a vapor deposition method such as CVD or PE-CVD. A necessary standard for the thickness of the insulating layer 207 is about three times the thickness (height) of the gap 203. The sealing can be confirmed by immersing the sealing surface in a liquid having a low surface tension (such as isopropyl alcohol) and confirming the optical reflection state of the cell surface. The film thickness is only necessary for sealing the etching hole 208, and the insulating layer 207 may be thinned by mechanical polishing, dry etching, or the like after sealing in order to realize the mechanical characteristics of the membrane. When the thickness is reduced, the thickness of the insulating layer 207 can be three times or less the thickness of the gap 203.

  A feature of the manufacturing method according to the present embodiment when dry etching is performed collectively from the upper electrode 205 to the sacrificial layer 209 using the mask pattern of the upper electrode 205 will be described with reference to the drawings.

  FIG. 6A is a diagram showing a cross section of the cell 101 in the etching process of the upper electrode 205. The figure shows that the ion species of the gas ionized from the plasma 1201 are attracted by the bias between the substrates of the etching apparatus, and the etching proceeds with the gas radical species. Here, a trace resulting from a trace such as a fine streak shape 1202 at the end of the region of the upper electrode 205 (the outer peripheral edge of the region viewed from above) is transferred to the lower layer. The trace such as the fine streak shape 1202 may be due to the edge of the resist mask 501 or due to the crystal grain boundary of the upper electrode 205. As for the angle of the side wall with respect to the film surface, there is often a forward taper angle that spreads from the top to the substrate. Of course, by optimizing the exposure end face of the resist 501 (the slope of the side wall of the resist shown in FIG. 6A) and the etching conditions, the angle of the side wall with respect to the film surface can be close to vertical (90 °). Depending on the manufacturing method, a reverse taper angle may occur.

  FIG. 6B is a diagram illustrating a cross section of the cell 101 in the etching process of the insulating layer 204. The insulating layer 204 is etched using the photoresist pattern 501 used in the processing of the second electrode 205. Then, a part of the trace such as the fine streak shape 1202 of the outer peripheral edge carved by the mask 501 in the second electrode layer 205 is taken over and formed in the insulating layer 204 as well. In general, the insulating layer 204 is often dry-etched with a fluorine-based gas, and the etching of the upper second electrode 205 hardly proceeds. In that case, in etching of the insulating layer 204, the photoresist pattern 501 and the second electrode 205 serve as mask materials. In this case as well, the angle of the side wall with respect to the film surface often has a forward taper angle extending from the top to the substrate. Of course, it is possible to approach the vertical (90 °) by optimizing the resist exposure end face and etching conditions. In addition, when the etching gas component contains a large amount of radical species, a slight undercut shape may occur with respect to the second electrode 205. In such a case, it is preferable to adjust the etching conditions so as to avoid the undercut shape.

  FIG. 6C is a diagram illustrating a cross section of the cell 101 in the etching process of the sacrificial layer 209. Since the sacrificial layer 209 is etched using the upper layer mask 501, traces due to traces such as the fine stripe shape 1202 at the end of the region are transferred. Also in this step, it is preferable to adjust the etching conditions so as to avoid the undercut shape of the side wall. As shown in FIG. 6C, the side wall angles of the second electrode 205, the insulating layer 204, and the sacrificial layer 209 may be formed almost continuously and smoothly. There is also an influence on the etching conditions, and a slight difference in side wall angle may occur.

  FIG. 6D shows a top correlation diagram of a structure in which the second electrode 205, the insulating layer 204, and the sacrificial layer 209 are collectively dry-etched using the mask pattern 501 of the upper electrode 205. 1501 indicates the shape difference between the insulating layer 204 and the sacrificial layer 209, and 1502 indicates the shape difference between the second electrode 205 and the insulating layer 204.

  When observed with a high-resolution scanning electron microscope (FE-SEM), a shape that gently spreads from the upper layer toward the substrate is observed. For example, if the angle of the side wall is 45 °, a spread of about 70% of the film thickness is formed on one side. If the thickness of the sacrificial layer 209 is 200 nm, the spread of the sacrificial layer is about 140 nm on one side. If the side wall angle can be formed substantially vertically, the spread width becomes very small. Further, when viewed from above the substrate, the processed regions of the insulating layer 204 and the sacrificial layer 209 have a substantially isotropic shape with respect to the mask pattern 501 of the upper electrode 205. That is, as shown in FIG. 6D, the edges of the processing regions of the insulating layer 204 and the sacrificial layer 209 are drawn in parallel at a minute equidistant distance from the edge of the mask pattern 501 in all directions. The The difference (absolute value) between the area of the gap 203 and the area of the second electrode 205 as viewed from above is preferably at least 5% or less, preferably 1% or less of the area of the gap 203. When the cell diameter is 10 μm, the undercut amount is about 25 nm if it is within 1%, and about 125 nm if it is within 5%. This undercut amount can be calculated by multiplying approximately 1/2 of the area difference (in%) by the cell radius. When the area difference is 1%, since the cell radius is 5 μm and 1/2 of the area difference is 0.5%, the undercut amount is about 25 nm. When the area difference is 5%, the cell radius is Since 1/2 of the area difference is 2.5% at 5 μm, the undercut amount is about 125 nm. When the cell diameter is 40 μm, the undercut amount is about 100 nm if it is within 1%, or about 480 nm if it is within 5%. In the present embodiment, the cell diameter, that is, the void diameter can be designed in the range of 5 μm to 40 μm.

  Next, an embodiment of an object information acquiring apparatus using the capacitive transducer of the present invention will be described with reference to the drawings. FIG. 7 is a perspective view of an ultrasonic probe using the capacitive transducer of the present invention. The ultrasonic probe includes a capacitive transducer 1601, an acoustic matching layer 1602, an acoustic lens 1603, and a circuit board 1604. As shown in FIG. 7, the transducer 1601 has a large number of elements 1605 arranged in the X direction like a one-dimensional array. Although the one-dimensional array is shown in FIG. 7, the elements may be a two-dimensional array or may have other shapes such as a convex type. The transducer 1601 is mounted on the circuit board 1604 and is electrically connected. The circuit board 1604 may be a board integrated with the transmission / reception circuit, or may be connected to the transmission / reception circuit via the circuit board. An acoustic matching layer 1602 is provided on the surface side where the transducer 1601 transmits acoustic waves in order to match the acoustic impedance with the subject. The acoustic matching layer 1602 may be provided as a protective film for preventing electrical leakage to the subject. An acoustic lens 1603 is disposed via the acoustic matching layer 1602. As the acoustic lens 1603, it is preferable to use a lens that can match the acoustic impedance between the subject and the acoustic matching layer 1602. When an acoustic lens 1603 having a curvature in the Y direction as shown in FIG. 7 is provided, an acoustic wave spreading in the Y direction can be narrowed at the focal position of the acoustic lens 1603. Since the acoustic wave spreading in the X direction cannot be narrowed as it is, the acoustic wave can be narrowed at the focal position by performing transmission driving by beam forming while shifting the timing of transmitting the acoustic wave for each element 1605. The shape of the acoustic lens 1603 is preferably a shape that provides a desired acoustic wave distribution characteristic. In addition, the type and shape of the acoustic matching layer 1602 and the acoustic lens 1603 may be selected according to the type of the object to be used, or these may not be provided.

  The probe may be mechanically scanned or may be moved (handheld) by a user such as a doctor or engineer relative to the subject. The capacitive transducer that transmits the acoustic wave may be used also as the receiving capacitive transducer, or may be separate. Further, the subject may be used as a probe for irradiating the subject with pulsed light energy and receiving the generated photoacoustic wave.

  FIG. 8 shows a block diagram of the configuration of the processing / control unit of the subject information acquiring apparatus using the ultrasonic probe 1705. A control signal is transmitted from the system control unit 1701 to the bias voltage control unit 1702 and the transmission drive voltage control unit 1703, and a voltage is applied to the capacitive transducer (ultrasonic probe) 1705 through the transmission / reception circuit 1704 to generate an acoustic wave. To do. In order to generate the desired transmission sound pressure, for example, a negative DC bias voltage is applied to one electrode of the element, and a dipole wave or monopolar wave having a required pulse width is applied to the other electrode of the element. Is done.

  After irradiating the subject with acoustic waves, the reception signal reflected from the inside of the subject and received by the ultrasonic probe is subjected to signal amplification processing and A / D conversion by the transmission / reception circuit 1704, and then the image processing unit 1706. In the image processing unit 1706, the time signal of each element 1605 is reconstructed into a two-dimensional image, and processing is performed to make it easy for the user to visually recognize. The processed image information is visually recognized by the user on the display unit 1707. This block diagram is generally known as an object information acquisition apparatus, and adds the functions necessary for guaranteeing the transmission and reception performance of acoustic waves of the ultrasonic probe 1705, and reliability and safety. It doesn't matter.

  According to the present embodiment, since the electrodes can be formed in almost all of the membrane region when the cell is viewed in plan view from above, it is possible to suppress a decrease in the utilization efficiency of the membrane, and to perform transmission efficiency and reception as an ultrasonic device. A decrease in sensitivity can be suppressed. In addition, since the step between the electrode on the cell membrane and the wiring that electrically connects the cells can be substantially prevented, an increase in electrical resistance due to deterioration in step coverage can be suppressed. . This also contributes to suppression of a decrease in transmission efficiency and reception sensitivity. Furthermore, since the lower layer is processed using the electrode pattern in the membrane region, it contributes to an improvement in manufacturing yield and cost reduction by reducing the exposure process.

[Embodiment 2]
Embodiment 2 will be described. The process up to forming the second electrode 205 is the same as that described in the first embodiment. The items other than those described below are the same as in the first embodiment.

  In the present embodiment, when Cr or Mo is used for the sacrificial layer 209, not only dry etching but also a commercially available mixed acid solution is used in the processing step of the sacrificial layer 209 in FIG. It can also be selectively removed. In particular, since the etching selectivity with respect to silicon oxide or silicon nitride can be ensured to be almost infinite, this method can be selected depending on the structure of the cell 101 or the membrane. However, when an acid solution is used for etching the sacrificial layer 209, the second electrode 205 is exposed, and therefore, it is preferable to select a material with a high etching selectivity for the second electrode 205. In view of the etching selectivity, the insulating layer 204 is suitably made of silicon oxide or silicon nitride.

  FIG. 9 shows a cross-sectional correlation diagram when the second electrode 205 is processed by wet etching, the insulating layer 204 is processed by dry etching, and the sacrificial layer 209 is processed by wet etching. 1802 shows the shape difference between the second electrode 205 and the insulating layer 204, and 1801 shows the shape difference between the insulating layer 204 and the sacrificial layer 209. The shape differences 1801 and 1802 reflect the undercut accompanying wet etching.

  When acid-based wet etching is selected in the processing of the sacrificial layer 209, it is difficult to use an Al alloy for the second electrode 205. Therefore, a material having an etching selectivity such as Au is selected. In that case, dry etching or wet etching may be selected in the processing of the second electrode 205. Here, a case where the second electrode 205 is processed by wet etching is shown.

  When wet etching is used in the processing of the second electrode 205, the upper photoresist mask 501 often has a slightly undercut shape. Then, since the insulating layer 204 is formed using a photoresist obtained by processing the second electrode 205, the undercut shape of the second electrode 205 often remains as a terrace shape (indicated by 1805 in FIG. 9). In general, the undercut amount is at least 1 times the film thickness. When wet etching is used in the processing of the sacrificial layer 209, it is assumed that the upper insulating layer 204 has a slightly undercut shape (indicated by 1806 in FIG. 9). In this case as well, the undercut amount is often formed to be at least one times the film thickness.

  As described above, when wet etching is used in some processing steps as well as dry etching, an undercut with respect to the mask 501 is formed, and a discontinuous step is finally formed in the cross section. However, since the thickness of the second electrode 205 and the sacrificial layer 209 is as thin as about 100 nm to several 100 nm, the undercut with respect to the shape of the upper layer 204 is small. In this case, the shape of the side wall is a discontinuous concave step, but the shape of the lower layer is substantially isotropic as described above with respect to the shape of the upper electrode 205. Also in this case, it is preferable that the difference between the area of the gap 203 and the area of the second electrode 205 is at least within 5%, desirably within 1%. The cell structure formed on this premise will be described with reference to the drawings.

  10 is a cross-sectional view of the cell 101 in the AB direction, and FIG. 11 is a cross-sectional view of the cell 101 in the CD direction. When the shape of the second electrode 205 and the sacrificial layer 209 is formed by wet etching, a discontinuous step is formed on the side wall of the cell portion. In the final membrane structure, the sacrificial layer 209 is removed to form a gap 203, but the shape is formed on the membrane support portion (indicated by 1901 in FIGS. 10 and 11) located on the opposite side of the side wall portion where the sacrificial layer 209 is located. Is transcribed. As described above, a characteristic microstructure is formed in the structure of the CMUT cell 101 formed by the manufacturing method of the present embodiment and the side wall of the wiring (102, 105, 106). These characteristics can be easily confirmed with a high-resolution scanning electron microscope (FE-SEM).

  Also according to the present embodiment, since electrodes can be formed in almost all membrane regions corresponding to the void regions when the cell is viewed from above, it is possible to suppress a decrease in the utilization efficiency of the membrane, A decrease in transmission efficiency and reception sensitivity can be suppressed. In addition, an increase in electrical resistance due to a deterioration in step coverage is suppressed, which contributes to an improvement in manufacturing yield and a reduction in cost by reducing the exposure process.

[Embodiment 3]
A third embodiment will be described. A structure and a manufacturing method are substantially the same as the description described in Embodiment 1, and it applies to Embodiment 1 except the matter described below. FIG. 12 is a top view illustrating the capacitive transducer according to the present embodiment. In this configuration, the sacrificial layer 209 under the lead-out wiring region 105 that collects and draws signals having a plurality of cell structures is removed.

  Generally, in order to increase the reception sensitivity, it is necessary to reduce the parasitic capacitance with respect to the active capacitance of the CMUT, and therefore the lower electrode 201 in the lead-out wiring region 105 is usually removed. However, when the semiconductor substrate itself is electrically grounded, the wiring is not completely floated and some parasitic capacitance remains through the substrate. On the other hand, by removing the sacrificial layer 209 in the lower region 7 of the wiring region 105, it is possible to provide a gap 203 between the wiring and the substrate, thereby reducing the electric field strength applied in the film and further reducing the parasitic capacitance. As a secondary effect, the thermal oxide film directly on the semiconductor substrate can be thinned (shortening the thermal oxidation process), and the processing time for opening the thermal oxide film in order to place the substrate on the ground is also shortened. be able to.

In this embodiment, for example, when XeF ₂ gas is used in the sacrificial layer removal step, the etching rate can be estimated depending on the distance from the etching gas supply port (etching hole 103) and the cross-sectional area of the sacrificial layer 209. Is possible. Therefore, the etching hole 103 is disposed close to a region where the sacrificial layer is to be removed under the wiring. When it is desired to remove the sacrificial layer 209 in the lead-out wiring region 105, the etching hole 103 is disposed along the wiring in the lead-out wiring region 105 as shown in FIG. Conversely, when it is desired to leave the sacrificial layer 209 in the lead-out wiring region 105, as shown in the first embodiment, the etching hole 103 is moved away to allow an etching time, thereby leaving a region where the sacrificial layer is not removed. Is also possible.

  Also according to the present embodiment, since electrodes can be formed in almost all membrane regions corresponding to the void regions when the cell is viewed from above, it is possible to suppress a decrease in the utilization efficiency of the membrane, A decrease in transmission efficiency and reception sensitivity can be suppressed. Further, the parasitic capacitance can be further reduced.

Examples of the present invention will be described below, but the present invention is not limited to the examples.
(Example 1)
FIG. 1 is a top view of the capacitive transducer according to the first embodiment. 2 is a cross-sectional view of the cell 101 (AB cross-section), and FIG. 3 is a cross-sectional view of the cell 101 (CD cross-section). In this embodiment, the second electrode 205, the insulating layer 204, and the sacrificial layer 209 are dry-etched using a photoresist pattern 501 for processing the second electrode 205. The cell diameter is 50 μm, and 196 one element 104 in which 450 cells 101 are arranged in a range of 0.3 mm × 4.0 mm is arranged.

  The structure and manufacturing method of the manufactured capacitive transducer will be specifically described. First, the steps up to FIG. 4A will be described in detail. FIG. 4A is a process until the second electrode 205 is formed on the upper layer of the semiconductor substrate. The Si substrate is oxidized in a steam atmosphere at 1100 ° C. for 2 hours and 30 minutes to form a thermal oxide film of 1000 nm. A hole portion for securing a GND (ground) potential is formed in the Si substrate, an Al film is formed by sputtering in the hole portion, and an electrode portion is formed by a general photolithography process or a dry etching process using vacuum plasma.

  Next, in the element region of the capacitive transducer, a W film is formed with a thickness of 100 nm, and a Ti film is formed thereon with a 10 nm sputtering apparatus, and a lower electrode 201 is formed by a photolithography process and a dry etching process using vacuum plasma. . In order to suppress the parasitic capacitance of the device, the lower electrode is not disposed in the wiring region 105 where the wiring is drawn out to the external substrate.

  Next, an SiO film as an insulating film 202 is formed to a thickness of 700 nm by PE-CVD on the lower electrode 201, and a hole for making electrical contact with the lower electrode 201 is formed by a photolithography process. Next, an a-Si film is deposited as a sacrificial layer 209 by 240 nm by PE-CVD. Next, as the insulating layer 204, a SiN film having a tensile stress (200 MPa or less) is formed to 400 nm by PE-CVD. On this upper layer, an AlNd film is deposited as an upper electrode 205 to a thickness of 100 nm using a sputtering apparatus.

  In the process of FIG. 4-1 (b), the upper electrode 205 is integrated with a round shape having a cell diameter of 50 μm, wiring for electrically connecting adjacent cells, structures for etching holes adjacent to each cell, and wiring. A photoresist pattern 501 of wiring for connecting to an external substrate is formed. Since a plurality of layers are etched using this pattern 501, the resist thickness is set to 3.5 μm in consideration of the etching selectivity.

4-1 (c) to 4-2 (e), etching is continuously performed from the AlNd film of the upper electrode 205 to the a-Si film of the sacrificial layer 209 by a high-density plasma dry etching apparatus. Do. Etching of the AlNd film of the upper electrode 205 is performed using an RF power of 600 W, a substrate bias of 200 W, and an etching gas using a mixed gas of Cl ₂ and BCl ₃ .

In the process of FIG. 4D, the SiN film 204 below the upper electrode 205 has a low etching rate due to the chlorine-based gas, so that the gas type is switched to SF ₆ for etching. In the step of FIG. 4E, the a-Si film of the sacrificial layer 209 under the SiN film of the insulating layer 204 is etched with a chlorine-based gas. Since the SiO film 202 is formed as the lower layer of the a-Si film and the etching rate of the SiO film with respect to the chlorine-based gas is low, it functions well as an etching stop layer. Thus, process yield is considered.

  As described above, the upper electrode 205 / insulating layer 204 / sacrificial layer 209 were collectively etched to produce a shape in which the shapes of the upper electrode 205 and the sacrificial layer 209 in plan view from above are substantially the same. The taper shape of the side wall portion of each layer was about 80 °, and a smooth side wall shape substantially continuous from the upper electrode 205 to the sacrificial layer 209 was obtained. Since the lower layer is processed using the photoresist mask 501 for forming the upper electrode 205, the shape of the sacrificial layer 209 in plan view from above is substantially isotropic as described above with respect to the shape of the upper electrode 205. It became.

Further, in the process of FIG. 4-2 (f), a SiN film which is an insulating layer 206 having a tensile stress (200 MPa or less) is formed by PE-CVD to a thickness of 450 nm. Next, an opening (etching hole 208) for removing the sacrificial layer 209 is formed. First, the SiN film 206 is etched with SF ₆ , and the exposed AlNd film of the upper electrode 205 is continuously etched with a mixed gas of Cl ₂ and BCl ₃ . Further, the SiN film 204 exposed in the lower layer is etched with SF ₆ to expose the a-Si film of the sacrificial layer 209.

In the process of FIG. 4G, the a-Si of the sacrificial layer 209 is etched using XeF ₂ gas with an etching apparatus manufactured by Memsstar. The etching conditions were 9.5 Torr, substrate temperature 15 ° C., N ₂ gas as a carrier gas, and a slight amount of H ₂ gas was added to ensure the selection ratio of the SiN films 204 and 206. Since the selection ratio between the a-Si and SiN of the sacrificial layer in the XeF ₂ gas cannot be ensured infinitely, the etching time is limited to the extent that the region of the element 104 is etched, and the a-Si of the sacrificial layer 209 in the extraction wiring region 105 Is not removed. Thus, by removing a-Si from the sacrificial layer 209, the void 203 under the membrane is formed.

  In the process of FIG. 5, an SiN film of an insulating layer 207 having a tensile stress (200 MPa or less) is formed to 2000 nm by PE-CVD, and the etching hole 208 is sealed. Next, an opening 106 in which wirings in the lead-out wiring region 105 are gathered for mounting on an external electric substrate, an opening for drawing out the lower electrode 201, and an opening for wiring out the substrate GND (ground). Are formed by a general-purpose photolithography process. Then, an Al film is formed by sputtering with a thickness of 500 nm, and wiring (not shown) to be drawn to the external substrate is formed by a general-purpose photolithography process and dry etching using vacuum plasma. This is an extension of wiring necessary to electrically mount the external signal line to the element portion, and has the function of not increasing the wiring resistance during the extension and ensuring the flexibility of the base necessary in the wire bonder region. . Thereafter, it is protected with a resist, and the wafer is divided into capacitive transducers by a dicing apparatus.

  Next, the manufactured capacitive transducer is fixed to an external substrate, and wiring is connected to the external substrate with a wire bonder. A negative DC voltage is applied to the lower electrode 201 in common to all elements, and the upper electrode 205 is configured to be able to input a signal to each element 104 independently. When the capacitive transducer surface is immersed in oil (diisodecyl sebacate) and driven by applying a bias voltage of -290 V and an AC waveform of ± 100 V, the transmitted sound pressure is approximately 0.9 MPa (converted to a plane wave) at a position 2 mm directly above the device. ) Also, a good value of about 2.5 Pa was obtained for noise characteristics (NEP; Noise Equivalent) which is a measure of reception sensitivity.

FIG. 7 shows an ultrasonic probe using a capacitive transducer according to the present embodiment, and FIG. 8 shows an object information acquiring apparatus using the ultrasonic probe. The ultrasonic probe will be described with reference to FIG. An object information acquisition apparatus including an ultrasonic probe in which 196 elements 1605 each having a size of about 0.3 mm × 4 mm constituted by cells are arranged in a one-dimensional direction and an acoustic matching layer 1602 and an acoustic lens 1603 are arranged on the upper layer. To manufacture. The acoustic matching layer 1602 uses a silicone adhesive having an acoustic impedance of 1.082 MRayls and an attenuation coefficient of 1.47 × (frequency) ^1.44 dB / cm / MHz. Further, the acoustic lens 1603 has a shape with an acoustic impedance of 1.22 MRayls, an attenuation coefficient of 3.1 × (frequency) ^1.4 dB / cm / MHz, and an average thickness of 530 μm.

  A bias potential can be supplied to the lower electrode 201 of each element through the common electrode of the semiconductor substrate, and the upper electrode 205 is drawn out for each element and connected to the external substrate by a wire bonder. Transmission / reception circuits are arranged on the external substrate, and all 196 channels and corresponding channels on the system side are connected by coaxial thin cables of AWG 40 size.

  Next, the subject information acquisition apparatus will be described with reference to FIG. In this system, the bias voltage control unit 1702 is controlled to output a DC negative voltage with a pull-in voltage ratio of 80%. Based on the trigger signal from the user, the transmission drive voltage control unit 1703 is controlled to generate an acoustic wave having a necessary phase difference from each channel of the transducer. Here, control is performed so that a bipolar wave (AC) of 20% of the pull-in voltage is output with a pulse width of 45 nsec. The transmission / reception circuit 1704 includes a function that can automatically determine whether the acoustic wave is transmitted or received based on a voltage threshold value of a bipolar wave input / output to / from the capacitive transducer 1705.

  The probe 1705 was brought into contact with the medical image phantom, an acoustic wave was transmitted, and a wave reflecting the difference in acoustic impedance was received. The time axis image for each channel was reconstructed into an XY two-dimensional image, and image processing such as necessary filtering was performed to obtain an ultrasonic image on the display unit 1707.

(Example 2)
A cross-sectional configuration of the cell 101 according to the second embodiment will be described with reference to FIGS. 10 is a cross-sectional view of cell 101 (A-B cross section in FIG. 1), and FIG. 11 is a cross-sectional view of cell 101 (C-D cross section in FIG. 1). The difference from Example 1 is that, using a photoresist pattern for processing the second electrode 205, the second electrode 205 is wet-etched, the insulating layer 204 is dry-etched, and the sacrificial layer 209 is wet-etched. is there. That is, the dry etching and wet etching are used in combination. Therefore, the upper electrode 205 and the gap layer 203 have a slight undercut shape with respect to the insulating layer 204. The configuration such as the cell diameter is the same as that of the first embodiment.

  First, the process up to FIG. 4A will be described in detail. FIG. 4A shows a process until the second electrode 205 is formed on the upper layer of the semiconductor substrate. Similar to the first embodiment, a thermal oxide film having an opening pattern connected to the substrate GND is formed on the Si semiconductor substrate by 1000 nm, the lower electrode W is formed by 100 nm, and Ti is formed by 10 nm in the region of the element 104. A SiO film of 700 nm is formed.

  Next, a Cr film having a thickness of 240 nm is formed as a sacrificial layer 209 using a sputtering apparatus. Next, a SiN film having a tensile stress of about 200 MPa is formed as an insulating layer 204 by PE-CVD to a thickness of 400 nm. Next, an Au film is formed as an upper electrode 205 to a thickness of 100 nm using a sputtering apparatus.

  In the step of FIG. 4B, the round shape with a cell diameter of 50 μm, the wiring 102 for electrically connecting adjacent cells, the structure 103 for etching holes adjacent to each cell, and the wiring are integrated on the upper electrode 205. Then, a resist pattern of the wiring region 105 for connecting to the external substrate is formed. In the process of FIG. 4C, a plurality of layers are etched using this pattern. Since Au of the upper electrode 205 and Cr of the sacrificial layer 209 are processed by wet etching and SiN of the insulating layer 204 under the upper electrode 205 are processed by dry etching, the thickness of the resist 501 is set to 2.5 μm in consideration of the etching selectivity. And When the shape of the upper electrode 205 made of Au is wet-etched with a commercially available solution, an undercut of about 200 nm occurs on the mask 501 (the undercut shape is not shown).

  In the process of FIG. 4D, the SiN of the lower insulating layer 204 is etched by a dry etching apparatus while keeping the mask shape including the upper electrode 205. A terrace region of about 200 nm is formed in the SiN of the insulating layer 204. In the process of FIG. 4-2 (e), Cr of the sacrificial layer 209 is etched with a commercially available solution in the mask shape. An undercut of about 250 nm is formed on the Cr side wall of the sacrificial layer 209 with respect to the mask shape of the upper electrode 205. Since the lower layer is processed using the photoresist mask 501 for forming the upper electrode 205, the shape of the sacrificial layer 209 is as compared with the shape of the upper electrode 205 as described above, although there is a nano-order step in the undercut shape. And is approximately isotropic.

In the process of FIG. 4B, a SiN film of the insulating layer 206 having a tensile stress (200 MPa or less) is formed to 450 nm by PE-CVD. Next, an opening (etching hole 208) for removing the sacrificial layer 209 is formed. First, the SiN film is etched by SF ₆ , the exposed Au of the upper electrode 205 is etched by wet etching while keeping the same mask, and further, the SiN film of the insulating layer 204 exposed to the lower layer is etched by SF ₆ and sacrificed. The Cr of layer 209 is exposed.

  In the process of FIG. 4-2 (g), Cr of the sacrificial layer 209 is etched, but the selection ratio between the Cr of the sacrificial layer 209 and the SiN of the insulating layer 204 can be secured infinitely, so it is immersed in the etchant for about 5 hours. To do. In this way, by removing Cr from the sacrificial layer 209, the void 203 under the membrane is formed. In the washing process after forming the membrane, in order to prevent sticking of the membrane, the liquid is gradually replaced with a low surface tension liquid (isopropyl alcohol, 3M HFE) after washing, and finally the inside of the membrane is dried in an HFE atmosphere. To do.

  In the process of FIG. 5, an SiN film of an insulating layer 207 having a tensile stress (200 MPa or less) is formed to 2000 nm by PE-CVD, and the etching hole 208 is sealed. Next, an opening for forming a wiring for extracting the upper electrode 205, an opening for forming a wiring for extracting the lower electrode 201, and an opening for forming a wiring for extracting the substrate GND are formed by a photolithography process. To do. Then, an Al film is formed by sputtering with a thickness of 500 nm, and wiring (not shown) to be drawn out to the external substrate is formed by a photolithography process and a dry etching process using vacuum plasma.

As in Example 1, the wafer was divided, electric wiring was mounted on the capacitive transducer, and characteristics were evaluated in oil. NEP was 2.1 Pa, which is a slight improvement over Example 1. Was seen. In Example 1, the selection ratio of the exposed SiN film to XeF ₂ was about a certain range of 1000 or more. However, in this example, the selection ratio of the SiN film to the Cr etchant solution is close to infinity. Up to the sacrificial layer can also be removed. As a result, parasitic capacitance can be reduced, which contributes to further improvement in reception sensitivity.

(Example 3)
FIG. 12 is a top view of the capacitive transducer according to the third embodiment. Since the structure and the manufacturing method are similar to those of the first embodiment, the cross-sectional structure of the cell is also shown in FIGS. In this embodiment, as in the first embodiment, the second electrode 205, the insulating layer 204, and the sacrificial layer 209 are dry-etched using the photoresist pattern 501 for processing the second electrode 205. In order to reduce parasitic capacitance, the sacrificial layer in the lead-out wiring region 105 is also removed in the sacrificial layer removal step. In addition, since the cell diameter is changed from 50 μm of Example 1 to 30 μm, one etching hole 103 is assigned to a plurality of cells. The cell diameter is 30 μm, and 196 one element 104 in which 700 cells 101 are arranged in a range of 0.2 mm × 4.0 mm is arranged. The film thickness of each layer is changed to reflect the difference in cell diameter.

  First, the process up to FIG. 4A will be described in detail. FIG. 4A shows the next state. That is, in the region of the element 104, W of the lower electrode 201 is 100 nm, Ti is 10 nm, the SiO film of the insulating layer 202 is 300 nm, the a-Si of the sacrificial layer 209 is 200 nm, and the SiN of the upper insulating layer 204 is 400 nm. An AlNd of the electrode 205 is formed to 100 nm.

  Next, the next formation is performed in the step of FIG. That is, on the upper electrode 205, a round shape with a cell diameter of 30 μm, a wiring 102 for electrically connecting adjacent cells, a structure for the etching hole 103 adjacent to each cell 101, and wiring are collected and connected to an external substrate. A resist pattern 501 of the wiring region 105 is formed. Since a plurality of layers are etched using this pattern, the resist thickness is set to 3.0 μm in consideration of the etching selectivity.

  In the process of FIGS. 4-1 (c) to 4-2 (e), the dry etching apparatus using high-density plasma continuously performs from the AlNd film of the upper electrode 205 to the a-Si film of the sacrificial layer 209. Etching is performed. In this manner, the upper electrode 205 / insulating layer 204 / sacrificial layer 209 are collectively etched to produce a shape in which the shapes of the upper electrode 205 and the sacrificial layer 209 are substantially the same. The taper shape of the side wall portion is about 80 °, and a smooth side wall shape substantially continuous from the upper electrode 205 to the sacrificial layer 209 is obtained. Since the lower layer is processed using the photoresist mask 501 for forming the upper electrode 205, the shape of the sacrificial layer 209 is substantially isotropic with respect to the shape of the upper electrode 205 as described above.

In the step of FIG. 4B, a SiN film of the insulating layer 206 having a tensile stress (200 MPa or less) is formed to 350 nm by PE-CVD. Next, an opening (etching hole 208) for removing the sacrificial layer 209 is formed. First, the SiN film is etched with SF ₆ , the exposed AlNd film of the upper electrode 205 is continuously etched with a mixed gas of Cl ₂ and BCl ₃ , and the SiN film exposed to the lower layer is etched with SF _6. Then, the a-Si film of the sacrificial layer 209 is exposed.

In the process of FIG. 4G, the a-Si of the sacrificial layer 209 is etched using XeF ₂ gas with an etching apparatus manufactured by Memsstar. Etching conditions are 9.5 Torr, a substrate temperature of 15 ° C., introduction of N ₂ gas as a carrier gas, and a slight amount of H ₂ gas is added to ensure the selectivity of the SiN film. Since the cell diameter is smaller than that in the first embodiment, the number of the etching holes 103 is reduced and the arrangement thereof is changed in consideration of the reduction of the etching area amount that the single etching hole 103 is responsible for. In this embodiment, the etching hole 103 is positively arranged in the wiring region 105 in order to remove the a-Si in the sacrifice layer 209 in the lead-out wiring region 105. By removing a-Si in the sacrificial layer 209 with such a configuration, the void 203 under the membrane is formed.

  Next, in the process of FIG. 5, an SiN film of an insulating layer 207 having a tensile stress (200 MPa or less) is formed to 800 nm by PE-CVD, and the etching hole 208 is sealed. Next, an opening for forming a wiring for extracting the upper electrode 205, an opening for forming a wiring for extracting the lower electrode, and an opening for forming a wiring for extracting the substrate GND are formed by a general-purpose photolithography process. To do. Then, an Al film is formed by sputtering with a thickness of 500 nm, and wiring (not shown) to be drawn to the external substrate is formed by a general-purpose photolithography process and dry etching using vacuum plasma. This is an extension of wiring necessary for electrical mounting to the element portion, and has a function of not increasing the wiring resistance during the extension and ensuring the flexibility of the foundation required in the wire bonder region.

  The manufactured capacitive transducer was electrically mounted in the same manner as in Example 1, dipped in oil (diisodecyl sebacate), and driven by applying a bias voltage of −170 V and an AC waveform of ± 60 V. At this time, a transmission sound pressure of about 0.5 MPa (plane wave conversion) was obtained at a position 2 mm directly above the device. In the present embodiment, since the cell diameter was made smaller than those in the first and second embodiments, characteristics with a wide bandwidth of 120% or more in the reception sensitivity ratio band and the transmission efficiency ratio band were obtained. Also, a good value of about 2.2 Pa was obtained for the noise characteristic (NEP) which is a measure of the reception sensitivity.

In this embodiment, considering that the selection ratio of the SiN film to XeF ₂ is about a certain range of 1000 or more, an etching hole 103 for removing the sacrificial layer in the lead-out wiring region 105 is disposed in the wiring region 105. As a result, the parasitic capacitance can be further reduced, which contributes to further improvement in reception sensitivity.

  101: cell, 102: wiring, 104: element, 201: first electrode (lower electrode), 203: gap, 204: insulating layer, 205: second electrode (upper electrode), 209: sacrificial layer, 501: Photoresist pattern (mask pattern)

Claims (16)

One or more elements having a cell including a structure in which a vibration film including at least a second electrode provided with a gap between the first electrode and the first electrode is supported, and the cell of the element includes an adjacent cell and , A capacitive transducer electrically connected by a wire connected to the second electrode,
The capacitance type transducer, wherein the shape of the second electrode viewed from above is substantially the same as the shape of the gap.   The capacitive transducer according to claim 1, wherein the first electrode is formed on a semiconductor substrate.   3. The capacitive transducer according to claim 1, wherein a shape of the wiring viewed from above is substantially the same as a shape of a void layer connected to the void. 4.   4. The capacitance according to claim 1, wherein a gap is included in a lower portion of a wiring region that collects and draws out the second electrode of the cell included in the wiring and the element. 5. Type transducer.   5. The vibration film includes an insulating layer that seals an opening used to remove a sacrificial layer in the gap when the gap is formed. 2. The capacitive transducer according to item 1.   The shape of the film included in the vibration film in the lower layer of the second electrode is such that the edge is drawn parallel to the shape of the second electrode viewed in plan from above with a minute equidistant distance. Have tapered sidewalls, or edges are defined in parallel at a minute equidistant and have opposite tapered sidewalls, or overlap, or edges are depicted in parallel at a minute equidistant under 6. The capacitive transducer according to claim 1, further comprising a cut side wall.   7. The capacitive transducer according to claim 1, wherein a diameter of the gap is in a range of 5 μm to 40 μm.   8. The difference between the area of the gap and the area of the second electrode as viewed in plan from above is 5% or less of the area of the gap. 9. Capacitive transducer.   9. The capacitive transducer according to claim 8, wherein a difference between the area of the gap viewed from above and the area of the second electrode is 1% or less of the area of the gap.   The vibrating membrane includes the second electrode and an insulating layer under the second electrode, and the insulating layer takes over fine traces formed on the outer peripheral edge of the second electrode. The capacitive transducer according to any one of claims 1 to 9, wherein the trace is transferred.   An insulating layer is formed on the first electrode, the vibration film includes another insulating layer, and the insulating layer and the other insulating layer are each formed of silicon oxide or silicon nitride. The capacitive transducer according to any one of claims 1 to 10, wherein:   The capacitive transducer according to claim 11, wherein the insulating layer and the other insulating layer are formed of different materials. A method for manufacturing a capacitive transducer comprising at least one element having a cell including a structure in which a vibrating membrane including at least a second electrode provided with a gap between the first electrode and a first electrode is supported,
At least a step of forming a sacrificial layer on the first electrode, a step of forming a first insulating layer on the sacrificial layer, and forming the second electrode on the first insulating layer. Forming a second insulating layer on the second electrode; removing the sacrificial layer to form the gap; forming a third insulating layer on the second insulating layer; And sealing the opening used to remove the sacrificial layer,
In the step of forming the gap by removing the sacrificial layer, etching is performed to a position including the sacrificial layer located in a lower region of the second electrode, using a mask shape that forms the second electrode. A method of manufacturing a capacitive transducer characterized by the above.   14. The method of manufacturing a capacitive transducer according to claim 13, further comprising a step of removing the sacrificial layer located under the wiring region.   15. The method of manufacturing a capacitive transducer according to claim 14, further comprising a step of removing the sacrificial layer located below a wiring region that collects and draws out the second electrodes of the cell.   In the etching process, the dry etching is performed up to a position including the sacrificial layer located in the lower region of the second electrode and the wiring, or the dry etching and the wet etching are used in combination. The method for manufacturing a capacitive transducer according to any one of claims 13 to 15.