CN113990835A - 基于覆铜陶瓷基板布置的功率半导体模块结构 - Google Patents

基于覆铜陶瓷基板布置的功率半导体模块结构 Download PDF

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CN113990835A
CN113990835A CN202111188481.XA CN202111188481A CN113990835A CN 113990835 A CN113990835 A CN 113990835A CN 202111188481 A CN202111188481 A CN 202111188481A CN 113990835 A CN113990835 A CN 113990835A
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power semiconductor
copper
clad
upper bridge
ceramic substrate
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高崎哲
王庆凯
毛先叶
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Zhenghai Group Co ltd
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
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    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
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    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
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    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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Abstract

本发明公开了一种基于覆铜陶瓷基板布置的功率半导体模块结构，本结构中覆铜陶瓷基板分别设有上桥、下桥源极和门极PIN针，覆铜陶瓷基板两侧设有上桥覆铜纹路、中部间隔设于两列下桥覆铜纹路，若干上桥和下桥功率半导体芯片间隔设于上桥覆铜纹路和下桥覆铜纹路，正极母排连接上桥覆铜纹路并且正极母排电流经上桥覆铜纹路分流后汇入三相母排，三相母排连接下桥覆铜纹路并且三相母排经下桥覆铜纹路分流后汇入负极母排，若干上桥功率半导体芯片的源极和门极连接上桥源极和门极PIN针，若干下桥功率半导体芯片的源极门极连接下桥源极和门极PIN针。本结构实现均流特性,确保功率半导体模块开管一致性，提高功率半导体模块使用寿命及性能。

Description

基于覆铜陶瓷基板布置的功率半导体模块结构
技术领域
本发明涉及功率半导体技术领域，尤其涉及一种基于覆铜陶瓷基板布置的功率半导体模块结构。
背景技术
功率半导体模块是将功率半导体芯片按照一定的功能组合封装成一个整体的电路模块,具有尺寸小、功率密度高等优点,因此在新能源汽车领域有着广泛的应用。随着新能源汽车高功率、长续航的发展，功率半导体模块的应用环境日益严苛，功率半导体模块的均流特性得到广泛关注。
随着新能源汽车的快速发展,Si基和SiC基功率半导体模块得到持续发展。在这些大功率的应用领域,对功率半导体模块的开关频率提出了越来越高的要求。为了获得更高的额定电流和更低的制造成本,这些功率半导体模块通常采用多芯片并联的封装结构。然后,由于覆铜陶瓷基板的电流回路不对称、功率芯片的动静态参数不一致,并联芯片间会出现较大的暂态不平衡电流,给功率半导体模块的安全和稳定带来不小的挑战。
在三相交流电机控制系统中，功率半导体模块的电路图如图1所示，各相回路中并联连接多个功率半导体芯片a1至a6、b1至b6。如图2所示为U相电路图,在图2的电路图中，当上桥功率半导体芯片a1至a6导通,下桥功率半导体芯片b1至b6断开时，电流Ia从正极母排流向三相母排。各功率半导体芯片的源极与门极控制回路信号的电阻值、长度产生的电感、功率半导体芯片之间的电阻和电感等决定了各功率半导体芯片的开管时间。假设功率半导体芯片a1的开关时间早于其他功率半导体芯片，则大电流集中流过功率半导体芯片a1，极端情况下，会导致功率半导体芯片a1的损坏。同时，如图3所示，当下桥功率半导体芯片b1至b6导通，上桥功率半导体芯片a1至a6断开时，电流Ia从三相母排流向负极母排。在这种情况下，如上所述，若最靠近三相母排的功率半导体芯片b3的开管时间早于其他功率半导体芯片时，电流集中流过功率半导体芯片b3，极端情况下，会对功率半导体芯片b3造成破坏。如此，降低了功率半导体模块的使用寿命及性能，严重影响电机的控制性能，并存在一定的安全隐患。
发明内容
本发明所要解决的技术问题是提供一种基于覆铜陶瓷基板布置的功率半导体模块结构，本结构克服传统功率半导体模块并联芯片间暂态电流不平衡的缺陷，通过调整各功率半导体芯片的开管时间,实现均流特性,确保功率半导体模块的开管一致性，提高功率半导体模块的使用寿命及性能，保证电机的稳定、可靠控制。
为解决上述技术问题，本发明基于覆铜陶瓷基板布置的功率半导体模块结构包括散热器、塑壳、覆铜陶瓷基板、正极母排、负极母排、三相母排、邦定线、若干上桥功率半导体芯片和若干下桥功率半导体芯片，所述覆铜陶瓷基板设于所述散热器表面，所述塑壳设于所述散热器并且包覆所述覆铜陶瓷基板，所述覆铜陶瓷基板分别设有上桥源极PIN针、上桥门极PIN针和下桥源极PIN针、下桥门极PIN针，所述覆铜陶瓷基板两侧分别设有连通的上桥覆铜纹路、中部间隔设于两列下桥覆铜纹路，所述若干上桥功率半导体芯片分别间隔设于所述上桥覆铜纹路，所述若干下桥功率半导体芯片分别间隔设于所述下桥覆铜纹路，所述正极母排连接所述上桥覆铜纹路并且正极母排电流经所述覆铜陶瓷基板两侧的上桥覆铜纹路分流后汇入所述三相母排，所述三相母排连接所述覆铜陶瓷基板中部的两列下桥覆铜纹路并且三相母排经两列下桥覆铜纹路分流后汇入所述负极母排，所述若干上桥功率半导体芯片的源极通过所述邦定线依次串联后连接所述上桥源极PIN针，所述若干下桥功率半导体芯片的源极通过所述邦定线依次串联后连接所述下桥源极PIN针，所述若干上桥功率半导体芯片的门极通过所述邦定线连接所述上桥门极PIN针，所述若干下桥功率半导体芯片的门极通过所述邦定线连接所述下桥门极PIN针。
进一步，所述覆铜陶瓷基板两侧的上桥覆铜纹路在相邻上桥功率半导体芯片之间设有突起浮铜接点，所述若干上桥功率半导体芯片的源极通过所述邦定线连接所述突起浮铜接点实现串联连接。
进一步，所述若干上桥功率半导体芯片在所述上桥覆铜纹路上相邻芯片的间距至少大于或等于芯片最小边长的一半，并且所述覆铜陶瓷基板表面的覆铜厚度为0.3～0.8mm。
进一步，所述上桥源极PIN针与上桥门极PIN针之间的控制信号和所述下桥源极PIN针与下桥门极PIN针之间的控制信号从外部输入，所述上桥源极PIN针和上桥门极PIN针在所述覆铜陶瓷基板上的位置位于距离所述正极母排最远的上桥功率半导体芯片外侧，所述下桥源极PIN针和下桥门极PIN针在所述覆铜陶瓷基板上的位置位于距离所述三相母排最远的下桥功率半导体芯片外侧。
进一步，所述若干上桥功率半导体芯片中各芯片中心距所述正极母排与上桥源极PIN针距离之和相等，并且距离所述正极母排最近的上桥功率半导体芯片距离所述上桥源极PIN针最远，距离所述正极母排最远的上桥功率半导体芯片距离所述上桥源极PIN针最近，所述若干下桥功率半导体芯片中各芯片中心距所述三相母排与下桥源极PIN针距离之和相等，并且距离所述三相母排最近的下桥功率半导体芯片距离所述下桥源极PIN针最远，距离所述三相母排最远的下桥功率半导体芯片距离所述下桥源极PIN针最近。
进一步，所述若干上桥功率半导体芯片和若干下桥功率半导体芯片分别为并联的至少四个功率半导体芯片。
由于本发明基于覆铜陶瓷基板布置的功率半导体模块结构采用了上述技术方案，即本结构覆铜陶瓷基板设于散热器表面，塑壳设于散热器并且包覆覆铜陶瓷基板，覆铜陶瓷基板分别设有上桥源极和门极PIN针、下桥源极和门极PIN针，覆铜陶瓷基板两侧设有连通的上桥覆铜纹路、中部间隔设于两列下桥覆铜纹路，若干上桥功率半导体芯片间隔设于上桥覆铜纹路，若干下桥功率半导体芯片间隔设于下桥覆铜纹路，正极母排连接上桥覆铜纹路并且正极母排电流经覆铜陶瓷基板两侧的上桥覆铜纹路分流后汇入三相母排，三相母排连接覆铜陶瓷基板中部的两列下桥覆铜纹路并且三相母排经两列下桥覆铜纹路分流后汇入负极母排，若干上桥功率半导体芯片的源极通过邦定线依次串联后连接上桥源极PIN针，若干下桥功率半导体芯片的源极通过邦定线依次串联后连接下桥源极PIN针，若干上桥功率半导体芯片的门极通过邦定线连接上桥门极PIN针，若干下桥功率半导体芯片的门极通过邦定线连接下桥门极PIN针。本结构克服传统功率半导体模块并联芯片间暂态电流不平衡的缺陷，通过调整各功率半导体芯片的开管时间,实现均流特性,确保功率半导体模块的开管一致性，提高功率半导体模块的使用寿命及性能，保证电机的稳定、可靠控制。
附图说明
下面结合附图和实施方式对本发明作进一步的详细说明：
图1为三相交流电机控制系统中功率半导体模块电路图；
图2为图1中单相上桥电流流动方向示意图；
图3为图1中单相下桥电流流动方向示意图；
图4为本发明基于覆铜陶瓷基板布置的功率半导体模块结构示意图；
图5为本结构中覆铜陶瓷基板设有突起浮铜接点示意图；
图6为功率半导体模块的整体框图；
图7为功率半导体模块单相内部信号连接示意图；
图8为功率半导体模块单相上半桥信号连接及电流流向示意图；
图9为功率半导体模块单相下半桥信号连接及电流流向示意图；
图10为功率半导体模块单相电路原理图；
图11为电阻电感串联电路示意图。
具体实施方式
实施例如图4所示，本发明基于覆铜陶瓷基板布置的功率半导体模块结构包括散热器8、塑壳3、覆铜陶瓷基板4、正极母排1、负极母排2、三相母排5、邦定线7、若干上桥功率半导体芯片a和若干下桥功率半导体芯片b，所述覆铜陶瓷基板4设于所述散热器8表面，所述塑壳3设于所述散热器8并且包覆所述覆铜陶瓷基板4，所述覆铜陶瓷基板4分别设有上桥源极PIN针S1、上桥门极PIN针G1和下桥源极PIN针S2、下桥门极PIN针G2，所述覆铜陶瓷基板4两侧分别设有连通的上桥覆铜纹路41、中部间隔设于两列下桥覆铜纹路42，所述若干上桥功率半导体芯片a分别间隔设于所述上桥覆铜纹路41，所述若干下桥功率半导体芯片b分别间隔设于所述下桥覆铜纹路42，所述正极母排1连接所述上桥覆铜纹路41并且正极母排1电流经所述覆铜陶瓷基板4两侧的上桥覆铜纹路41分流后汇入所述三相母排5，所述三相母排5连接所述覆铜陶瓷基板4中部的两列下桥覆铜纹路42并且三相母排5经两列下桥覆铜纹路42分流后汇入所述负极母排2，所述若干上桥功率半导体芯片a的源极通过所述邦定线7依次串联后连接所述上桥源极PIN针S1，所述若干下桥功率半导体芯片b的源极通过所述邦定线7依次串联后连接所述下桥源极PIN针S2，所述若干上桥功率半导体芯片a的门极通过所述邦定线7连接所述上桥门极PIN针G1，所述若干下桥功率半导体芯片b的门极通过所述邦定线7连接所述下桥门极PIN针G2。
优选的，如图5所示，所述覆铜陶瓷基板4两侧的上桥覆铜纹路41在相邻上桥功率半导体芯片a之间设有突起浮铜接点c，所述若干上桥功率半导体芯片a的源极通过所述邦定线7连接所述突起浮铜接点c实现串联连接。通过突起浮铜接点的设置可以减小邦定线的长度,提高邦定线的抗振性,从而提高功率半导体芯片的抗振性。
优选的，所述若干上桥功率半导体芯片a在所述上桥覆铜纹路41上相邻芯片的间距至少大于或等于芯片最小边长的一半，并且所述覆铜陶瓷基板4表面的覆铜厚度为0.3～0.8mm。通过提高芯片之间的距离,增大电流路径中的电感,从而抑制功率半导体芯片开管瞬间流过的大电流。
优选的，所述上桥源极PIN针S1与上桥门极PIN针G1之间的控制信号和所述下桥源极PIN针S2与下桥门极PIN针G2之间的控制信号从外部输入，所述上桥源极PIN针S1和上桥门极PIN针G1在所述覆铜陶瓷基板4上的位置位于距离所述正极母排1最远的上桥功率半导体芯片a外侧，所述下桥源极PIN针S2和下桥门极PIN针G2在所述覆铜陶瓷基板4上的位置位于距离所述三相母排5最远的下桥功率半导体芯片b外侧。通过调整控制信号PIN针距离功率半导体芯片的位置不同,调整控制信号到不同功率半导体芯片的电阻及电感,远离控制信号PIN针的延迟时间最长,从而抑制最远功率半导体芯片的电流。
优选的，所述若干上桥功率半导体芯片a中各芯片中心距所述正极母排1与上桥源极PIN针S1距离之和相等，并且距离所述正极母排1最近的上桥功率半导体芯片a距离所述上桥源极PIN针S1最远，距离所述正极母排1最远的上桥功率半导体芯片a距离所述上桥源极PIN针S1最近，所述若干下桥功率半导体芯片b中各芯片中心距所述三相母排5与下桥源极PIN针S2距离之和相等，并且距离所述三相母排5最近的下桥功率半导体芯片b距离所述下桥源极PIN针S2最远，距离所述三相母排5最远的下桥功率半导体芯片b距离所述下桥源极PIN针S2最近。通过上述设置使得电流回路的电感与控制信号回路的电感达到均衡,实现不同芯片的电流均衡。
优选的，所述若干上桥功率半导体芯片a和若干下桥功率半导体芯片b分别为并联的至少四个功率半导体芯片。
本结构利用施加于并联连接的多个功率半导体芯片的源极与门极控制回路信号线的电感和电流路径的电感，通过将施加到接近正极母排的上桥功率半导体芯片的源极与门极信号晚于其他上桥功率半导体芯片，来达到延迟的目的，而无需使用特殊的延迟电路。此外，三相母排附近下桥功率半导体芯片的源极与门极信号晚于其他下桥功率半导体芯片，因此大电流不会瞬间集中在三相母排附近的下桥功率半导体芯片上流动。另外，通过在覆铜陶瓷基板上分别设置长铜板形式的上桥覆铜纹路和下桥覆铜纹路，并且在上桥覆铜纹路和下桥覆铜纹路上分别配置上桥功率半导体芯片和下桥功率半导体芯片，从而在功率半导体芯片之间形成大电感，可以抑制功率半导体芯片导通时瞬间大幅度流动的电流。
如图6所示，本结构适用于在覆铜陶瓷基板4一侧设有正极母排1和负极母排2、在另一侧设有三相母排5，并且每相并联有四个或更多个功率半导体芯片的功率模块，以承载大电流流过。
图7是产生三相交流电的功率半导体模块中的一相，有六个功率半导体芯片并联的示意图，上桥功率半导体芯片a1、a2、a3、a4、a5、a6分别设置在覆铜陶瓷基板两侧的两列覆铜纹路41上，两列覆铜纹路41之间连接正极母排1；下桥功率半导体芯片b1、b2、b3、b4、b5、b6分别设置在覆铜陶瓷基板中部的两列覆铜纹路42上，两列覆铜纹路42之间连接三相母排5。
如图8所示，上桥功率半导体芯片a1、a2、a3、a4、a5、a6分别设于覆铜陶瓷基板表面的两列覆铜纹路41上,正极母排1与两列覆铜纹路41相连，正极母排1流入的电流，在上桥功率半导体芯片所在的覆铜纹路41上分流,然后汇入三相母排5。如图9所示，下桥功率半导体芯片b1、b2、b3、b4、b5、b6分别设于覆铜陶瓷基板表面中部的两列覆铜纹路42上,三相母排5与两列覆铜纹路42相连，三相母排5流入的电流，在下桥功率半导体芯片所在的覆铜纹路42上分流,然后汇入负极母排2，电流被分成两部分，可以减少单个功率半导体芯片集中通过的电流。此外，通过将电流路径一分为二，可以拉长功率半导体芯片之间的距离，增加电感，从而抑制在功率模块导通时瞬间大幅度流动的电流。
此外，图10是图7所示的等效电路。在连接上桥和下桥的各功率半导体芯片的门极信号中，产生由门极信号线的长度形成的电感Lgt和Lgu。 此外，在正极母排1与上桥功率半导体芯片之间，以及上桥功率半导体芯片之间，产生由覆铜陶瓷基板上的铜板宽度、长度和厚度形成的电感Ldt和Ldu。
传输到上桥功率半导体芯片的门极信号Vgt从距离最远的上桥功率半导体芯片依次连接到正极母排1。即最靠近正极母排1的上桥功率半导体芯片a1、a4与其他上桥功率半导体芯片相比，对门极信号的累积电感最大，因此可以延迟开管时间，并且在上桥导通之后可以立即延迟流经上桥功率半导体芯片a1、a4的电流。另外，传输到下桥功率半导体芯片的门极信号Vgu从接近三相母排5的功率半导体芯片依次连接。即最接近三相母排5的下桥功率半导体芯片b3、b6与其他下桥功率半导体芯片相比，到门极信号的累积电感最大，因此能够延迟开管时间，使流向下桥功率半导体芯片的电流得到延迟。
同时，功率半导体芯片之间的电感Ldt和Ldu，可以抑制在功率半导体芯片导通时瞬间大幅度流入功率半导体芯片的电流。如图11所示为电感L和电阻R的串联电路，电感L表示功率半导体芯片之间的电感，电阻R表示功率半导体芯片导通的电阻，在该电路中，当开关K 导通时瞬间产生的电流 i (t) 如下式所示。
Figure DEST_PATH_IMAGE002
即，当电感较大时，即使施加电压E，电流i(t)也不会立即流通。根据该原理，通过应用本结构，每个功率半导体芯片中的电流可以达到逐渐增大的效果，以此来减轻电流集中的影响。
本结构通过覆铜陶瓷基板的覆铜纹路设计以及邦定线连接,增加功率半导体芯片源极与门极回路信号线的长度,调整各功率半导体芯片的开管时间,确保各功率半导体芯片开管的一致性，从而实现均流特性,保证功率半导体模块的开管可靠性。

Claims (6)

1.一种基于覆铜陶瓷基板布置的功率半导体模块结构，包括散热器、塑壳、覆铜陶瓷基板、正极母排、负极母排、三相母排、邦定线、若干上桥功率半导体芯片和若干下桥功率半导体芯片，所述覆铜陶瓷基板设于所述散热器表面，所述塑壳设于所述散热器并且包覆所述覆铜陶瓷基板，其特征在于：所述覆铜陶瓷基板分别设有上桥源极PIN针、上桥门极PIN针和下桥源极PIN针、下桥门极PIN针，所述覆铜陶瓷基板两侧分别设有连通的上桥覆铜纹路、中部间隔设于两列下桥覆铜纹路，所述若干上桥功率半导体芯片分别间隔设于所述上桥覆铜纹路，所述若干下桥功率半导体芯片分别间隔设于所述下桥覆铜纹路，所述正极母排连接所述上桥覆铜纹路并且正极母排电流经所述覆铜陶瓷基板两侧的上桥覆铜纹路分流后汇入所述三相母排，所述三相母排连接所述覆铜陶瓷基板中部的两列下桥覆铜纹路并且三相母排经两列下桥覆铜纹路分流后汇入所述负极母排，所述若干上桥功率半导体芯片的源极通过所述邦定线依次串联后连接所述上桥源极PIN针，所述若干下桥功率半导体芯片的源极通过所述邦定线依次串联后连接所述下桥源极PIN针，所述若干上桥功率半导体芯片的门极通过所述邦定线连接所述上桥门极PIN针，所述若干下桥功率半导体芯片的门极通过所述邦定线连接所述下桥门极PIN针。
2.根据权利要求1所述的基于覆铜陶瓷基板布置的功率半导体模块结构，其特征在于：所述覆铜陶瓷基板两侧的上桥覆铜纹路在相邻上桥功率半导体芯片之间设有突起浮铜接点，所述若干上桥功率半导体芯片的源极通过所述邦定线连接所述突起浮铜接点实现串联连接。
3.根据权利要求1或2所述的基于覆铜陶瓷基板布置的功率半导体模块结构，其特征在于：所述若干上桥功率半导体芯片在所述上桥覆铜纹路上相邻芯片的间距至少大于或等于芯片最小边长的一半，并且所述覆铜陶瓷基板表面的覆铜厚度为0.3～0.8mm。
4.根据权利要求3所述的基于覆铜陶瓷基板布置的功率半导体模块结构，其特征在于：所述上桥源极PIN针与上桥门极PIN针之间的控制信号和所述下桥源极PIN针与下桥门极PIN针之间的控制信号从外部输入，所述上桥源极PIN针和上桥门极PIN针在所述覆铜陶瓷基板上的位置位于距离所述正极母排最远的上桥功率半导体芯片外侧，所述下桥源极PIN针和下桥门极PIN针在所述覆铜陶瓷基板上的位置位于距离所述三相母排最远的下桥功率半导体芯片外侧。
5.根据权利要求3所述的基于覆铜陶瓷基板布置的功率半导体模块结构，其特征在于：所述若干上桥功率半导体芯片中各芯片中心距所述正极母排与上桥源极PIN针距离之和相等，并且距离所述正极母排最近的上桥功率半导体芯片距离所述上桥源极PIN针最远，距离所述正极母排最远的上桥功率半导体芯片距离所述上桥源极PIN针最近，所述若干下桥功率半导体芯片中各芯片中心距所述三相母排与下桥源极PIN针距离之和相等，并且距离所述三相母排最近的下桥功率半导体芯片距离所述下桥源极PIN针最远，距离所述三相母排最远的下桥功率半导体芯片距离所述下桥源极PIN针最近。
6.根据权利要求1所述的基于覆铜陶瓷基板布置的功率半导体模块结构，其特征在于：所述若干上桥功率半导体芯片和若干下桥功率半导体芯片分别为并联的至少四个功率半导体芯片。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115513163A (zh) * 2022-09-28 2022-12-23 上海海姆希科半导体有限公司 功率模块正负母排的优化结构

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170133332A1 (en) * 2012-10-31 2017-05-11 Delta Electronics (Shanghai) Co., Ltd Power integrated module
CN111566927A (zh) * 2018-03-08 2020-08-21 重庆金康新能源汽车有限公司 用于电动车辆驱动系统的功率转换器
CN113295913A (zh) * 2021-05-28 2021-08-24 正海集团有限公司 集成电流传感器的功率模块结构
CN217035630U (zh) * 2021-10-12 2022-07-22 正海集团有限公司 基于覆铜陶瓷基板布置的功率半导体模块结构
CN115132711A (zh) * 2022-05-28 2022-09-30 上海正海世鲲半导体有限公司 基于覆铜陶瓷基板的功率半导体模块结构
CN115733334A (zh) * 2022-11-08 2023-03-03 上海海姆希科半导体有限公司 功率半导体模块中覆铜陶瓷基板的优化结构

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170133332A1 (en) * 2012-10-31 2017-05-11 Delta Electronics (Shanghai) Co., Ltd Power integrated module
CN111566927A (zh) * 2018-03-08 2020-08-21 重庆金康新能源汽车有限公司 用于电动车辆驱动系统的功率转换器
CN113295913A (zh) * 2021-05-28 2021-08-24 正海集团有限公司 集成电流传感器的功率模块结构
CN217035630U (zh) * 2021-10-12 2022-07-22 正海集团有限公司 基于覆铜陶瓷基板布置的功率半导体模块结构
CN115132711A (zh) * 2022-05-28 2022-09-30 上海正海世鲲半导体有限公司 基于覆铜陶瓷基板的功率半导体模块结构
CN115733334A (zh) * 2022-11-08 2023-03-03 上海海姆希科半导体有限公司 功率半导体模块中覆铜陶瓷基板的优化结构

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115513163A (zh) * 2022-09-28 2022-12-23 上海海姆希科半导体有限公司 功率模块正负母排的优化结构

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