CN113985387B - Laser radar front end receiving circuit and intensity information compensation method - Google Patents
Laser radar front end receiving circuit and intensity information compensation method Download PDFInfo
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/48—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S17/00
- G01S7/483—Details of pulse systems
- G01S7/486—Receivers
- G01S7/4861—Circuits for detection, sampling, integration or read-out
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/48—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S17/00
- G01S7/483—Details of pulse systems
- G01S7/486—Receivers
- G01S7/4865—Time delay measurement, e.g. time-of-flight measurement, time of arrival measurement or determining the exact position of a peak
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/48—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S17/00
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Abstract
The invention relates to a laser radar front end receiving circuit and an intensity information compensation method, comprising the following steps: the device comprises an analog front-end circuit and a distance and intensity information acquisition unit, wherein the analog front-end circuit is used for receiving a photocurrent signal reflected by a detection target and a reset signal generated by a signal processing and control unit and outputting a rising edge moment identification signal, a falling edge moment identification signal and an amplitude signal; the input end of the distance and intensity information acquisition unit is electrically connected with the output end of the analog front-end circuit, receives the rising edge moment identification signal, the falling edge moment identification signal, the amplitude signal, the reference clock signal and the starting signal generated by the signal processing and control unit, and outputs first laser pulse flight time information, second laser pulse flight time information and pulse amplitude information. The laser radar front-end receiving circuit can output distance information and intensity information simultaneously under the condition that a high-speed analog-to-digital converter is not needed, and the cost and design complexity of the whole laser radar front-end receiving circuit are effectively reduced.
Description
Technical Field
The invention belongs to the technical field of laser radar optical signal receiver systems, and particularly relates to a laser radar front-end receiving circuit and an intensity information compensation method.
Background
The laser radar is widely applied to the fields of geographic mapping, spacecraft navigation, unmanned aerial vehicle detection and the like based on the specific three-dimensional imaging capability of the laser radar through continuous development from the initial military applications of laser ranging, laser guidance and the like. The development of three-dimensional imaging lidar has undergone an overall evolution from single-point, multi-channel line-scan to array. Because the traditional laser radar is limited by factors such as volume, cost, power consumption and the like, the large-scale application is difficult to realize in the civil fields such as automatic driving and the like. In lidar systems, the front-end analog circuitry constrains the overall performance of the system. High-performance, fully integrated laser radar front-end analog circuits have become an important development in the field of laser radar research.
Lidar systems generally consist of a laser emitting unit, an optical system and a receiving unit. Compared with a single photon detection laser radar, the linear mode laser radar can realize intensity information detection, and is beneficial to improving the target object recognition capability. The traditional linear mode laser radar needs to sample the output of a transimpedance amplifier through an analog-to-digital converter (ADC) so as to realize intensity information detection, and the sampling rate of the analog-to-digital converter has very high requirements, so that the cost of the whole system is difficult to reduce. Meanwhile, the dynamic range of the transimpedance amplifier circuit is generally small, so that the dynamic range of the receiving unit capable of simultaneously acquiring the intensity and distance information is limited by the front-end amplifying circuit.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a laser radar front-end receiving circuit and an intensity information compensation method. The technical problems to be solved by the invention are realized by the following technical scheme:
The embodiment of the invention provides a laser radar front-end receiving circuit based on intensity information compensation, which comprises: analog front-end circuitry and a distance and intensity information acquisition unit, wherein,
The analog front-end circuit is used for receiving a photocurrent signal reflected by a detection target and a reset signal generated by the signal processing and control unit, converting and amplifying the photocurrent signal, carrying out echo moment discrimination and amplitude information monitoring according to the converted and amplified signal, and outputting a rising edge moment discrimination signal, a falling edge moment discrimination signal and an amplitude signal;
The distance and intensity information acquisition unit is electrically connected with the output end of the analog front-end circuit, and is used for receiving the rising edge moment identification signal, the falling edge moment identification signal, the amplitude signal, the reference clock signal and the starting signal generated by the signal processing and control unit, performing time information conversion on the rising edge moment identification signal and the falling edge moment identification signal according to the starting signal and the reference clock signal, outputting first laser pulse flight time information and second laser pulse flight time information, performing data conversion on the amplitude signal and outputting pulse amplitude information.
In one embodiment of the invention, the analog front-end circuit comprises an amplifier unit, a time discrimination unit, a peak sample-and-hold circuit, and a unity gain buffer, wherein,
The input end of the amplifier unit inputs the photocurrent signal and the common mode signal, the in-phase voltage signal output end outputs an in-phase voltage signal and is electrically connected with the in-phase input end of the moment discriminating unit and the first input end of the peak value sampling and holding circuit, and the reverse voltage signal output end outputs an opposite-phase voltage signal;
The inverting input end of the moment identification unit inputs a threshold voltage signal, the first output end outputs the rising edge moment identification signal, and the second output end outputs the falling edge moment identification signal;
The second input end of the peak value sampling hold circuit inputs the reset signal, and the output end is electrically connected with the non-inverting input end of the unit gain buffer;
The output end of the unit gain buffer is electrically connected with the inverting input end of the unit gain buffer and outputs the amplitude signal.
In one embodiment of the invention, the amplifier unit comprises a first amplifier, a subsequent amplifier, a first resistor, a first capacitor and a second resistor, wherein,
The first resistor is connected between the input end and the output end of the first amplifier in a bridging way;
The input end of the first amplifier inputs the photocurrent signal, and the output end of the first amplifier is electrically connected with one end of the first capacitor;
The other end of the first capacitor is electrically connected with the first input end of the rear-stage amplifier and one end of the second resistor, the other end of the second resistor is electrically connected with the second input end of the rear-stage amplifier, and the second input end of the rear-stage amplifier inputs the common mode signal;
The first output end of the rear-stage amplifier is electrically connected with the non-inverting input end of the moment identification unit and the first input end of the peak value sampling and holding circuit, and the second output end of the rear-stage amplifier outputs the inverted voltage signal.
In one embodiment of the present invention, the distance and intensity information acquisition unit includes an intensity information conversion unit and a distance information conversion unit, wherein,
The input end of the intensity information conversion unit inputs the rising edge moment identification signal, the reference clock signal, the amplitude signal, the reference voltage and the common mode voltage of the integrator, and the output end is electrically connected with the input end of the distance information conversion unit;
The input end of the distance information conversion unit is further electrically connected with the first output end and the second output end of the moment identification unit, the reference clock signal and the start signal are further input into the input end of the distance information conversion unit, and the output end of the distance information conversion unit outputs the first laser pulse flight time information, the second laser pulse flight time information and the pulse amplitude information.
In one embodiment of the present invention, the intensity information converting unit includes an n1+1 stage D flip-flop, a first exclusive-or gate, a buffer, a first switch, a second switch, a third resistor, a second amplifier, a second capacitor, a reset signal switch, and a comparator, wherein,
The clock ends in the N1 +1-stage D flip-flops are all input with the reference clock signal, the data end of the first-stage D flip-flop in the N1 +1-stage D flip-flops is input with the rising edge moment identification signal, the output end of the N1-stage D flip-flop in the N1 +1-stage D flip-flops is electrically connected with the data end of the N1 +1-stage D flip-flop, the output end of the N1 +1-stage D flip-flop is electrically connected with the first input end of the first exclusive-OR gate and the input end of the buffer, and the second input end of the first exclusive-OR gate is electrically connected with the output end of the first-stage D flip-flop;
The output end of the first exclusive-or gate is electrically connected with the control end of the first switch, one end of the first switch is used for inputting the amplitude signal, the other end of the first switch is electrically connected with one end of the third resistor, the other end of the third resistor is electrically connected with the inverting input end of the second amplifier, the non-inverting input end of the second amplifier is used for inputting the common-mode voltage of the integrator, and the second capacitor and the reset signal switch are connected between the inverting input end of the second amplifier and the output end of the second amplifier in parallel;
The output end of the buffer is electrically connected with the first input end of the distance information conversion unit and the control end of the second switch, one end of the second switch inputs the reference voltage, and the other end of the second switch is electrically connected with one end of the third resistor;
the output end of the second amplifier is electrically connected with the non-inverting input end of the comparator, the inverting input end of the comparator inputs the common mode voltage of the integrator, and the output end of the comparator is electrically connected with the second input end of the distance information conversion unit.
In one embodiment of the present invention, the distance information converting unit includes a data integrating unit, an integer bit time information converting unit, and a decimal place time information converting unit, wherein,
The input end of the data integration unit is electrically connected with the output end of the buffer, the output end of the comparator, the first output end of the moment identification unit and the second output end of the moment identification unit; the output end of the data integration unit is electrically connected with the input end of the integer bit time information conversion unit and the input end of the decimal bit time information conversion unit;
the input end of the integer bit time information conversion unit is also input with the start signal and the reference clock signal, and the output end of the integer bit time information conversion unit outputs integer bit time information and clock signals with different phases;
the input end of the decimal time information conversion unit is electrically connected with the output end of the integer time information conversion unit so as to receive the clock signals with different phases, and the output end outputs decimal time information.
In one embodiment of the present invention, the data integration unit includes a second exclusive-or gate, a third exclusive-or gate, and a fourth exclusive-or gate, wherein,
The first input end of the second exclusive-OR gate is electrically connected with the output end of the buffer, the second input end of the second exclusive-OR gate is electrically connected with the output end of the comparator, and the output end of the second exclusive-OR gate is electrically connected with the first input end of the fourth exclusive-OR gate;
the first input end of the third exclusive-or gate is electrically connected with the first output end of the moment identification unit, the second input end of the third exclusive-or gate is electrically connected with the second output end of the moment identification unit, and the output end of the third exclusive-or gate is electrically connected with the second input end of the fourth exclusive-or gate;
the output end of the fourth exclusive-or gate is electrically connected with the input end of the integer bit time information conversion unit and the input end of the decimal bit time information conversion unit.
In one embodiment of the invention, the integer bit time information conversion unit comprises a counter, a phase detector and charge pump unit, an input buffer, an N2-stage voltage controlled delay buffer (N2. Gtoreq.1) and a loop filter capacitor, wherein,
The first input end of the counter is electrically connected with the output end of the fourth exclusive-OR gate, the second input end inputs the starting signal, and the output end outputs the integer bit time information;
The input end of the input buffer inputs the reference clock signal, and the output end is electrically connected with the clock end of the counter, the first input end of the phase discriminator and charge pump unit and the input end of a first stage voltage-controlled delay buffer in the N2 stage voltage-controlled delay buffer;
the N2-stage voltage-controlled delay buffers are sequentially and serially cascaded, and the output end of the N2-stage voltage-controlled delay buffer is electrically connected with the second input ends of the phase discriminator and the charge pump unit;
the output ends of the phase discriminator and the charge pump unit are electrically connected with one end of the loop filter capacitor and the voltage control end of each voltage-controlled delay buffer in the N2-stage voltage-controlled delay buffers, and the other end of the loop filter capacitor is grounded;
the output end of the N2-stage voltage-controlled delay buffer outputs N2 clock signals with different phases, and the output end of each stage of voltage-controlled delay buffer is electrically connected with the input end of the decimal time information conversion unit.
In one embodiment of the present invention, the decimal time information converting unit includes N2D flip-flops (N2. Gtoreq.1), N2 exclusive OR gates (N2. Gtoreq.1) and a decoding circuit, wherein,
The data end of each D trigger in the N2D triggers is electrically connected with the output end of the fourth exclusive-OR gate, and the clock ends of the N2D triggers are electrically connected with the output ends of the N2-stage voltage-controlled delay buffers in a one-to-one correspondence manner;
The output end of each D trigger in the N2D triggers is electrically connected with the first input end of each of the N2 exclusive-OR gates in a one-to-one correspondence manner, the output ends of the 2 nd D triggers to the N2D triggers are also electrically connected with the second input ends of the first exclusive-OR gate to the N2-1 exclusive-OR gate in a one-to-one correspondence manner, and the output end of the 1 st D trigger is also electrically connected with the second input end of the last exclusive-OR gate in the N2 exclusive-OR gates;
The output end of each of the N2 exclusive-OR gates is electrically connected with the input end of the decoding circuit, and the output end of the decoding circuit outputs the decimal time information.
Another embodiment of the present invention provides a method for compensating intensity information based on a laser radar front-end receiving circuit, which is used for the laser radar front-end receiving circuit according to the above embodiment, and includes the steps of:
S1, measuring pulse width information output by an amplifier unit according to input current amplitude values of different photocurrent signals to obtain the relation between the input current amplitude values and the pulse width information;
s2, based on the relation between the input current amplitude value and the pulse width information, compensating by using an interpolation method to obtain an intensity information compensation curve;
and S3, reversely pushing the target input current amplitude value according to the target pulse width information when the output of the amplifier unit is saturated by utilizing the intensity information compensation curve.
Compared with the prior art, the invention has the beneficial effects that:
1. The laser radar front-end receiving circuit can output distance information and intensity information at the same time under the condition of not needing a high-speed analog-to-digital converter, and effectively reduces the cost and design complexity of the whole laser radar front-end receiving circuit.
2. The invention is based on the intensity information compensation method of the laser radar front end receiving circuit, so that the dynamic range of the receiving unit for simultaneously acquiring the intensity and distance information is not limited by the front end amplifying circuit, and the intensity information acquisition can be realized in a larger dynamic range.
Drawings
Fig. 1 is a schematic structural diagram of a laser radar front end receiving circuit based on intensity information compensation according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of an analog front-end circuit according to an embodiment of the present invention;
Fig. 3 is a schematic circuit diagram of a distance and intensity information obtaining unit according to an embodiment of the present invention;
Fig. 4 is a schematic circuit diagram of an intensity information conversion unit according to an embodiment of the present invention;
Fig. 5 is a schematic circuit diagram of a distance information conversion unit according to an embodiment of the present invention;
FIG. 6 is a flowchart of a method for compensating intensity information according to an embodiment of the present invention;
fig. 7 is a working timing diagram of a laser radar front-end receiving circuit based on intensity information compensation according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but embodiments of the present invention are not limited thereto.
Example 1
Referring to fig. 1, fig. 1 is a schematic structural diagram of a laser radar front-end receiving circuit based on intensity information compensation according to an embodiment of the present invention. The laser radar front end receiving circuit 100 is a laser radar front end receiving circuit based on a feedback structure front end transimpedance amplifier, which receives a photocurrent signal i_in reflected by a detection target and transmitted through an optical lens, a reference clock signal CLK, and a reset signal RST and a Start signal Start generated by a signal processing and control unit, and processes these signals to output laser pulse flight time information and pulse amplitude information (i.e., intensity information) to the signal processing and control unit.
The laser radar front-end receiving circuit 100 includes an analog front-end circuit 110 and a distance and intensity information acquiring unit 120. Wherein,
The analog front-end circuit 110 is configured to receive a photocurrent signal i_in reflected by a detection target and a reset signal RST generated by the signal processing and control unit, where the reset signal RST is a reset signal of the peak sample-and-hold circuit, and is IN a synchronous relationship with a laser repetition frequency signal; the analog front-end circuit 110 converts and amplifies the optical current signal i_in, and performs echo time discrimination and amplitude information monitoring according to the converted and amplified signal, and outputs a rising edge time discrimination signal stop_r, a falling edge time discrimination signal stop_f and an amplitude signal V PEAK, wherein the rising edge time discrimination signal stop_r, the falling edge time discrimination signal stop_f represent echo distance information, and the amplitude signal V PEAK represents echo intensity information.
The input end of the distance and intensity information acquisition unit 120 is electrically connected with the output end of the analog front-end circuit 110; the distance and intensity information obtaining unit 120 is configured to receive a rising edge time discrimination signal stop_r, a falling edge time discrimination signal stop_f, an amplitude signal V PEAK, a reference clock signal CLK, and a Start signal Start generated by the signal processing and control unit, where the Start signal Start generated by the control unit represents emission time information of the laser pulse; the distance and intensity information acquiring unit 120 performs time information conversion on the rising edge time discrimination signal stop_r and the falling edge time discrimination signal stop_f according to the Start signal Start and the reference clock signal CLK, outputs first laser pulse flight time information and second laser pulse flight time information, performs data conversion on the amplitude signal V PEAK, and outputs pulse amplitude information. The pulse amplitude information is the output intensity information; the first laser pulse flight time information is time interval information between the rising edge time discrimination signal stop_r and the Start signal Start, which represents distance information output by the distance and intensity information acquisition unit 120; the second laser pulse flight time information is time interval information between the falling edge time identification signal stop_f and the Start signal Start, and a difference value between the second laser pulse flight time information and the first laser pulse flight time information is pulse width information.
Referring to fig. 2, fig. 2 is a schematic structural diagram of an analog front-end circuit according to an embodiment of the invention. The analog front-end circuit 110 includes an amplifier unit 111, a time discrimination unit 112, a peak sample-and-hold circuit 113, and a unit gain buffer 114. Wherein,
The input end of the amplifier unit 111 inputs a photocurrent signal i_in and a common mode signal V COM, the IN-phase voltage signal output end outputs an IN-phase voltage signal V OP and is electrically connected with the IN-phase input end of the time discrimination unit 112 and the first input end of the peak sample-and-hold circuit 113, and the reverse voltage signal output end outputs an anti-phase voltage signal V ON; specifically, the output terminals of the amplifier unit 111 simultaneously output differential voltage signals: the in-phase voltage signal V OP and the anti-phase voltage signal V ON, the in-phase voltage signal V OP is input from the in-phase input terminal of the time discrimination unit 112 and the first input terminal of the peak sample-and-hold circuit 113. The time discrimination unit 112 has an inverting input terminal to which the threshold voltage signal V TH is input, a first output terminal to which the rising edge time discrimination signal stop_r is output, and a second output terminal to which the falling edge time discrimination signal stop_f is output. A second input terminal of the peak sample-and-hold circuit 113 receives the reset signal RST, and an output terminal thereof is electrically connected to a non-inverting input terminal of the unity gain buffer 114. The output of the unity gain buffer 114 is electrically connected to its inverting input and outputs an amplitude signal V PEAK.
Specifically, the amplifier unit 111 includes a first amplifier-Av, a subsequent amplifier a 2, a first resistor R F, a first capacitor C 1, and a second resistor R 1, wherein the first amplifier-Av and the first resistor R F together form a transimpedance amplifier.
Wherein a first resistor R F is connected across the input and output of the first amplifier-Av. The input terminal of the first amplifier-Av inputs the photocurrent signal i_in, and the output terminal is electrically connected to one terminal of the first capacitor C 1. The other end of the first capacitor C 1 is electrically connected to the first input terminal of the post-stage amplifier a 2 and one end of the second resistor R 1, the other end of the second resistor R 1 is electrically connected to the second input terminal of the post-stage amplifier a 2, and the second input terminal of the post-stage amplifier a 2 inputs the common mode signal V COM. The first output terminal of the post-stage amplifier a 2 is electrically connected to the non-inverting input terminal of the time discrimination unit 112 and the first input terminal of the peak sample-and-hold circuit 113, and the second output terminal of the post-stage amplifier a 2 outputs the inverted voltage signal V ON.
Specifically, the output signal of the transimpedance amplifier is input into the post-stage amplifier a 2 through the ac coupling of the first capacitor C 1; the post-stage amplifier a 2 simultaneously outputs a differential voltage signal: an in-phase voltage signal V OP and an opposite-phase voltage signal V ON, where V OP is input to the timing discrimination unit 112 and the peak sample-and-hold circuit 113.
Referring to fig. 3, fig. 3 is a schematic circuit diagram of a distance and intensity information obtaining unit according to an embodiment of the present invention. The distance and intensity information acquisition unit 120 includes an intensity information conversion unit 121 and a distance information conversion unit 122.
The input end of the intensity information conversion unit 121 inputs the rising edge time discrimination signal stop_r, the reference clock signal CLK, the amplitude signal V PEAK, the reference voltage V N, and the integrator common mode voltage V CM, and the output end is electrically connected to the input end of the distance information conversion unit 122. The Start signal Start, the reference clock signal CLK, the rising edge timing discrimination signal stop_r, and the falling edge timing discrimination signal stop_f are also input to the input terminal of the distance information conversion unit 122, and the output terminal of the distance information conversion unit 122 outputs the first laser pulse time of flight information, the second laser pulse time of flight information, and the pulse amplitude information, wherein the information output by the distance information conversion unit 122 is composed of an integer bit output and a decimal bit output, the integer bit output includes integer digits of the first laser pulse time of flight information, the second laser pulse time of flight information, and the pulse amplitude information, and the decimal bit output includes decimal digits of the first laser pulse time of flight information, the second laser pulse time of flight information, and the pulse amplitude information.
That is, the input terminal of the intensity information conversion unit 121 is electrically connected to the first output terminal of the time discrimination unit 112, the output terminal of the reference clock signal CLK of the signal processing and control unit, the output terminal of the unity gain buffer 114, the output terminal of the reference voltage V N, and the output terminal of the integrator common mode voltage V CM, and then the second time information S 2 and the third time information S 3 are output into the distance information conversion unit 122. The input terminal of the distance information conversion unit 122 inputs the second time information S 2 and the third time information S 3, and is also electrically connected to the first output terminal and the second output terminal of the time discrimination unit 112, the output terminal of the reference clock signal CLK of the signal processing and control unit, and the output terminal of the Start signal Start of the signal processing and control unit, the distance information conversion unit 122 outputs the laser pulse flight time information and the pulse amplitude information.
Referring to fig. 4, fig. 4 is a schematic circuit diagram of an intensity information converting unit according to an embodiment of the invention. The intensity information converting unit 121 includes an n1+1 stage D flip-flop (n1≡1), a first exclusive-or gate, a buffer, a first switch S 1, a second switch S 2, a third resistor R 2, a second amplifier a 1, a second capacitor C 2, a reset signal switch RST, and a comparator CMP. Wherein,
The clock ends of the N1+1 stage D flip-flops are all input with a reference clock signal CLK, and the data end of the first stage D flip-flop of the N1+1 stage D flip-flop is electrically connected with the first output end of the time discrimination unit 112 to input a rising edge time discrimination signal stop_r; the output end of the N1-stage D trigger in the N1+ 1-stage D trigger is electrically connected with the data end of the N1+ 1-stage D trigger, namely the next-stage D trigger, the output end of the N1+ 1-stage D trigger is electrically connected with the first input end of the first exclusive-OR gate and the input end of the buffer, and the second input end of the first exclusive-OR gate is electrically connected with the output end of the first-stage D trigger.
The output end of the first exclusive-or gate outputs first time information S 1 and is electrically connected to the control end of the first switch S 1, and the first time information S 1 is used for controlling the first switch S 1; one end of the first switch S 1 is input with the amplitude signal V PEAK, the other end of the first switch S 1 is electrically connected with one end of the third resistor R 2, the other end of the third resistor R 2 is electrically connected with the inverting input end of the second amplifier a 1, the non-inverting input end of the second amplifier a 1 is input with the common-mode voltage V CM of the integrator, and the second capacitor C 2 and the reset signal switch RST are connected in parallel between the inverting input end of the second amplifier a 1 and the output end of the second amplifier a 1.
The output end of the buffer outputs the second time information S 2 and is electrically connected to the first input end of the distance information conversion unit 122 and the control end of the second switch S 2, the second time information S 2 is also used for controlling the second switch S 2 while being input to the distance information conversion unit 122, one end of the second switch S 2 inputs the reference voltage V N, and the other end of the second switch S 2 is electrically connected to one end of the third resistor R 2.
The output end of the second amplifier A 1 outputs a signal V INT, and the output end of the second amplifier A 1 is electrically connected with the non-inverting input end of the comparator CMP; an inverting input terminal of the comparator CMP inputs the integrator common mode voltage V CM, and an output terminal of the comparator CMP outputs the third time information S 3 and is electrically connected to a second input terminal of the distance information conversion unit 122 so that the third time information S 3 is input to the distance information conversion unit 122.
Referring to fig. 5, fig. 5 is a schematic circuit diagram of a distance information converting unit according to an embodiment of the invention. The distance information conversion unit 122 includes a data integration unit 1221, an integer bit time information conversion unit 1222, and a fractional bit time information conversion unit 1223. Wherein,
An input terminal of the data integration unit 1221 is electrically connected to an output terminal of the buffer, an output terminal of the comparator CMP, a first output terminal of the timing discrimination unit 112, and a second output terminal of the timing discrimination unit 112, to input the second timing information S 2, the third timing information S 3, the rising edge timing discrimination signal stop_r, and the falling edge timing discrimination signal stop_f, respectively; an output terminal of the data integration unit 1221 is electrically connected to an input terminal of the integer bit time information conversion unit and an input terminal of the fractional bit time information conversion unit to output a signal Tin value integer bit time information conversion unit 1122 and a fractional bit time information conversion unit 1123.
An input terminal of the integer-bit time information conversion unit 1222 inputs a Start signal Start and a reference clock signal CLK in addition to the input signal Tin, and an output terminal of the integer-bit time information conversion unit 1222 outputs integer-bit time information and different phase clock signals.
The input terminal of the fractional time information conversion unit 1223 is electrically connected to the output terminal of the integer time information conversion unit 1222 to receive clock signals of different phases, in addition to the Tin signal, and the output terminal of the fractional time information conversion unit 1223 outputs fractional time information.
In one embodiment, the data integration unit 1221 includes a second exclusive-or gate, a third exclusive-or gate, and a fourth exclusive-or gate.
The first input end of the second exclusive-or gate is electrically connected to the output end of the buffer to input the second time information S 2, the second input end of the second exclusive-or gate is electrically connected to the output end of the comparator CMP to input the third time information S 3, and the output end of the second exclusive-or gate is electrically connected to the first input end of the fourth exclusive-or gate. The first input terminal of the third exclusive-or gate is electrically connected to the first output terminal of the time discrimination unit 112 to input the rising edge time discrimination signal stop_r, the second input terminal is electrically connected to the second output terminal of the time discrimination unit 112 to input the falling edge time discrimination signal stop_f, and the output terminal is electrically connected to the second input terminal of the fourth exclusive-or gate. The output terminal of the fourth exclusive or gate outputs the signal Tin, and the output terminal thereof is electrically connected to the input terminal of the integer bit time information conversion unit 1222 and the input terminal of the fractional bit time information conversion unit 1223 so that the signal Tin is input to the integer bit time information conversion unit 1222 and the fractional bit time information conversion unit 1223.
In one embodiment, the integer bit time information conversion unit 1222 includes a counter, a phase detector and charge pump unit, an input buffer, an N2 stage voltage controlled delay buffer (N2. Gtoreq.1), and a loop filter capacitor C L.
The first input end of the counter is electrically connected with the output end of the fourth exclusive-OR gate to receive the signal Tin, the second input end inputs the Start signal Start, and the output end outputs the integral digital time information. The input end of the input buffer inputs the reference clock signal CLK, and the output end is electrically connected with the clock end of the counter, the first input end of the phase discriminator and charge pump unit and the input end of the first stage voltage-controlled delay buffer in the N2 stage voltage-controlled delay buffer. The N2-stage voltage-controlled delay buffers are sequentially and serially cascaded, and the output end of the N2-stage voltage-controlled delay buffer is electrically connected with the second input ends of the phase discriminator and the charge pump unit. The output ends of the phase discriminator and the charge pump unit output a control voltage signal V B, and are electrically connected with one end of the loop filter capacitor C L and the voltage control end of each voltage-controlled delay buffer in the N2-stage voltage-controlled delay buffers, the control voltage signal V B is used as the control voltage signal of the voltage-controlled delay buffers, and the other end of the loop filter capacitor C L is grounded. The output end of the N2-stage voltage-controlled delay buffer outputs N2 clock signals with different phases as the output end of the integer bit time information conversion unit 1222, and the output end of each stage of voltage-controlled delay buffer is electrically connected to the input end of the decimal bit time information conversion unit 1223.
In one embodiment, the fractional-time information conversion unit 1223 includes N2D flip-flops (N2. Gtoreq.1), N2 exclusive OR gates (N2. Gtoreq.1), and a decoding circuit.
The data end of each D trigger in the N2D triggers is electrically connected with the output end of the fourth exclusive-OR gate to receive signals Tin, and the clock ends of the N2D triggers are electrically connected with the output ends of the N2-stage voltage-controlled delay buffers in a one-to-one correspondence manner; the output end of each D trigger in the N2D triggers is electrically connected with the first input end of each of the N2 exclusive-OR gates in a one-to-one correspondence manner, the output ends of the 2 nd D trigger to the N2D trigger are also electrically connected with the second input ends of the first exclusive-OR gate to the N2-1 exclusive-OR gate in a one-to-one correspondence manner, and the output end of the 1 st D trigger is also electrically connected with the second input end of the last exclusive-OR gate in the N2 exclusive-OR gates. The output end of each of the N2 exclusive-OR gates is electrically connected with the input end of the decoding circuit, and the output end of the decoding circuit outputs decimal time information.
The laser radar front-end receiving circuit of the embodiment can output distance information and intensity information at the same time under the condition that a high-speed analog-to-digital converter is not needed, and therefore the cost and design complexity of the whole laser radar front-end receiving circuit are effectively reduced. Meanwhile, the time-to-digital conversion circuit (i.e., the distance information conversion unit 122) employed in the present embodiment can realize the time conversion function of a plurality of stop signals.
Referring to fig. 6, fig. 6 is a flowchart of a method for compensating intensity information according to an embodiment of the present invention. The intensity information compensation method is suitable for the laser radar front-end receiving circuit based on the feedback structure front-end transimpedance amplifier. After the output of the transimpedance amplifier of the feedback structure is saturated, the output of the peak sample-and-hold circuit 113 can only detect the saturated voltage of the amplifier unit 111, and cannot truly reflect the magnitude of the input photocurrent signal. Since the pulse width of the transimpedance amplifier output voltage signal is proportional to the amplitude value of the input photocurrent signal, the amplitude value of the input current, that is, the intensity information of the echo signal can be compensated by measuring the pulse width of the output voltage of the amplifier unit 111.
Specifically, the intensity information compensation method includes the steps of:
First, the pulse width information output from the amplifier unit 111 is measured for the input current amplitude values of the different photocurrent signals, and the relationship between the input current amplitude values and the pulse width information is obtained. Then, based on the relation between the input current amplitude value and the pulse width information, the intensity information compensation curve is obtained by utilizing an interpolation method to compensate. Finally, the intensity information compensation curve is utilized to reversely extrapolate the corresponding target input current amplitude value according to the target pulse width information when the amplifier unit 111 outputs saturation, and the intensity information of the echo signal is obtained.
According to the intensity information compensation method based on the laser radar front-end receiving circuit, the dynamic range of the receiving unit for simultaneously acquiring the intensity and distance information is not limited by the front-end amplifying circuit, and the intensity information acquisition can be realized in a larger dynamic range.
In order to explain the working principle of the laser radar front end receiving circuit based on intensity information compensation according to the present embodiment, the present embodiment further illustrates the function of acquiring the intensity and distance information of the laser radar front end receiving circuit based on the foregoing laser radar front end receiving circuit 100 and the intensity information compensation method, please refer to fig. 7, and fig. 7 is a working timing diagram of the laser radar front end receiving circuit based on intensity information compensation according to the embodiment of the present invention.
In particular, V OP may represent the detected echo signal, generating two stop signals at the threshold voltage of the comparator CMP, respectively: stop_r and stop_f represent the rising time and the falling time. Simultaneously, the reference clock signal CLK samples stop_r through an N1+1 level D trigger; the output of the first stage D flip-flop is exclusive-ored with the output of the N1+1st stage D flip-flop to generate first time information S 1 (S1 signal), and the pulse width of the S1 signal is N1 clock cycles; the output of the last stage D flip-flop is the second time information S 2 (S2 signal), i.e., the S2 signal is flipped up after the S1 signal becomes low.
For amplitude signal V PEAK, amplitude signal V PEAK is reset by reset signal RST before each laser emission cycle. After the laser echo pulse is detected, the amplitude signal V PEAK can output the peak voltage of the V OP signal and remain until the reset signal RST becomes high level. for the intensity information converting unit 121, the amplifier a 1, the third resistor R 2, and the second capacitor C 2 constitute an integrator. The reset signal RST resets the output signal V INT of the integrator before each laser emission period and to the integrator common mode signal V CM. At the stage where S 1 is high, the output V INT of the integrator decreases with the slope of V PEAK/(R1*C1); At low level S 1 and high level S 2, the output V INT of the integrator increases with the slope of V N/(R1*C1), until higher than the integrator common mode signal V CM, the comparator CPM output toggles and the S 3 signal goes high. Thus the amplitude signal V PEAK can be calculated from the phase difference of S 2 and S 3, i.e
Where S 3-S2 represents the phase difference between S 3 and S 2, τ CLK represents the period of the reference clock signal CLK. The amplitude signal V PEAK can thus be obtained by measuring the phase difference of S 3 and S 2. Therefore, the Tin signal contains distance information stop_r, stop_f, and intensity information (i.e., amplitude signal V PEAK). The converted time information stop_r and stop_f can be directly obtained by the distance information conversion unit 122, and the pulse width information is obtained by the external signal processing unit, so that the pulse width information is applied to the intensity information compensation method of fig. 6 to carry out intensity information compensation; and meanwhile, obtaining time information after the conversion of S 2 and S 3, and obtaining the phase difference of S 3 and S 2 through an external signal processing unit, so as to obtain the intensity information through calculation.
The laser radar front-end receiving circuit of the embodiment is based on a direct flight time method, adopts a peak value sampling and holding circuit and a double-slope analog-to-digital converter (namely, an intensity information acquisition unit 121) to acquire intensity information, adopts a front edge moment identification method to acquire distance information, and adopts a walking error and amplitude saturation error compensation method to respectively correct the distance information and the intensity information, so that the dynamic range of the circuit can be enlarged and the system cost can be reduced on the premise of acquiring the distance information and the intensity information at the same time.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.
Claims (8)
1. A laser radar front-end receiving circuit (100) based on intensity information compensation, characterized by comprising: an analog front-end circuit (110) and a distance and intensity information acquisition unit (120), wherein,
The analog front-end circuit (110) is used for receiving a photocurrent signal (I_IN) reflected by a detection target and a Reset Signal (RST) generated by the signal processing and control unit, converting and amplifying the photocurrent signal (I_IN), carrying out echo time discrimination and amplitude information monitoring according to the converted and amplified signal, and outputting a rising edge time discrimination signal (stop_r), a falling edge time discrimination signal (stop_f) and an amplitude signal (V PEAK);
the input end of the distance and intensity information acquisition unit (120) is electrically connected with the output end of the analog front-end circuit (110), the distance and intensity information acquisition unit (120) is used for receiving the rising edge moment identification signal (stop_r), the falling edge moment identification signal (stop_f), the amplitude signal (V PEAK), the reference clock signal (CLK) and the starting signal (Start) generated by the signal processing and controlling unit, performing time information conversion on the rising edge moment identification signal (stop_r) and the falling edge moment identification signal (stop_f) according to the starting signal (Start) and the reference clock signal (CLK), outputting first laser pulse flight time information and second laser pulse flight time information, performing data conversion on the amplitude signal (V PEAK) and outputting pulse amplitude information;
The analog front-end circuit (110) comprises an amplifier unit (111), a time discrimination unit (112), a peak value sampling and holding circuit (113) and a unit gain buffer (114), wherein the input end of the amplifier unit (111) inputs the photocurrent signal (I_IN) and a common mode signal (V COM), the IN-phase voltage signal output end of the amplifier unit outputs an IN-phase voltage signal (V OP) and is electrically connected with the IN-phase input end of the time discrimination unit (112) and the first input end of the peak value sampling and holding circuit (113), and the reverse voltage signal output end outputs an opposite-phase voltage signal (V ON); the inverting input end of the moment identification unit (112) inputs a threshold voltage signal (V TH), the first output end outputs the rising edge moment identification signal (stop_r), and the second output end outputs the falling edge moment identification signal (stop_f); a second input end of the peak value sampling hold circuit (113) inputs the Reset Signal (RST), and an output end of the peak value sampling hold circuit is electrically connected with a non-inverting input end of the unit gain buffer (114); the output end of the unit gain buffer (114) is electrically connected with the inverting input end of the unit gain buffer and outputs the amplitude signal (V PEAK);
The distance and intensity information acquisition unit (120) comprises an intensity information conversion unit (121) and a distance information conversion unit (122), wherein the input end of the intensity information conversion unit (121) inputs the rising edge moment identification signal (stop_r), the reference clock signal (CLK), the amplitude signal (V PEAK), the reference voltage (V N) and the integrator common mode voltage (V CM), and the output end is electrically connected with the input end of the distance information conversion unit (122); the input end of the distance information conversion unit (122) is further electrically connected with the first output end and the second output end of the time identification unit (112), the reference clock signal (CLK) and the Start signal (Start) are further input to the input end of the distance information conversion unit (122), and the output end of the distance information conversion unit (122) outputs the first laser pulse flight time information, the second laser pulse flight time information and the pulse amplitude information.
2. The laser radar front-end receiving circuit (100) based on intensity information compensation according to claim 1, wherein the amplifier unit (111) includes a first amplifier (-Av), a subsequent stage amplifier (a 2), a first resistor (R F), a first capacitor (C 1), and a second resistor (R 1), wherein,
The first resistor (R F) is connected across the input end and the output end of the first amplifier (-Av);
The input end of the first amplifier (-Av) inputs the photocurrent signal (I_IN), and the output end is electrically connected with one end of the first capacitor (C 1);
The other end of the first capacitor (C 1) is electrically connected with the first input end of the rear-stage amplifier (A 2) and one end of the second resistor (R 1), the other end of the second resistor (R 1) is electrically connected with the second input end of the rear-stage amplifier (A 2) and the second input end of the rear-stage amplifier (A 2) inputs the common-mode signal (V COM);
The first output end of the rear-stage amplifier (A 2) is electrically connected with the non-inverting input end of the moment identification unit (112) and the first input end of the peak value sampling and holding circuit (113), and the second output end of the rear-stage amplifier (A 2) outputs the inverted voltage signal (V ON).
3. The laser radar front-end receiving circuit (100) based on intensity information compensation according to claim 1, wherein the intensity information converting unit (121) comprises an n1+1 stage D flip-flop, a first exclusive-or gate, a buffer, a first switch (S 1), a second switch (S 2), a third resistor (R 2), a second amplifier (a 1), a second capacitor (C 2), a reset signal switch and a Comparator (CMP), wherein N1 is not less than 1,
The clock ends in the N1+1-stage D flip-flops are all input with the reference clock signal (CLK), the data end of the first-stage D flip-flop in the N1+1-stage D flip-flops is input with the rising edge moment identification signal (stop_r), the output end of the N1-stage D flip-flop in the N1+1-stage D flip-flops is electrically connected with the data end of the N1+1-stage D flip-flop, the output end of the N1+1-stage D flip-flop is electrically connected with the first input end of the first exclusive-OR gate and the input end of the buffer, and the second input end of the first exclusive-OR gate is electrically connected with the output end of the first-stage D flip-flop;
The output end of the first exclusive-or gate is electrically connected with the control end of the first switch (S 1), one end of the first switch (S 1) is input with the amplitude signal (V PEAK), the other end of the first switch (S 1) is electrically connected with one end of the third resistor (R 2), the other end of the third resistor (R 2) is electrically connected with the inverting input end of the second amplifier (a 1), the non-inverting input end of the second amplifier (a 1) is input with the common-mode voltage (V CM) of the integrator, and the second capacitor (C 2) and the reset signal switch are connected in parallel between the inverting input end of the second amplifier (a 1) and the output end of the second amplifier (a 1);
The output end of the buffer is electrically connected with the first input end of the distance information conversion unit (122) and the control end of the second switch (S 2), one end of the second switch (S 2) inputs the reference voltage (V N), and the other end of the second switch (S 2) is electrically connected with one end of the third resistor (R 2);
The output end of the second amplifier (A 1) is electrically connected with the non-inverting input end of the Comparator (CMP), the inverting input end of the Comparator (CMP) inputs the common-mode voltage (V CM) of the integrator, and the output end of the Comparator (CMP) is electrically connected with the second input end of the distance information conversion unit (122).
4. The laser radar front end receiving circuit (100) based on intensity information compensation according to claim 3, wherein the distance information converting unit (122) includes a data integrating unit (1221), an integer bit time information converting unit (1222), and a fractional bit time information converting unit (1223), wherein,
The input end of the data integration unit (1221) is electrically connected with the output end of the buffer, the output end of the Comparator (CMP), the first output end of the moment identification unit (112) and the second output end of the moment identification unit (112); the output end of the data integration unit (1221) is electrically connected with the input end of the integer bit time information conversion unit and the input end of the decimal bit time information conversion unit;
The input end of the integer bit time information conversion unit (1222) is also input with the Start signal (Start) and the reference clock signal (CLK), and the output end of the integer bit time information conversion unit (1222) outputs integer bit time information and clock signals with different phases;
An input end of the decimal time information converting unit (1223) is electrically connected with an output end of the integer time information converting unit (1222) to receive the clock signals with different phases, and the output end outputs decimal time information.
5. The laser radar front end receiving circuit (100) based on intensity information compensation according to claim 4, wherein the data integrating unit (1221) includes a second exclusive-or gate, a third exclusive-or gate, and a fourth exclusive-or gate, wherein,
The first input end of the second exclusive-OR gate is electrically connected with the output end of the buffer, the second input end of the second exclusive-OR gate is electrically connected with the output end of the Comparator (CMP), and the output end of the second exclusive-OR gate is electrically connected with the first input end of the fourth exclusive-OR gate;
the first input end of the third exclusive-OR gate is electrically connected with the first output end of the moment identification unit (112), the second input end of the third exclusive-OR gate is electrically connected with the second output end of the moment identification unit (112), and the output end of the third exclusive-OR gate is electrically connected with the second input end of the fourth exclusive-OR gate;
an output of the fourth exclusive-or gate is electrically connected to an input of the integer bit time information conversion unit (1222) and an input of the fractional bit time information conversion unit (1223).
6. The laser radar front-end receiving circuit (100) based on intensity information compensation according to claim 5, wherein said integer bit time information conversion unit (1222) comprises a counter, a phase detector and charge pump unit, an input buffer, an N2 stage voltage controlled delay buffer and a loop filter capacitor (C L), N2 being equal to or greater than 1,
The first input end of the counter is electrically connected with the output end of the fourth exclusive-OR gate, the second input end inputs the Start signal (Start), and the output end outputs the integer bit time information;
The input end of the input buffer inputs the reference clock signal (CLK), and the output end is electrically connected with the clock end of the counter, the first input ends of the phase discriminator and the charge pump unit and the input end of a first stage voltage-controlled delay buffer in the N2 stage voltage-controlled delay buffer;
the N2-stage voltage-controlled delay buffers are sequentially and serially cascaded, and the output end of the N2-stage voltage-controlled delay buffer is electrically connected with the second input ends of the phase discriminator and the charge pump unit;
The output ends of the phase discriminator and the charge pump unit are electrically connected with one end of the loop filter capacitor (C L) and the voltage control end of each voltage-controlled delay buffer in the N2-stage voltage-controlled delay buffers, and the other end of the loop filter capacitor (C L) is grounded;
the output end of the N2-stage voltage-controlled delay buffer outputs N2 clock signals with different phases, and the output end of each stage of voltage-controlled delay buffer is electrically connected with the input end of the decimal time information conversion unit.
7. The laser radar front end receiving circuit (100) based on intensity information compensation according to claim 6, wherein the decimal time information converting unit includes N2D flip-flops, N2 exclusive or gates, and a decoding circuit, N2 is 1 or more, wherein,
The data end of each D trigger in the N2D triggers is electrically connected with the output end of the fourth exclusive-OR gate, and the clock ends of the N2D triggers are electrically connected with the output ends of the N2-stage voltage-controlled delay buffers in a one-to-one correspondence manner;
The output end of each D trigger in the N2D triggers is electrically connected with the first input end of each of the N2 exclusive-OR gates in a one-to-one correspondence manner, the output ends of the 2 nd D triggers to the N2D triggers are also electrically connected with the second input ends of the first exclusive-OR gate to the N2-1 exclusive-OR gate in a one-to-one correspondence manner, and the output end of the 1 st D trigger is also electrically connected with the second input end of the last exclusive-OR gate in the N2 exclusive-OR gates;
The output end of each of the N2 exclusive-OR gates is electrically connected with the input end of the decoding circuit, and the output end of the decoding circuit outputs the decimal time information.
8. A method for compensating intensity information based on a laser radar front end receiving circuit, for a laser radar front end receiving circuit according to claims 1 to 7, comprising the steps of:
S1, measuring pulse width information output by an amplifier unit according to input current amplitude values of different photocurrent signals to obtain the relation between the input current amplitude values and the pulse width information;
s2, based on the relation between the input current amplitude value and the pulse width information, compensating by using an interpolation method to obtain an intensity information compensation curve;
and S3, reversely pushing the target input current amplitude value according to the target pulse width information when the output of the amplifier unit is saturated by utilizing the intensity information compensation curve.
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