CN111726179B - Received signal strength detection circuit and method - Google Patents

Received signal strength detection circuit and method Download PDF

Info

Publication number
CN111726179B
CN111726179B CN201910202591.3A CN201910202591A CN111726179B CN 111726179 B CN111726179 B CN 111726179B CN 201910202591 A CN201910202591 A CN 201910202591A CN 111726179 B CN111726179 B CN 111726179B
Authority
CN
China
Prior art keywords
signal
amplitude
frequency
output
ook
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201910202591.3A
Other languages
Chinese (zh)
Other versions
CN111726179A (en
Inventor
赵健
杨华中
刘勇攀
孙文钰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tsinghua University
Original Assignee
Tsinghua University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tsinghua University filed Critical Tsinghua University
Priority to CN201910202591.3A priority Critical patent/CN111726179B/en
Publication of CN111726179A publication Critical patent/CN111726179A/en
Application granted granted Critical
Publication of CN111726179B publication Critical patent/CN111726179B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B17/00—Monitoring; Testing
    • H04B17/30—Monitoring; Testing of propagation channels
    • H04B17/309—Measuring or estimating channel quality parameters
    • H04B17/318—Received signal strength

Abstract

The embodiment of the invention provides a received signal strength detection circuit and a method thereof, wherein the circuit comprises: the device comprises an OOK signal amplitude detection module for inhibiting ripples and a time domain analog-to-digital conversion module; the amplitude detection module of the ripple-suppressed OOK signal receives an OOK receiving signal, converts the OOK receiving signal into a direct-current analog amplitude signal, and suppresses alternating-current ripples in the conversion process; the time domain analog-to-digital conversion module converts the direct current analog amplitude signal into an amplitude frequency modulation signal, measures the frequency of the amplitude frequency modulation signal, and outputs a digital amplitude signal representing a measurement result. According to the embodiment of the invention, the amplitude of the OOK signal is sampled with high efficiency and high precision by the ripple-suppressed OOK signal amplitude detection module, the sampling ripple interference can be effectively reduced, the conversion from sampling voltage to frequency signal is realized by the time domain analog-to-digital conversion module, the low-frequency noise can be greatly suppressed, and the received signal intensity detection with ultra-low power consumption is realized.

Description

Received signal strength detection circuit and method
Technical Field
The embodiment of the invention relates to the technical field of wireless body area networks, in particular to a received signal strength detection circuit and a received signal strength detection method.
Background
In recent years, wireless body area network communication technology has attracted much attention and research in a system dedicated to wireless communication, which is a target of devices around a human body, such as a portable wristwatch, a sensor, a mobile phone, and the like, and implanted devices inside the human body. In a body area network receiver circuit, a Received Signal Strength Indication (RSSI) circuit can be used for estimating the Strength of a Received Signal, and further, a front-end adjustable gain amplification circuit is used for realizing closed-loop automatic gain control, and the RSSI circuit is one of key modules in the whole receiver link.
Because the wireless body area network transceiver has the limited conditions of small volume, limited node energy and the like, research aiming at the low-power consumption RSSI circuit is increasing. The low-power consumption RSSI circuit disclosed in the prior art adopts a form of cascade connection of multiple stages of limiting amplifiers, and each stage needs an RC low-pass filter circuit, so that the area cost is large and the performance is unstable. The current superposition principle is utilized to reduce the overall power consumption of the RSSI module, but the SAR-ADC is required to be utilized to carry out analog-digital conversion, so that the further reduction of the overall circuit power consumption is limited.
Therefore, it is desirable to provide a new RSSI circuit that can satisfy the low power consumption requirement of the wireless body area network receiver and has stable performance.
Disclosure of Invention
Embodiments of the present invention provide a received signal strength detection circuit and method that overcomes, or at least partially solves, the above-mentioned problems.
In a first aspect, an embodiment of the present invention provides a received signal strength detection circuit, including: the device comprises an OOK signal amplitude detection module for inhibiting ripples and a time domain analog-to-digital conversion module; wherein the content of the first and second substances,
the ripple-suppressed OOK signal amplitude detection module is configured to receive an OOK received signal, convert the OOK received signal into a dc analog amplitude signal according to the amplitude of the OOK received signal, suppress ac ripples during the conversion, and output the dc analog amplitude signal;
the time domain analog-to-digital conversion module is used for receiving the direct current analog amplitude signal, converting the direct current analog amplitude signal into an amplitude frequency modulation signal with amplitude changing along with the direct current analog amplitude signal, measuring the frequency of the amplitude frequency modulation signal and outputting a digital amplitude signal representing a measurement result.
In a second aspect, an embodiment of the present invention provides a method for detecting received signal strength, including:
receiving an OOK receiving signal, converting the OOK receiving signal into a direct current analog amplitude signal according to the amplitude of the OOK receiving signal, and inhibiting alternating current ripples in the conversion process;
and converting the direct current analog amplitude signal into an amplitude frequency modulation signal with the amplitude changing along with the direct current analog amplitude signal, measuring the frequency of the amplitude frequency modulation signal, and outputting a digital amplitude signal representing the measurement result.
According to the received signal strength detection circuit and method provided by the embodiment of the invention, the amplitude of the OOK signal is sampled by the OOK signal amplitude detection module with ripple suppression, the sampling ripple interference can be effectively reduced, high-efficiency and high-precision stable sampling is realized, the conversion from sampling voltage to frequency signal to digital signal is realized by the time domain analog-to-digital conversion module, the low-frequency noise can be greatly suppressed, and the received signal strength detection with ultra-low power consumption is realized.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a received signal strength detection circuit according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of an OOK signal amplitude detection module for suppressing ripple according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a sample using a conventional sampling technique;
FIG. 4 is a sample schematic of an embodiment of the invention;
fig. 5 is a schematic structural diagram of a time domain analog-to-digital conversion module according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a time domain analog-to-digital conversion module according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a time domain analog-to-digital conversion module according to an embodiment of the present invention;
fig. 8 is a flowchart illustrating a method for detecting a received signal strength according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Unless specifically stated otherwise, the terms "first," "second," "third," and the like, as used herein below and in the claims, are used merely to distinguish one element from another, and are not intended to limit any temporal or spatial order.
The received signal strength detection circuit provided by the embodiment of the invention is applied to a low-power-consumption wireless body area network receiver system, can realize high-efficiency and high-precision sampling of the received signal strength, and realizes digital conversion by a delta sigma principle. As shown in fig. 1, a schematic structural diagram of a received signal strength detection circuit provided in an embodiment of the present invention includes: the system comprises an OOK signal amplitude detection module 100 for ripple suppression and a time domain analog-to-digital conversion module 200; wherein the content of the first and second substances,
the ripple-suppressed OOK signal amplitude detection module 100 is configured to receive an OOK received signal, convert the OOK received signal into a dc analog amplitude signal according to the amplitude of the OOK received signal, suppress an ac ripple in the conversion process, and output the dc analog amplitude signal;
the time domain analog-to-digital conversion module 200 is configured to receive the dc analog amplitude signal, convert the dc analog amplitude signal into an amplitude frequency modulation signal whose amplitude changes with the dc analog amplitude signal, measure the frequency of the amplitude frequency modulation signal, and output a digital amplitude signal representing a measurement result.
Specifically, the OOK (On-Off Keying) reception signal refers to an On-Off Keying reception signalRipple-suppressed OOK signal amplitude detection module 100 receives OOK received signal SOOKThen receives a signal S according to the OOKOOKConverts the OOK received signal into a dc analog amplitude signal MaAC ripple is suppressed during the conversion.
The time domain analog-to-digital conversion module 200 is shown receiving the direct current analog amplitude signal M output by the ripple-suppressed OOK signal amplitude detection module 100aAnd converting it to frequency with MaVarying alternating current signal: amplitude frequency modulation signal MfFor amplitude modulated signal MfIs measured and a digital amplitude signal M representing the measurement result is outputdWill MdAs the output of the entire received signal strength detection circuit.
According to the received signal strength detection circuit provided by the embodiment of the invention, the amplitude of the OOK signal is stably sampled with high efficiency and high precision through the OOK signal amplitude detection module with ripple suppression, the sampling ripple interference can be effectively reduced, the conversion from the sampling voltage to the frequency signal and then to the digital signal is realized through the time domain analog-to-digital conversion module, the low-frequency noise can be greatly suppressed, and thus the received signal strength detection with ultra-low power consumption is realized.
On the basis of the foregoing embodiment, as shown in fig. 2, the ripple-suppressed OOK signal amplitude detection module 100 further includes: a first rectifying module 101, a second rectifying module 102, a first comparator 103, a second comparator 104, a first D flip-flop 105, a voltage buffer 106, a first resistor R1A second resistor R2A first capacitor C1And a second capacitor C2(ii) a Wherein the content of the first and second substances,
the first rectifying module 101 and the second rectifying module 102 are configured to perform square or absolute value operation on the OOK received signal, and output a current signal related to the amplitude of the OOK received signal;
wherein, the first rectification module 101 and the second rectification module 102 are both used for receiving an input voltage signal SOOKTo SOOKThe square or absolute value operation is carried out, and the current signal is converted into an output current signal, and two possible input and output functions are as follows:
irec＝k1|SOOK|
Figure BDA0001997917060000051
wherein k is1,k2Respectively the gain of the two input and output functions.
The output port of the first rectifying module 101 is connected to the first resistor R1And a first comparator 103, the first resistor R1For converting the current signal output by the first rectifying module 101 into a high-frequency rectified voltage signal SHThe first comparator 103 is used for rectifying a voltage signal S according to the high frequencyHGenerating a high frequency sampling signal SHs。
The output port of the second rectifying module 102 is connected to the second comparator 104 and the second resistor R2And a first capacitor C1A filter network for converting the current signal output by the second rectifying module 102 into a low-frequency rectified voltage signal SLThe second comparator 104 is used for rectifying the voltage signal S according to the low frequencyLGenerating a low frequency sampling signal SLs；
Wherein, the cut-off frequency of the filter network is:
Figure BDA0001997917060000052
wherein f isRCShould be less than OOK receive signal SOOKOf (c) is detected.
It should be noted that, in practical applications, the input ports of the first comparator 103 and the second comparator 104 need to be externally connected with a dc power supply.
The trigger port R of the first D flip-flop 105 is connected to the high-frequency sampling signal SHsThe input port D of the first D flip-flop 105 is connected to the low frequency sampling signal SLsThe output port Q of the first D flip-flop 105 outputs a synchronous sampling signal Ssamp；
The input of the voltage buffer 106 receives the low frequency rectified voltage signal SLThe output terminal of the voltage buffer 106 is connected to the synchronous sampling signal SsampA controlled switch for generating the DC analog amplitude signal Ma。
At DC analog amplitude signal MaA second capacitor C is also connected between the port and the ground2And the voltage stabilizing function is realized.
Fig. 3 is a schematic diagram of sampling by a conventional sampling technique, and fig. 4 is a schematic diagram of sampling according to an embodiment of the present invention. As can be seen from fig. 3, when the sampling clock synchronization is performed, the external sampling clock signal SextFor low frequency rectification voltage signal SLThe sampling has uncertainty, so that large ripple waves are generated, and large noise interference is generated on a rear-stage time domain analog-to-digital conversion module, so that the performance requirement of low power consumption of the whole received signal strength detection circuit cannot be met. As can be seen from fig. 4, if the synchronous sampling signal S is usedsampSampling is carried out, ripples can be greatly suppressed, and therefore sampling stability is improved. Comparing fig. 3 with fig. 4, it can be known that the ripple-suppressed OOK signal amplitude detection module 101 can reduce the low-frequency rectified voltage signal SLThe function of medium AC ripple. Sampling the high frequency signal S by a D flip-flopHsAnd a low frequency sampling signal SLsAnd synchronizing so as to fix the position of the sampling point and inhibit the amplitude of ripple waves.
Based on the content of the above embodiment, as shown in fig. 5, the time domain analog-to-digital conversion module 200 further includes: a voltage to frequency converter 201 and a quantization noise shaped frequency to digital converter 202, wherein,
the voltage-to-frequency converter 201 is configured to receive the dc analog amplitude signal M output by the ripple-suppressed OOK signal amplitude detection module 100aConverting the DC analog amplitude signal into an amplitude frequency modulation signal M with a frequency varying with the DC analog amplitude signalfAnd outputting the amplitude frequency modulation signal M outwardsf；
The conversion of the sampling voltage into a frequency signal is realized by a voltage-frequency converter.
The quantization noise shaped frequency-to-digital converter 202 is configured to receive the amplitude modulation signal MfAnd frequency-modulating said amplitude signal MfIs measured and a digital amplitude signal M representing the measurement result is outputdThe digital amplitude signal M is converted into a digital amplitude signaldAs the output of the entire received signal strength detection circuit.
In the embodiment of the present invention, the quantization noise-shaped frequency-to-digital converter 202 reduces low-frequency noise by using the first-order noise shaping principle, thereby implementing frequency-to-digital conversion with ultra-low power consumption.
Based on the content of the foregoing embodiment, as shown in fig. 6, a specific structural diagram of the time domain analog-to-digital conversion module 200 is shown, wherein the voltage-to-frequency converter 201 further includes: first PMOS transistor MP0A first NMOS transistor MN0And N delay units; wherein the content of the first and second substances,
each delay unit comprises a second PMOS transistor, a third PMOS transistor, a second NMOS transistor and a third NMOS transistor;
specifically, the ith delay unit includes a second PMOS transistor MPibAnd a third PMOS transistor MPiaA second NMOS transistor MNiaAnd a third NMOS transistor MNib。
The number N of delay units in the voltage-to-frequency converter 201 reflects the conversion relationship between the voltage and the frequency, and the value of N can be set according to the actual application requirement.
As shown in fig. 6, in each delay cell, the second PMOS transistor MPibIs connected to the power supply, the second PMOS transistor MPibIs connected to the third PMOS transistor MPiaThe third PMOS transistor MPiaIs connected with the second NMOS transistor MNiaThe third PMOS transistor MPiaHas a drain connected to the second NMOS transistor MNiaThe second NMOS transistor MNiaIs connected to the third NMOS transistor MNibThe third NMOS transistor MNibOfIs connected with the first NMOS transistor MN0The third NMOS transistor MNibIs grounded.
The ripple-suppressed OOK signal amplitude detection module 100 outputs a dc analog amplitude signal MaThe grid of the second PMOS transistor connected to all the delay units and the first PMOS transistor MP0Of the grid, i.e. MaAccessing MP1b～MPNbGate and MP of0In order to equalize the currents flowing through the second PMOS transistors of each delay cell.
The first PMOS transistor MP0With the drain of the first NMOS transistor MN at the same time0Is connected with the drain electrode to form a current mirror structure, and the current mirror structure is used for converting the direct current analog amplitude signal MaThird NMOS transistor mirrored to all delay cells, i.e. DC analog amplitude signal MaMN connected by diode0Mirrored to all third NMOS transistors, i.e. connected to MN1b～MNNbIn order to equalize the currents flowing through the third NMOS transistors of each delay cell.
The input and output ports between adjacent delay units being connected end to end, e.g. the output D of the first delay unit1And input G of the second delay unit2Connect, and so on.
It is worth to say that the output D of the Nth delay unitNInput G connected to the first delay unit1Forming a loop with the output M of any one delay unitfAs the output of the voltage to frequency converter 201.
Accordingly, the quantization noise shaped frequency-to-digital converter 202 further comprises a second D flip-flop 301, a third D flip-flop 302 and an exclusive or gate 303; wherein the content of the first and second substances,
the input port D of the second D flip-flop 301 is connected to the amplitude frequency modulation signal M output by the voltage-to-frequency converter 201fThe output port Q of the second D flip-flop 301 is connected to the input port D of the third D flip-flop 302 and one of the xor gate 303The trigger ports C of the second D flip-flop 301 and the third D flip-flop 302 are both connected to an externally input clock signal clk, the output port Q of the third D flip-flop 302 is connected to another input port of the xor gate 303, and a signal output by the xor gate 303 is an output digital amplitude signal M of the time domain analog-to-digital conversion module 200d。
As shown in fig. 7, a schematic diagram of a specific structure of a time domain analog-to-digital conversion module according to another embodiment of the present invention is provided, where the voltage-to-frequency converter 201 includes: first PMOS transistor MP0A first NMOS transistor MP0And N delay units; wherein the content of the first and second substances,
each delay unit comprises a second PMOS transistor, a third PMOS transistor, a second NMOS transistor and a third NMOS transistor;
specifically, the ith delay unit includes a second PMOS transistor MPibAnd a third PMOS transistor MPiaA second NMOS transistor MNiaAnd a third NMOS transistor MNib。
In each of the delay cells, the second PMOS transistor MPibIs connected to the power supply, the second PMOS transistor MPibIs connected to the third PMOS transistor MPiaThe third PMOS transistor MPiaIs connected with the second NMOS transistor MNiaThe third PMOS transistor MPiaHas a drain connected to the second NMOS transistor MNiaThe second NMOS transistor MNiaIs connected to the third NMOS transistor MNibThe third NMOS transistor MNibIs connected with the first NMOS transistor MN0The third NMOS transistor MNibThe source of (2) is grounded;
the ripple-suppressed OOK signal amplitude detection module 100 outputs a dc analog amplitude signal MaThe grid of the second PMOS transistor connected to all the delay units and the first PMOS transistor MP0Of the grid, i.e. MaAccessing MP1b～MPNbGate and MP of0A gate electrode of (1); likewise, do soThe purpose is to equalize the current flowing through the second PMOS transistor of each delay cell.
The first PMOS transistor MP0With the drain of the first NMOS transistor MN at the same time0Is connected with the drain electrode to form a current mirror structure, and the current mirror structure is used for converting the direct current analog amplitude signal MaThird NMOS transistor mirrored to all delay cells, i.e. DC analog amplitude signal MaMN connected by diode0Mirrored to all third NMOS transistors, i.e. connected to MN1b～MNNbIn order to equalize the currents flowing through the third NMOS transistors of each delay cell.
The input and output ports between adjacent delay units are connected end to end, wherein the output of the Nth delay unit is connected back to the input port G of the first delay unit after passing through the second D flip-flop1And taking the output of the Nth time delay unit as the output of the voltage-frequency converter.
Accordingly, the quantization noise shaped frequency-to-digital converter 202 further comprises the second D flip-flop 301, a third D flip-flop 302 and an exclusive or gate 303; wherein the content of the first and second substances,
the input port D of the second D flip-flop 301 is connected to the amplitude frequency modulation signal M output by the voltage-to-frequency converter 201fThe output port Q of the second D flip-flop 301 is connected to the input port G of the first delay unit1An input port D of the third D flip-flop 302 and an input port of the xor gate 303, trigger ports C of the second D flip-flop 301 and the third D flip-flop 303 are connected to an externally input clock signal clk, an output port Q of the third D flip-flop 302 is connected to another input port of the xor gate 303, and a signal output by the xor gate 303 is an output M of the time domain analog-to-digital conversion module 200d。
As can be known from comparing fig. 6 and fig. 7, fig. 7 is different from fig. 6 in that the output D of the nth delay cell in the time domain analog-to-digital conversion module shown in fig. 7NFirst passes through the second D flip-flop and then returns to the input G of the first delay unit1. It will be appreciated thatThe time domain analog-to-digital conversion module shown in fig. 6 or fig. 7 can realize the ultra-low power consumption conversion from the voltage signal to the frequency signal and then to the digital signal.
The received signal strength detection circuit provided by the embodiment of the invention realizes the conversion from sampling voltage to frequency signals through the voltage-frequency converter, and can greatly inhibit low-frequency noise and realize digital conversion with ultra-low power consumption by utilizing the first-order noise shaping principle, and the structure is simple and easy to realize.
As shown in fig. 8, a method for detecting received signal strength according to another embodiment of the present invention includes:
step 800, receiving an OOK receiving signal, converting the OOK receiving signal into a direct current analog amplitude signal according to the amplitude of the OOK receiving signal, and suppressing alternating current ripples in the conversion process;
step 810, converting the direct current analog amplitude signal into an amplitude frequency modulation signal with amplitude changing along with the direct current analog amplitude signal, measuring the frequency of the amplitude frequency modulation signal, and outputting a digital amplitude signal representing a measurement result.
Specifically, in order to detect the strength of the OOK receiving signal, amplitude detection is performed on the received OOK receiving signal, the OOK receiving signal is converted into a direct current analog amplitude signal according to the amplitude of the OOK receiving signal, and an alternating current ripple is suppressed by a synchronous sampling signal during the conversion process. And then, performing time domain conversion on the direct current analog amplitude signal, specifically, converting the direct current analog amplitude signal into an amplitude frequency modulation signal of which the amplitude changes along with the direct current analog amplitude signal, measuring the frequency of the amplitude frequency modulation signal, and outputting a digital amplitude signal representing a measurement result, wherein the digital amplitude signal is an obtained strength detection result of the OOK receiving signal.
According to the received signal strength detection method provided by the embodiment of the invention, through sampling the amplitude of the OOK signal, the sampling ripple interference can be effectively reduced, high-efficiency and high-precision sampling is realized, and through realizing the conversion from the sampling voltage to the frequency signal and then to the digital signal, the low-frequency noise is greatly inhibited, so that the received signal strength detection with ultra-low power consumption is realized.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims (7)

1. A received signal strength detection circuit, comprising: the device comprises an OOK signal amplitude detection module for inhibiting ripples and a time domain analog-to-digital conversion module; wherein the content of the first and second substances,
the ripple-suppressed OOK signal amplitude detection module is configured to receive an OOK received signal, convert the OOK received signal into a dc analog amplitude signal according to the amplitude of the OOK received signal, suppress ac ripples during the conversion, and output the dc analog amplitude signal;
the time domain analog-to-digital conversion module is used for receiving the direct current analog amplitude signal, converting the direct current analog amplitude signal into an amplitude frequency modulation signal with amplitude changing along with the direct current analog amplitude signal, measuring the frequency of the amplitude frequency modulation signal and outputting a digital amplitude signal representing a measurement result;
wherein the time domain analog-to-digital conversion module further comprises: a voltage to frequency converter and a quantization noise shaped frequency to digital converter;
the voltage frequency converter is used for receiving the direct current analog amplitude signal, converting the direct current analog amplitude signal into an amplitude frequency modulation signal with the frequency changing along with the direct current analog amplitude signal, and outputting the amplitude frequency modulation signal outwards;
and the quantization noise-shaped frequency-to-digital converter is used for receiving the amplitude frequency modulation signal, measuring the frequency of the amplitude frequency modulation signal, outputting a digital amplitude signal representing the measurement result, and taking the digital amplitude signal as the output of the whole received signal strength detection circuit.
2. The circuit of claim 1, wherein the ripple-suppressed OOK signal magnitude detection module further comprises: the circuit comprises a first rectifying module, a second rectifying module, a first comparator, a second comparator, a first D trigger, a voltage buffer, a first resistor, a second resistor, a first capacitor and a second capacitor; wherein the content of the first and second substances,
the first rectifying module and the second rectifying module are both used for receiving the OOK receiving signal, performing square or absolute value operation on the OOK receiving signal, and outputting a current signal related to the amplitude of the OOK receiving signal;
an output port of the first rectifying module is connected with the first resistor and a first comparator, the first resistor is used for converting a current signal output by the first rectifying module into a high-frequency rectified voltage signal, and the first comparator is used for generating a high-frequency sampling signal according to the high-frequency rectified voltage signal;
the output port of the second rectifying module is connected with the second comparator and a filter network consisting of the second resistor and the first capacitor, the filter network is used for converting a current signal output by the second rectifying module into a low-frequency rectified voltage signal, and the second comparator is used for generating a low-frequency sampling signal according to the low-frequency rectified voltage signal;
a trigger port of the first D trigger is connected with the high-frequency sampling signal, an input port of the first D trigger is connected with the low-frequency sampling signal, and an output port of the first D trigger outputs a synchronous sampling signal;
the input end of the voltage buffer receives the low-frequency rectified voltage signal, and the output end of the voltage buffer is connected with a switch controlled by the synchronous sampling signal to generate the direct-current analog amplitude signal;
and the second capacitor is connected between the port of the direct current analog amplitude signal and the ground.
3. The circuit of claim 1, wherein the voltage to frequency converter comprises: the delay circuit comprises a first PMOS transistor, a first NMOS transistor and N delay units; wherein the content of the first and second substances,
each delay unit comprises a second PMOS transistor, a third PMOS transistor, a second NMOS transistor and a third NMOS transistor;
in each delay unit, the source of the second PMOS transistor is connected to a power supply, the drain of the second PMOS transistor is connected to the source of the third PMOS transistor, the gate of the third PMOS transistor is connected to the gate of the second NMOS transistor, the drain of the third PMOS transistor is connected to the drain of the second NMOS transistor, the source of the second NMOS transistor is connected to the drain of the third NMOS transistor, the gate of the third NMOS transistor is connected to the gate of the first NMOS transistor, and the source of the third NMOS transistor is grounded;
the direct-current analog amplitude signal output by the ripple-suppressed OOK signal amplitude detection module is simultaneously connected to the gates of the second PMOS transistors and the gates of the first PMOS transistors of all the delay units;
the drain electrode of the first PMOS transistor is simultaneously connected with the grid electrode and the drain electrode of the first NMOS transistor to form a current mirror structure, and the current mirror structure is used for mirroring the direct current analog amplitude signal to the third NMOS transistors of all the delay units;
and the input and output ports between adjacent delay units are connected end to end, the output of the Nth delay unit is connected with the input of the first delay unit, and the output of any delay unit is used as the output of the voltage-frequency converter.
4. The circuit of claim 1, wherein the voltage to frequency converter comprises: the delay circuit comprises a first PMOS transistor, a first NMOS transistor and N delay units; wherein the content of the first and second substances,
each delay unit comprises a second PMOS transistor, a third PMOS transistor, a second NMOS transistor and a third NMOS transistor;
in each delay unit, the source of the second PMOS transistor is connected to a power supply, the drain of the second PMOS transistor is connected to the source of the third PMOS transistor, the gate of the third PMOS transistor is connected to the gate of the second NMOS transistor, the drain of the third PMOS transistor is connected to the drain of the second NMOS transistor, the source of the second NMOS transistor is connected to the drain of the third NMOS transistor, the gate of the third NMOS transistor is connected to the gate of the first NMOS transistor, and the source of the third NMOS transistor is grounded;
the direct-current analog amplitude signal output by the ripple-suppressed OOK signal amplitude detection module is connected to the gates of the second PMOS transistors and the gates of the first PMOS transistors of all the delay units;
the drain electrode of the first PMOS transistor is simultaneously connected with the grid electrode and the drain electrode of the first NMOS transistor to form a current mirror structure, and the current mirror structure is used for mirroring the direct current analog amplitude signal to the third NMOS transistors of all the delay units;
and the input and output ports between the adjacent delay units are connected end to end, the output of the Nth delay unit passes through the second D trigger and then is connected back to the input of the first delay unit, and the output of the Nth delay unit is used as the output of the voltage-frequency converter.
5. The circuit of claim 3, wherein the quantization noise-shaped frequency-to-digital converter further comprises a second D flip-flop, a third D flip-flop, and an XOR gate; wherein the content of the first and second substances,
an input port of the second D flip-flop is connected to the amplitude frequency modulation signal output by the voltage-frequency converter, an output port of the second D flip-flop is connected to an input port of the third D flip-flop and an input port of the xor gate, trigger ports of the second D flip-flop and the third D flip-flop are both connected to an externally input clock signal, an output port of the third D flip-flop is connected to the other input port of the xor gate, and a signal output by the xor gate is output by the time domain analog-to-digital conversion module.
6. The circuit of claim 4, wherein the quantization noise-shaped frequency-to-digital converter further comprises the second D flip-flop, a third D flip-flop, and an XOR gate; wherein the content of the first and second substances,
an input port of the second D flip-flop is connected to the amplitude frequency modulation signal output by the voltage-frequency converter, an output port of the second D flip-flop is connected to an input port of the first delay unit, an input port of the third D flip-flop and an input port of the xor gate, trigger ports of the second D flip-flop and the third D flip-flop are connected to an external input clock signal, an output port of the third D flip-flop is connected to another input port of the xor gate, and a signal output by the xor gate is output by the time domain analog-to-digital conversion module.
7. A received signal strength detection method based on the received signal strength detection circuit according to any one of claims 1 to 6, characterized by comprising:
receiving an OOK receiving signal, converting the OOK receiving signal into a direct current analog amplitude signal according to the amplitude of the OOK receiving signal, and inhibiting alternating current ripples in the conversion process;
and converting the direct current analog amplitude signal into an amplitude frequency modulation signal with the amplitude changing along with the direct current analog amplitude signal, measuring the frequency of the amplitude frequency modulation signal, and outputting a digital amplitude signal representing the measurement result.
CN201910202591.3A 2019-03-18 2019-03-18 Received signal strength detection circuit and method Active CN111726179B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910202591.3A CN111726179B (en) 2019-03-18 2019-03-18 Received signal strength detection circuit and method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910202591.3A CN111726179B (en) 2019-03-18 2019-03-18 Received signal strength detection circuit and method

Publications (2)

Publication Number Publication Date
CN111726179A CN111726179A (en) 2020-09-29
CN111726179B true CN111726179B (en) 2021-12-17

Family

ID=72563003

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910202591.3A Active CN111726179B (en) 2019-03-18 2019-03-18 Received signal strength detection circuit and method

Country Status (1)

Country Link
CN (1) CN111726179B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113346869B (en) * 2021-04-27 2023-02-10 西安电子科技大学 Efficient ripple suppression circuit applied to weak signal reading

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101714851A (en) * 2009-11-16 2010-05-26 杭州士兰微电子股份有限公司 ASK/OOK modulating mode detecting circuit
CN102882821A (en) * 2012-09-13 2013-01-16 清华大学 On-off keying (OOK) radio frequency receiver
CN104582564A (en) * 2012-09-03 2015-04-29 株式会社日立制作所 Vital sign signal measurement device, and vital sign signal measurement system
CN104905767A (en) * 2014-03-12 2015-09-16 三星电子株式会社 Parallel biometric signal processor and method of controlling the same

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010093676A1 (en) * 2009-02-11 2010-08-19 Cardiac Pacemakers, Inc. Method and apparatus for intra-body ultrasound communication

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101714851A (en) * 2009-11-16 2010-05-26 杭州士兰微电子股份有限公司 ASK/OOK modulating mode detecting circuit
CN104582564A (en) * 2012-09-03 2015-04-29 株式会社日立制作所 Vital sign signal measurement device, and vital sign signal measurement system
CN102882821A (en) * 2012-09-13 2013-01-16 清华大学 On-off keying (OOK) radio frequency receiver
CN104905767A (en) * 2014-03-12 2015-09-16 三星电子株式会社 Parallel biometric signal processor and method of controlling the same

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
An Auto Loss Compensation System for Capacitive-Coupled Body Channel Communication;Jian Zhao等;《2018 IEEE International Symposium on Circuits and Systems(ISCAS)》;20180530;1-5页 *
一种应用于无线传感网络的自校正有源RC复数滤波器;陈涛;《中国优秀硕士学位论文全文数据库信息科技辑》;20130115(第2013年01期);第3-4章 *

Also Published As

Publication number Publication date
CN111726179A (en) 2020-09-29

Similar Documents

Publication Publication Date Title
US9641060B2 (en) Switching mode power supply
US20100052637A1 (en) Apparatus and Method for Sensing a Current Within a Coil
CN103345289B (en) Slope compensation and loop bandwidth self-adaptation control circuit and switching power supply using same
US20150137782A1 (en) Systems and methods to monitor current in switching converters
US9467774B2 (en) System and method for a PCM interface for a capacitive signal source
TW200824297A (en) Analog to digital converter with interference rejection capability
CN103760943B (en) A kind of slew rate enhancing circuit being applied to LDO
CN111726179B (en) Received signal strength detection circuit and method
Kranz Complete digital control method for PWM DCDC boost converter
CN109900981B (en) Low-power consumption RSSI detection circuitry based on automatic gain control
CN205067735U (en) Laser detection processing circuit
CN109412593A (en) A kind of part division assembly line SAR ADC digital circuit
JPWO2011104804A1 (en) Signal processing circuit, radio communication apparatus, and signal processing method
CN103326735A (en) Direct current offset correcting method of wireless medium-frequency receiving circuit system
CN108241129B (en) Device and method for monitoring output filter capacitor of switching power supply
CN106685633B (en) Full digital phase-shift micro signal phase-lock detection method and equipment
CN107104674B (en) Noise power estimation device in electric parameter measurement process
CN102427342B (en) Switched capacitor clock generator
TWI609565B (en) Piezoelectric energy harvesting device
TWI493884B (en) Delta-sigma modulator and method of calibration thereof
US20120013312A1 (en) Power Control Device and Method thereof
Cox et al. Zero-crossing chirp frequency demodulation for ultra-low-energy precise hybrid RF-acoustic ranging of mobile nodes
CN210089854U (en) Light intensity detection circuit
CN104506172A (en) 4-20mA current loop control PWM (Pulse Width Modulation) output circuit
CN204807622U (en) Detection circuitry

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant