CN113972203B - Trench MOS power device integrating Schottky diode and manufacturing process thereof - Google Patents
Trench MOS power device integrating Schottky diode and manufacturing process thereof Download PDFInfo
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- CN113972203B CN113972203B CN202111353315.0A CN202111353315A CN113972203B CN 113972203 B CN113972203 B CN 113972203B CN 202111353315 A CN202111353315 A CN 202111353315A CN 113972203 B CN113972203 B CN 113972203B
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- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000002184 metal Substances 0.000 claims abstract description 53
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 49
- 230000004888 barrier function Effects 0.000 claims abstract description 32
- 229920005591 polysilicon Polymers 0.000 claims abstract description 31
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 29
- 230000000873 masking effect Effects 0.000 claims abstract description 29
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 29
- 239000010703 silicon Substances 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 17
- 239000000956 alloy Substances 0.000 claims abstract description 17
- 210000000746 body region Anatomy 0.000 claims abstract description 17
- 229920002120 photoresistant polymer Polymers 0.000 claims description 79
- 238000000151 deposition Methods 0.000 claims description 38
- 238000005530 etching Methods 0.000 claims description 33
- 238000001259 photo etching Methods 0.000 claims description 24
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 21
- 238000000137 annealing Methods 0.000 claims description 15
- 238000005468 ion implantation Methods 0.000 claims description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 229910004339 Ti-Si Inorganic materials 0.000 claims description 3
- 229910010978 Ti—Si Inorganic materials 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims description 2
- 238000011084 recovery Methods 0.000 abstract description 5
- 230000003071 parasitic effect Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 30
- 230000007547 defect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention relates to a trench MOS power device integrating a Schottky diode, which comprises an N-type silicon substrate, a gate oxide layer, shielding gate polysilicon, gate conductive polysilicon, a P-type body region, an N+ type source region, a first front metal, a masking layer, a barrier alloy, a P-type column, a second front metal and a back metal. The high-efficiency groove MOS and the Schottky diode are integrated and connected in parallel in one cell, so that the number of devices of the circuit is reduced, the functions of two devices are integrated, the recovery efficiency of the switch is effectively ensured, the conduction loss of the parasitic diode in the parallel body is reduced, and the application cost of the devices is also reduced as a whole.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a trench MOS power device integrating a Schottky diode and a manufacturing process thereof.
Background
In the application of a switch circuit, a diode is connected in parallel for improving the recovery time of the switch, and a common MOS tube and a Schottky diode are connected in parallel for reducing conduction propagation delay, current and voltage ringing, but the volume and the number of devices occupy more circuit space and generate more power consumption.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provide a trench MOS power device integrating a Schottky diode and a manufacturing process thereof, wherein the trench MOS power device can reduce the number of devices of a circuit, effectively ensure the recovery efficiency of a switch and reduce the conduction loss of a parasitic diode in a parallel body.
According to the technical scheme provided by the invention, the trench MOS power device integrating the Schottky diode comprises an N-type silicon substrate, a gate oxide layer, shielding gate polysilicon, gate conductive polysilicon, a P-type body region, an N+ type source region, a first front metal, a masking layer, a barrier alloy, a P-type column, a second front metal and a back metal;
A groove is formed in the front surface of an N-type silicon substrate at one side of a corresponding groove MOS power device, a grid oxide layer is arranged in the groove, shielding grid polycrystalline silicon and grid conducting polycrystalline silicon are arranged in the grid oxide layer, the grid conducting polycrystalline silicon is located above the shielding grid polycrystalline silicon, the grid conducting polycrystalline silicon and the shielding grid polycrystalline silicon are separated by the grid oxide layer, a P-type body region formed by ion implantation and annealing is arranged outside the groove and between adjacent grooves, an N+ type source region formed by ion implantation and annealing is arranged above the P-type body region, first front metal is arranged above the N+ type source region, and the first front metal is conducted with the P-type body region;
Masking layers which are arranged at intervals are arranged on the front face of the N-type silicon substrate corresponding to one side of the Schottky diode, barrier alloy is arranged on the front face of the N-type silicon substrate between adjacent masking layers positioned in the middle, P-type columns which are formed by ion implantation and annealing are arranged between adjacent masking layers on two sides of the corresponding barrier alloy, and second front metal is arranged on the barrier alloy;
and the back metal is arranged on the back of the N-type silicon substrate.
Preferably, the width of the gate conductive polysilicon is greater than the width of the shielding gate polysilicon.
The manufacturing process of the trench MOS power device integrating the Schottky diode comprises the following steps of:
S1, providing an N-type silicon substrate;
S2, oxidizing the front surface of the N-type silicon substrate to form a SiO 2 masking layer;
S3, integrally depositing photoresist on the SiO 2 masking layer, and photoetching the photoresist on one side of the trench MOS power device;
S4, etching the SiO 2 masking layer on one side of the groove MOS power device and then removing the photoresist;
S5, carrying out groove etching on the N-type silicon substrate at one side of the groove MOS power device;
S6, depositing photoresist on the SiO 2 masking layer at one side of the Schottky diode, and photoetching the photoresist;
s7, etching the SiO 2 masking layer on one side of the Schottky diode and then removing the photoresist;
S8, depositing and etching back a first grid oxide layer and polysilicon in the groove;
S9, integrally depositing photoresist, and photoetching the photoresist at the position of the groove;
S10, removing photoresist after etching the gate oxide layer and the polysilicon to form shielding gate polysilicon;
S11, depositing and etching back a second gate oxide layer and polysilicon in the groove to form gate conductive polysilicon;
S12, depositing integral photoresist, photoetching the photoresist, and finally performing P-type conductive ion implantation;
s13, integrally removing the photoresist, and then performing P-region annealing to form a P-type body region and a P-type column;
s14, integrally depositing a SiO 2 barrier layer;
S15, integrally depositing photoresist on the silicon dioxide layer, and photoetching the photoresist on one side of the Schottky diode;
S16, firstly etching a silicon dioxide layer on one side of the Schottky diode, then integrally removing photoresist, and finally depositing an integral Ti metal barrier layer;
s17, carrying out a furnace tube high-temperature process on part of the Ti barrier layer at one side of the Schottky diode to form Ti-Si barrier alloy;
s18, integral etching is carried out on the Ti metal barrier layer;
s19, integral photoresist deposition is carried out, and photoresist on one side of the groove MOS power device is subjected to photoetching;
S20, etching the SiO 2 barrier layer on one side of the groove MOS power device;
s21, conducting N+ conductive ion implantation on one side of the groove MOS power device;
s22, integrally removing the photoresist;
s23, annealing the N+ region to form an N+ type source region;
S24, integral photoresist is deposited, and photoetching is carried out on the photoresist at the position of the opening;
S25, hole etching is carried out;
S26, integrally removing photoresist;
s27, integrally depositing a front metal layer;
S28, depositing integral photoresist, and then photoetching the photoresist to leave partial photoresist on one side of the groove MOS power device and partial photoresist on one side of the Schottky diode;
S29, etching the front metal layer to form a first front metal and a second front metal, then integrally removing photoresist, and finally thinning the back of the N-type epitaxial material;
s30, depositing an integral back metal layer to form back metal, thereby obtaining a finished product of the groove MOS power device integrating the Schottky diode.
The high-efficiency groove MOS and the Schottky diode are integrated and connected in parallel in one cell, so that the number of devices of the circuit is reduced, the functions of two devices are integrated, the recovery efficiency of the switch is effectively ensured, the conduction loss of the parasitic diode in the parallel body is reduced, and the application cost of the devices is also reduced as a whole.
Drawings
Fig. 1 is a structural diagram of an N-type silicon substrate provided in step S1.
Fig. 2 is a block diagram after the processing of step S2.
Fig. 3 is a block diagram after the processing of step S3.
Fig. 4 is a block diagram after the processing of step S4.
Fig. 5 is a block diagram after the processing of step S5.
Fig. 6 is a block diagram after the processing of step S6.
Fig. 7 is a block diagram after the processing of step S7.
Fig. 8 is a block diagram after the processing of step S8.
Fig. 9 is a block diagram after the processing of step S9.
Fig. 10 is a block diagram after the processing of step S10.
Fig. 11 is a block diagram after the processing of step S11.
Fig. 12 is a block diagram after the processing of step S12.
Fig. 13 is a configuration diagram after the processing of step S13.
Fig. 14 is a block diagram after the processing of step S14.
Fig. 15 is a block diagram after the processing of step S15.
Fig. 16 is a block diagram after the processing of step S16.
Fig. 17 is a block diagram after the processing of step S17.
Fig. 17 is a block diagram after the processing of step S18.
Fig. 19 is a block diagram after the processing of step S19.
Fig. 20 is a block diagram after the processing of step S20.
Fig. 21 is a block diagram after the processing of step S21.
Fig. 22 is a block diagram after the processing of step S22.
Fig. 23 is a configuration diagram after the processing of step S23.
Fig. 24 is a block diagram after the processing of step S24.
Fig. 25 is a block diagram after the processing of step S25.
Fig. 26 is a block diagram after the processing of step S26.
Fig. 27 is a configuration diagram after the processing of step S27.
Fig. 28 is a block diagram after the processing of step S28.
Fig. 29 is a configuration diagram after the processing of step S29.
Fig. 30 is a block diagram after the processing of step S30.
Detailed Description
The invention will be further illustrated with reference to specific examples.
The trench MOS power device integrating the Schottky diode comprises an N-type silicon substrate 1, a gate oxide layer 2, a shielding gate polysilicon 3, a gate conductive polysilicon 4, a P-type body region 5, an N+ type source region 6, a first front metal 7, a masking layer 8, a barrier alloy 9, a P-type column 10, a second front metal 11 and a back metal 12 as shown in FIG. 30;
a groove is formed in the front face of an N-type silicon substrate 1 at one side of a corresponding groove MOS power device, a grid electrode oxide layer 2 is arranged in the groove, shielding grid polycrystalline silicon 3 and grid electrode conducting polycrystalline silicon 4 are arranged in the grid electrode oxide layer 2, the grid electrode conducting polycrystalline silicon 4 is positioned above the shielding grid polycrystalline silicon 3, the grid electrode conducting polycrystalline silicon 4 and the shielding grid polycrystalline silicon 3 are separated by the grid electrode oxide layer 2, a P-type body region 5 formed by ion implantation and annealing is arranged outside the groove and between adjacent grooves, an N+ type source region 6 formed by ion implantation and annealing is arranged above the P-type body region 5, a first front face metal 7 is arranged above the N+ type source region 6, and the first front face metal 7 is communicated with the P-type body region 5;
Masking layers 8 which are arranged at intervals are arranged on the front surface of the N-type silicon substrate 1 corresponding to one side of the Schottky diode, barrier alloy 9 is arranged on the front surface of the N-type silicon substrate 1 between adjacent masking layers 8 positioned in the middle, P-type columns 10 formed by ion implantation and annealing are arranged between adjacent masking layers 8 corresponding to two sides of the barrier alloy 9, and second front surface metal 11 is arranged on the barrier alloy 9;
A back metal 12 is provided on the back surface of the N-type silicon substrate 1.
The width of the gate conductive polysilicon 4 is larger than the width of the shielding gate polysilicon 3.
The manufacturing process of the trench MOS power device integrating the Schottky diode comprises the following steps of:
s1, providing an N-type silicon substrate 1, as shown in FIG. 1;
S2, oxidizing the front surface of the N-type silicon substrate 1 to form a SiO 2 masking layer 8, as shown in FIG. 2;
S3, integrally depositing photoresist on the SiO 2 masking layer 8, and photoetching the photoresist on one side of the trench MOS power device, as shown in FIG. 3;
S4, etching the SiO 2 masking layer 8 on one side of the trench MOS power device, and then removing photoresist, as shown in FIG. 4;
S5, carrying out groove etching on the N-type silicon substrate 1 at one side of the groove MOS power device, as shown in FIG. 5;
S6, depositing photoresist on the SiO 2 masking layer 8 at one side of the Schottky diode, and photoetching the photoresist, wherein the photoresist is shown in FIG. 6;
s7, removing photoresist after etching the SiO 2 masking layer 8 on one side of the Schottky diode, as shown in FIG. 7;
s8, depositing and etching back the first grid oxide layer 2 and the polysilicon in the groove, as shown in FIG. 8;
S9, integrally depositing photoresist, and photoetching the photoresist at the groove position, as shown in FIG. 9;
s10, removing photoresist after etching the gate oxide layer 2 and the polysilicon to form shielding gate polysilicon 3, as shown in FIG. 10;
S11, depositing and etching back a second gate oxide layer and polysilicon in the groove to form gate conductive polysilicon 4, as shown in FIG. 11;
S12, firstly depositing integral photoresist, then photoetching the photoresist, and finally performing P-type conductive ion implantation, as shown in FIG. 12;
s13, performing P-region annealing after integrally removing the photoresist to form a P-type body region 5 and a P-type column 10, as shown in FIG. 13;
S14, integrally depositing a SiO 2 barrier layer, as shown in FIG. 14;
S15, integrally depositing photoresist on the silicon dioxide layer, and photoetching the photoresist on one side of the Schottky diode, as shown in FIG. 15;
s16, firstly etching a silicon dioxide layer on one side of the Schottky diode, then integrally removing photoresist, and finally depositing an integral Ti metal barrier layer, as shown in FIG. 16;
s17, carrying out a furnace tube high-temperature process on part of the Ti barrier layer on one side of the Schottky diode to form Ti-Si barrier alloy 9, as shown in FIG. 17;
s18, integrally etching the Ti metal barrier layer, as shown in FIG. 18;
s19, integral photoresist is deposited, and photoresist on one side of the groove MOS power device is subjected to photoetching, as shown in FIG. 19;
S20, etching the SiO 2 barrier layer on one side of the groove MOS power device, as shown in FIG. 20;
S21, conducting N+ conductive ion implantation on one side of the groove MOS power device, as shown in FIG. 21;
s22, integrally removing the photoresist, as shown in FIG. 22;
s23, annealing the N+ region to form an N+ type source region 6, as shown in FIG. 23;
s24, integral photoresist is deposited, and photoetching is carried out on the photoresist at the position of the opening, as shown in FIG. 24;
S25, hole etching is carried out, as shown in FIG. 25;
s26, integrally removing the photoresist, as shown in FIG. 26;
s27, integrally depositing a front metal layer, as shown in FIG. 27;
S28, depositing integral photoresist, and then photoetching the photoresist to leave a part of photoresist on one side of the groove MOS power device and a part of photoresist on one side of the Schottky diode, as shown in FIG. 28;
S29, etching the front metal layer to form a first front metal 7 and a second front metal 11, then integrally removing photoresist, and finally thinning the back of the N-type epitaxial material, as shown in FIG. 29;
And S30, depositing an integral back metal layer to form a back metal 12, thereby obtaining a finished product of the trench MOS power device integrating the Schottky diode, as shown in figure 30.
In the invention, a trench MOS power device is composed of an N-type silicon substrate 1, a gate oxide layer 2, shielding gate polysilicon 3, gate conductive polysilicon 4, a P-type body region 5, an N+ type source region 6, a first front metal 7 and a back metal 12, a Schottky diode is composed of the N-type silicon substrate 1, a masking layer 8, a barrier alloy 9, a P-type column 10, a second front metal 11 and the back metal 12, and the trench MOS power device and the Schottky diode share the N-type silicon substrate 1 and the back metal 12.
The trench MOS power device and the Schottky diode are integrated and connected in parallel in one cell, so that the number of devices of the circuit is reduced, the functions of two devices are integrated, the recovery efficiency of a switch is effectively ensured, the conduction loss of parasitic diodes in parallel is reduced, and the application cost of the devices is also reduced as a whole.
According to the invention, the groove MOS power device process and the on-line process of the Schottky diode are matched and integrated in one cell by combining the device principle and the manufacturing process, so that the chip integration of two externally linked devices is realized, the size is smaller, the cost is lower, and the performance is better, thereby obtaining better product benefits. Meanwhile, from the perspective of circuit application, the chip is integrated, so that the product volume can be reduced, and the circuit space can be saved.
Claims (3)
1. A manufacturing process of a trench MOS power device integrating a Schottky diode is characterized by comprising the following steps:
s1, providing an N-type silicon substrate (1);
S2, oxidizing the front surface of the N-type silicon substrate (1) to form a SiO 2 masking layer (8);
S3, integrally depositing photoresist on the SiO 2 masking layer (8), and photoetching the photoresist on one side of the trench MOS power device;
S4, etching the SiO 2 masking layer (8) on one side of the groove MOS power device, and then removing the photoresist;
S5, carrying out groove etching on the N-type silicon substrate (1) at one side of the groove MOS power device;
s6, depositing photoresist on the SiO 2 masking layer (8) at one side of the Schottky diode, and photoetching the photoresist;
S7, etching the SiO 2 masking layer (8) on one side of the Schottky diode, and removing the photoresist;
s8, depositing and etching back a first grid oxide layer (2) and polysilicon in the groove;
S9, integrally depositing photoresist, and photoetching the photoresist at the position of the groove;
S10, removing photoresist after etching the gate oxide layer (2) and the polysilicon to form shielding gate polysilicon (3);
S11, depositing and etching back a second gate oxide layer and polysilicon in the groove to form gate conductive polysilicon (4);
S12, depositing integral photoresist, photoetching the photoresist, and finally performing P-type conductive ion implantation;
S13, integrally removing photoresist and then performing P-region annealing to form a P-type body region (5) and a P-type column (10);
s14, integrally depositing a SiO 2 barrier layer;
S15, integrally depositing photoresist on the silicon dioxide layer, and photoetching the photoresist on one side of the Schottky diode;
S16, firstly etching a silicon dioxide layer on one side of the Schottky diode, then integrally removing photoresist, and finally depositing an integral Ti metal barrier layer;
s17, carrying out a furnace tube high-temperature process on part of the Ti barrier layer at one side of the Schottky diode to form Ti-Si barrier alloy (9);
s18, integral etching is carried out on the Ti metal barrier layer;
s19, integral photoresist deposition is carried out, and photoresist on one side of the groove MOS power device is subjected to photoetching;
S20, etching the SiO 2 barrier layer on one side of the groove MOS power device;
s21, conducting N+ conductive ion implantation on one side of the groove MOS power device;
s22, integrally removing the photoresist;
S23, annealing the N+ region to form an N+ type source region (6);
S24, integral photoresist is deposited, and photoetching is carried out on the photoresist at the position of the opening;
S25, hole etching is carried out;
S26, integrally removing photoresist;
s27, integrally depositing a front metal layer;
S28, depositing integral photoresist, and then photoetching the photoresist to leave partial photoresist on one side of the groove MOS power device and partial photoresist on one side of the Schottky diode;
S29, etching the front metal layer to form a first front metal (7) and a second front metal (11), then integrally removing photoresist, and finally thinning the back of the N-type epitaxial material;
S30, depositing an integral back metal layer to form back metal (12), so that a finished product of the groove MOS power device integrating the Schottky diode is obtained.
2. A trench MOS power device incorporating a schottky diode fabricated according to the process of claim 1, characterized by: the semiconductor device comprises an N-type silicon substrate (1), a gate oxide layer (2), shielding gate polysilicon (3), gate conductive polysilicon (4), a P-type body region (5), an N+ type source region (6), a first front metal (7), a masking layer (8), a barrier alloy (9), a P-type column (10), a second front metal (11) and a back metal (12);
A groove is formed in the front face of an N-type silicon substrate (1) at one side of a corresponding groove MOS power device, a grid oxide layer (2) is arranged in the groove, shielding grid polycrystalline silicon (3) and grid conductive polycrystalline silicon (4) are arranged in the grid oxide layer (2), the grid conductive polycrystalline silicon (4) is located above the shielding grid polycrystalline silicon (3), the grid conductive polycrystalline silicon (4) and the shielding grid polycrystalline silicon (3) are separated by the grid oxide layer (2), a P-type body region (5) formed by ion implantation and annealing is arranged outside the groove and between adjacent grooves, an N+ type source region (6) formed by ion implantation and annealing is arranged above the P-type body region (5), a first front metal (7) is arranged above the N+ type source region (6), and the first front metal (7) is conducted with the P-type body region (5);
Masking layers (8) which are arranged at intervals are arranged on the front surface of the N-type silicon substrate (1) corresponding to one side of the Schottky diode, barrier alloy (9) is arranged on the front surface of the N-type silicon substrate (1) between adjacent masking layers (8) positioned in the middle, P-type columns (10) formed by ion implantation and annealing are arranged between adjacent masking layers (8) on two sides of the corresponding barrier alloy (9), and second front surface metal (11) is arranged on the barrier alloy (9);
a back metal (12) is provided on the back surface of the N-type silicon substrate (1).
3. The trench MOS power device of claim 2 integrated schottky diode, wherein: the width of the grid conductive polysilicon (4) is larger than that of the shielding grid polysilicon (3).
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| CN202111353315.0A CN113972203B (en) | 2021-11-16 | 2021-11-16 | Trench MOS power device integrating Schottky diode and manufacturing process thereof |
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| CN202111353315.0A CN113972203B (en) | 2021-11-16 | 2021-11-16 | Trench MOS power device integrating Schottky diode and manufacturing process thereof |
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