CN113922762A - Push-pull power amplification circuit and push-pull power amplification chip - Google Patents
Push-pull power amplification circuit and push-pull power amplification chip Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
- H03F3/195—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/213—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only in integrated circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/26—Push-pull amplifiers; Phase-splitters therefor
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
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Abstract
The embodiment of the application discloses a push-pull power amplification circuit and a push-pull power amplification chip, and relates to the technical field of electronic circuits. Wherein, push-pull power amplifier circuit includes: a first stage differential amplification circuit, the first stage differential amplification circuit comprising: the first bias ground terminal of the first bias amplification unit is connected with the second amplification ground terminal of the second bias amplification unit, the second amplification ground terminal is grounded, the second bias ground terminal of the second bias amplification unit is connected with the first amplification ground terminal of the first bias amplification unit, and the first amplification ground terminal is grounded, so that the potential difference between the first bias amplification unit and the second bias amplification unit caused by layout asymmetry is eliminated, and the linearity, the power addition efficiency and the memory effect of the push-pull power amplification circuit are improved.
Description
Technical Field
The application belongs to the technical field of electronic circuits, and particularly relates to a push-pull power amplification circuit and a push-pull power amplification chip.
Background
With the popularization of the fifth Generation Mobile Communication Technology (5G), the frequency band requirement for transmitting and receiving video signals to and from Communication devices such as terminals is increasing. For example, in order to satisfy compatibility of signal transceiving between different frequency bands, the terminal is required to simultaneously support signal transceiving operations of different frequency bands, that is, the radio frequency circuit in the terminal is enabled to satisfy transceiving of radio frequency signals of a wider frequency band. In the prior art, a push-pull power amplifier circuit is configured in a radio frequency circuit, and the push-pull power amplifier circuit is used as a core unit in the radio frequency circuit and is used for differentially amplifying input signal pairs.
However, the existing push-pull power amplifying circuit may also be composed of a multi-stage push-pull power amplifying circuit for amplifying the input signal pair step by step. In the case of a single-stage push-pull power amplifier circuit, which includes a pair of bias circuit and amplifier circuit, when differential amplification is implemented, two groups of combinational circuits composed of bias circuit and amplifier circuit are used to differentially amplify two signals in an input signal pair, respectively, so that when each combinational circuit differentially amplifies one signal in an input signal pair, the two differentially amplified signals will be different due to internal factors of the circuit, such as device characteristics, node potential difference, and the like. In addition, after two signals in the input signal pair are amplified step by step, the difference is more obvious, and the relevance between the amplified signal pair is further influenced. Therefore, the push-pull power amplification circuit in the prior art has the problem of low power addition efficiency.
Disclosure of Invention
The embodiment of the application provides a push-pull power amplification circuit and a push-pull power amplification chip, and aims to solve the problem that the push-pull power amplification circuit in the prior art is low in power addition efficiency.
In a first aspect, an embodiment of the present application provides a push-pull power amplifying circuit, including: a first stage differential amplification circuit, the first stage differential amplification circuit comprising:
the first bias amplification unit is provided with a first bias grounding end and a first amplification grounding end and is used for amplifying the first radio-frequency signal and outputting a first radio-frequency amplified signal;
the second bias amplification unit is provided with a second bias grounding end and a second amplification grounding end and is used for amplifying the second radio-frequency signal and outputting a second radio-frequency amplified signal;
the first bias grounding end is connected to the second amplification grounding end, the second amplification grounding end is grounded, the second bias is connected to the first amplification grounding end, and the first grounding end is grounded; the first radio frequency amplified signal and the second radio frequency amplified signal form a differential amplified signal pair.
In a first aspect, a push-pull power amplifying circuit is provided, which includes a first stage differential amplifying circuit, and the first stage differential amplifying circuit includes: the first bias amplifying unit and the second bias amplifying unit amplify the first radio frequency signal and the second radio frequency signal respectively to obtain a differential amplifying signal pair, wherein the first bias amplifying unit is provided with a first bias grounding terminal and a first amplifying grounding terminal, the second bias amplifying unit is provided with a second bias grounding terminal and a second amplifying grounding terminal, the first bias grounding terminal is connected with the second amplifying grounding terminal, the second amplifying grounding terminal is grounded, the second bias grounding terminal is connected with the first amplifying grounding terminal, the first amplifying grounding terminal is grounded, the grounding terminal part between the first bias amplifying unit and the second bias amplifying unit is shared to eliminate the potential difference between the first bias amplifying unit and the second bias amplifying unit caused by asymmetrical layout, namely, the first radio frequency amplifying signal obtained by amplifying the first radio frequency signal by the first bias amplifying unit is eliminated, and the voltage difference between the first radio-frequency amplified signal and the second radio-frequency amplified signal obtained by amplifying the second radio-frequency signal by using the second bias amplifying unit realizes the balance symmetry between the first bias amplifying unit and the second bias amplifying unit, thereby improving the linearity, the power addition efficiency and the memory effect of the push-pull power amplifying circuit.
In a second aspect, an embodiment of the present application further provides a push-pull power amplification chip, including the push-pull power amplification circuit in the first aspect.
The beneficial effects that the push-pull power amplifier chip can achieve can refer to the beneficial effects of the push-pull power amplifier circuit provided in the first aspect, which are not described herein again.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a push-pull power amplifying circuit provided in an embodiment of the present application;
fig. 2 is a schematic structural diagram of a push-pull power amplifying circuit provided in an embodiment of the present application;
fig. 3 is a specific circuit diagram of a push-pull power amplifying circuit according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of a push-pull power amplifier chip according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a push-pull power amplifier circuit according to an embodiment of the present disclosure. As shown in fig. 1, a push-pull power amplifying circuit 100 includes: the first stage differential amplifying circuit.
In fig. 1, the first stage differential amplification circuit includes: a first bias amplifying unit 20 and a second bias amplifying unit 30. Specifically, the method comprises the following steps:
the first bias amplifying unit 20 has a first bias ground terminal 21 and a first amplifying ground terminal 22, and the first bias amplifying unit 20 is configured to amplify the first radio frequency signal and output a first radio frequency amplified signal. The second bias amplifying unit 30 has a second bias ground terminal 31 and a second amplifying ground terminal 32, and the second bias amplifying unit 30 is configured to amplify the second radio frequency signal and output the second radio frequency amplified signal. The first bias ground terminal 21 is connected to the second amplification ground terminal 32, the second amplification ground terminal 32 is grounded, the second bias ground terminal 31 is connected to the first amplification ground terminal 22, and the first amplification ground terminal 22 is grounded; the first radio frequency amplified signal and the second radio frequency amplified signal form a differential amplified signal pair.
In this embodiment, the first rf signal and the second rf signal may be provided by a previous-stage signal source, for example, a signal transmission circuit located at a stage after the first-stage differential amplifying circuit, or other signal sources. The first bias amplifying unit 20 amplifies the first rf signal and outputs a first rf amplified signal, and the second bias amplifying unit 30 amplifies the second rf signal and outputs a second rf amplified signal. Because the first radio frequency amplified signal and the second radio frequency amplified signal are two paths of signal pairs with the same amplitude and the opposite phase, the first radio frequency amplified signal and the second radio frequency amplified signal form a differential amplified signal pair. Similarly, the first radio frequency signal and the second radio frequency signal are also two signal pairs with the same amplitude and opposite phases.
It is easy to understand that the differential amplification signal pair composed of the first rf amplification signal and the second rf amplification signal can be continuously transmitted to the subsequent circuit or the next stage amplification circuit through the output terminal (not shown) of the first offset amplification unit 20 and the output terminal (not shown) of the second offset amplification unit 30, and the subsequent transmission and use of the differential amplification signal pair are not related to this embodiment, and therefore, the detailed description is omitted here.
In a specific implementation, the first bias amplifying unit 20 and the second bias amplifying unit 30 are respectively configured to amplify the first radio frequency signal and the second radio frequency signal, so that in an actual implementation, the first bias amplifying unit 20 and the second bias amplifying unit 30 may select an existing bias amplifying circuit with the same structure.
As an example, taking the bias amplifying circuit having the same structure as the first bias amplifying unit 20 and the second bias amplifying unit 30 as an example, in order to amplify the radio frequency signal, the bias amplifying circuit may include an amplifying unit and a bias unit, each of which is composed of a transistor, and the amplifying unit is configured to amplify the radio frequency signal without distortion. In addition, in the amplifying unit formed by the transistor, it is necessary to ensure that an emitter junction and a collector junction of the transistor are forward biased and reverse biased, that is, working power is supplied to each pin of the transistor, and therefore, a bias potential required for a base, an emitter, and a collector of the transistor is used by the biasing unit.
It should be noted that, in the existing push-pull power amplifier circuit, when an input signal pair is amplified, two sets of bias amplifier circuits, that is, two sets of bias units and amplifier units that are independent of each other, are required, and a bias ground terminal of a bias unit in each set of bias amplifier circuit is connected to an amplifier ground terminal of a corresponding amplifier unit. Therefore, in the practical application process of the two sets of bias amplifying circuits, imbalance exists between the two sets of bias amplifying circuits due to device errors or structural factors or limitations of circuit layout and the like.
For example, in the process of respectively implementing differential amplification on a first radio frequency signal and a second radio frequency signal by using two sets of bias amplification circuits, a bias unit and a corresponding amplification unit in the first set of bias amplification circuits are connected to an a ground end in common, a bias unit and a corresponding amplification unit in the second set of bias amplification circuits are connected to a B ground end in common, and a difference exists between a voltage of the a ground end and a voltage of the B ground end, so that an imbalance exists between a first amplified radio frequency signal obtained by amplifying the first radio frequency signal by the first set of bias amplification circuits and a second amplified radio frequency signal obtained by amplifying the second radio frequency signal by the second set of bias amplification circuits. That is, an asymmetry of the bias potential between the two sets of bias amplifier circuits or a circuit layout (layout symmetry) is caused, thereby lowering the Power Added Efficiency (PAE) of the push-pull power amplifier circuit as a whole.
As shown in fig. 1, in the first bias amplifying unit 20 of the present embodiment, the first bias ground terminal 21 is a ground terminal of a bias circuit for providing a bias signal in the first bias amplifying unit 20, and the first amplification ground terminal 22 is a ground terminal of an amplifying circuit for amplifying a first radio frequency signal in the first bias amplifying unit 20. Accordingly, the second bias ground terminal 31 of the second bias amplifying unit 30 is a ground terminal of the bias circuit for providing the bias signal in the second bias amplifying unit 30, and the second amplification ground terminal 32 of the second bias amplifying unit 30 is a ground terminal of the amplifying circuit for amplifying the second radio frequency signal in the second bias amplifying unit 30. The first bias grounding terminal 21 of the first bias amplifying unit 20 is connected to the second amplification grounding terminal 32 of the second bias amplifying unit 30, the second amplification grounding terminal 32 is grounded, the second bias grounding terminal 31 of the second bias amplifying unit 30 is connected to the first amplification grounding terminal 22 of the first bias amplifying unit 20, and the first amplification grounding terminal 22 is grounded, so that the first bias amplifying unit 20 and the second bias amplifying unit 30 are connected in a crossed common mode, the bias grounding terminal and the amplification grounding terminal are connected in a crossed common mode, and the phenomenon of bias potential difference caused by the common grounding of the bias grounding terminal and the amplification grounding terminal of the same bias amplifying circuit is eliminated. Through the cross common ground between the first bias amplifying unit 20 and the second bias amplifying unit 30, while the structural association of each bias amplifying circuit in the differential amplifying process is realized, the bias potential symmetry or layout symmetry (layout symmetry) between the first bias amplifying unit 20 and the second bias amplifying unit 30 is also realized, and further, the pressure difference between the first bias amplifying unit 20 and the second bias amplifying unit 30 caused by the layout asymmetry is avoided, so that the overall power addition efficiency PAE, the linearity and the memory effect of the push-pull power amplifying circuit are improved.
Fig. 2 is a schematic structural diagram of a push-pull power amplifying circuit according to an embodiment of the present disclosure. As shown in fig. 2, as an example, the push-pull power amplifying circuit 100 may further include a previous stage circuit unit 10, and the previous stage circuit unit 10 includes a balun unit 101.
The balun unit 101 has a first input 1011, a first output 1012 and a second output 1013.
The balun unit 101 is configured to receive a radio frequency signal through a first input end 1011, provide a first radio frequency signal through a first output end 1012, and provide a second radio frequency signal through a second output end 1013.
In this embodiment, since the balun unit 101 is configured to provide impedance conversion or impedance conditions for at least two different lines, so as to implement combination of a balanced line and an unbalanced line, and the balun unit 101 accesses a radio frequency signal through the first input end 1011, in actual implementation, the first input end 1011 of the balun unit 101 may also be configured to be connected to a radio frequency signal source.
As an example, the balun unit 101 includes at least one twisted pair balun for providing impedance transformation for at least two different lines to achieve impedance matching, and the balun is composed of two or more sets of coils. Here, the first input terminal 1011 of the balun unit 101 may be a first terminal of a primary coil of the balun transformer, a second terminal of the primary coil is grounded, and the first output terminal 1012 and the second output terminal 1013 are both terminals of a secondary coil corresponding to the primary coil.
Fig. 3 is a specific circuit diagram of a push-pull power amplifying circuit according to an embodiment of the present disclosure. As shown in fig. 3, as an embodiment, the balun unit 101 includes: balun (L1, L2), a first capacitor C1 and a second capacitor C2.
The first end of a primary coil L1 of the balun is a first input end 1011 of the balun unit 101, the second end of the primary coil L1 of the balun is grounded, the first end of a secondary coil L2 of the balun is connected with the first end of a first capacitor C1, the second end of the first capacitor C1 is a first output end 1012 of the balun unit 101, the second end of a secondary coil L2 of the balun is connected with the first end of a second capacitor C2, and the second end of the second capacitor C2 is a second output end 1013 of the balun unit 101.
With reference to fig. 2 and fig. 3, in the front-stage circuit 10, the balun unit 101 receives an input signal through the primary coil L1, induces the input signal through the secondary coil L2, outputs a first radio frequency signal to the first bias amplifying unit 20 through the first capacitor C1, and outputs a second radio frequency signal to the second bias amplifying unit 30 through the second capacitor C2.
As shown in fig. 2, the first bias amplifying unit 20 includes: a first bias unit 201 and a first amplifying unit 202. The second bias amplifying unit 30 includes: a second bias unit 301 and a second amplifying unit 302.
The bias signal output terminal of the first bias unit 201 is connected to the input terminal of the first amplification unit 202 to form a first node P1, the first node P1 is used as the input terminal of the first bias amplification unit 201, the bias signal ground terminal of the first bias unit 201 is the first bias ground terminal 21 of the first bias amplification unit 20, and the amplification signal ground terminal of the first amplification unit 202 is the first amplification ground terminal 22 of the first bias amplification unit 20.
The bias signal output terminal of the second bias unit 301 is connected to the input terminal of the second amplification unit 302 to form a second node P2, the second node P2 is used as the input terminal of the second bias amplification unit 30, the bias signal ground terminal of the second bias unit 301 is the second bias ground terminal 31 of the second bias amplification unit 30, and the amplification signal ground terminal of the second amplification unit 302 is the second amplification ground terminal 32 of the second bias amplification unit 30.
In this embodiment, since the bias signal ground terminal of the first bias amplifying unit 201 is the first bias ground terminal 21 of the first bias amplifying unit 20 in the first bias amplifying unit 20, and the amplified signal ground terminal of the second amplifying unit 302 is the second amplified ground terminal 32 of the second bias amplifying unit 30 in the second bias amplifying unit 30, the bias signal ground terminal of the first bias amplifying unit 201 is connected to the amplified signal ground terminal of the second amplifying unit 302, and the amplified signal ground terminal of the second amplifying unit 302 is grounded. Accordingly, since the amplified signal ground terminal of the first amplification unit 202 is the first amplified ground terminal 22 of the first bias amplification unit 20 in the first bias amplification unit 20, and the biased signal ground terminal of the second bias amplification unit 301 is the second biased ground terminal 31 of the second bias amplification unit 30 in the second bias amplification unit 30, the biased signal ground terminal of the second bias amplification unit 301 is connected to the amplified signal ground terminal of the first amplification unit 202, and the amplified signal ground terminal of the first amplification unit 202 is grounded. In this embodiment, the bias signal ground terminal of the first bias unit 201 is connected to the amplified signal ground terminal of the second amplification unit 302, the amplified signal ground terminal of the second amplification unit 302 realizes the common ground between the first bias unit 201 and the second amplification unit 302, the bias signal ground terminal of the second bias unit 301 is connected to the amplified signal ground terminal of the first amplification unit 202, the common ground between the second bias unit 301 and the first amplification unit 202, so that the ground terminals between the first bias amplification unit 20 and the second bias amplification unit 30 are partially shared, thereby reducing the potential difference between the first bias amplification unit 20 and the second bias amplification unit 30, and further eliminating the first rf amplified signal obtained by performing differential amplification on the first rf signal by using the first bias amplification unit 20, the voltage difference between the first bias amplification unit 30 and the second radio frequency amplified signal obtained by performing the differential amplification on the first radio frequency signal improves the linearity and the power added efficiency of the push-pull power amplification circuit.
As shown in fig. 3, the first bias unit 201 includes a first bias amplifying transistor M1 and a first bias terminal capacitor C3, as one embodiment.
A first terminal of the first bias amplifying transistor M1 is connected to a first bias source terminal, a second terminal is connected to a first power supply terminal VCC, and a third terminal is coupled to the input terminal of the first amplifying unit 202; the first bias terminal capacitor C3 has one terminal connected to the first terminal of the first bias transistor M1 and the other terminal connected to the first bias ground terminal 21.
The second bias unit 301 includes a second bias amplifying transistor M2 and a second bias terminal capacitor C4.
A first terminal of the second bias amplifying transistor M2 is connected to a second bias source terminal, a second terminal is connected to a second power supply terminal VCC, and a third terminal is coupled to the input terminal of the second amplifying unit 302; the second bias terminal capacitor C4 has one terminal connected to the first terminal of the second bias transistor M2 and the other terminal connected to the second bias ground terminal 31.
In a specific embodiment, the first bias unit 201 may be coupled to the input terminal of the first amplifying unit 202 through the first resistor R1, the second bias unit 301 may be coupled to the input terminal of the second amplifying unit 302 through the first resistor R2, and by flexibly adjusting the resistances of the first resistor R1 and the second resistor R2, the first bias unit 201 may provide a proper bias signal to the first amplifying unit 202, and the second bias unit 301 may provide a proper bias signal to the second amplifying unit 302, so that the first amplifying unit 202 and the second amplifying unit 302 are at proper operating quiescent points; and the robustness of the whole circuit of the push-pull power amplification circuit is further improved.
It should be noted that, in the present application, the first bias unit 201 may be coupled to the input terminal of the first amplifying unit 202 through a first resistor R1, and the second bias unit 301 may be coupled to the input terminal of the second amplifying unit 302 through a second resistor R2, but in a preferred embodiment, the first bias unit 201 and the second bias unit 50 may also be coupled to the input terminal of the first amplifying unit 202 and the input terminal of the second amplifying unit 302 through any other manner. Such as: the first bias unit 201 may also be coupled to the input terminal of the first amplifying unit 202 through a first LC parallel circuit, and the second bias unit 301 is coupled to the input terminal of the second amplifying unit 302 through a second LC parallel circuit, which is not illustrated herein.
In a specific embodiment, the first bias unit 201 includes a first bias amplifying transistor M1 and a first bias terminal capacitor C3, a first terminal of the first bias amplifying transistor M1 is connected to a first bias source terminal, a second terminal of the first bias amplifying transistor M1 is connected to a first power supply terminal VCC, and a third terminal of the first bias amplifying transistor M1 is coupled to the input terminal of the first amplifying unit 202. The first bias source terminal is a port for receiving a first bias signal source. The first bias terminal capacitor C3 has one terminal connected to the first terminal of the first bias transistor M1 and the other terminal connected to the first bias ground terminal 21.
The second bias unit 301 includes a second bias amplifying transistor M2 and a second bias terminal capacitor C4.
A first terminal of the second bias amplifying transistor M2 is connected to a second bias source terminal, a second terminal is connected to a second power supply terminal VCC, and a third terminal is coupled to the input terminal of the second amplifying unit 302; one end of the second bias terminal capacitor C4 is connected to the first terminal of the second bias amplifying transistor M2, and the other end is connected to the second bias ground terminal 31, wherein the second bias power port is a port for receiving a second bias signal source.
As shown in fig. 3, as an example, the first bias unit 201 further includes a first serial voltage dividing circuit 2011, the first serial voltage dividing circuit 2011 is disposed between a first bias source terminal (not shown) and a ground terminal, and the first serial voltage dividing circuit 2011 includes a plurality of first voltage dividing units connected in series.
The second bias unit 301 further includes a second series voltage-dividing circuit 3011, where the second series voltage-dividing circuit 3011 is disposed between a second bias source terminal (not shown in the figure) and a ground terminal, and the second series voltage-dividing circuit includes a plurality of second voltage-dividing units connected in series.
Specifically, the first bias unit 201 further includes a first serial voltage dividing circuit 2011, a first bias source end of the first bias amplifying transistor M1 is connected to a first terminal of the first bias amplifying transistor M1, the first bias source end of the first bias amplifying transistor M1 is connected to a ground terminal of the first bias amplifying transistor M1 through the first serial voltage dividing circuit 2011, a second terminal of the first bias amplifying transistor M1 is connected to a first power supply terminal, and a third terminal of the first bias amplifying transistor M1 is connected to the first resistor R1.
The second bias unit 301 further includes a second series voltage-dividing circuit 3011, where a second bias source end is connected to a first end of the second bias amplifying transistor M2, the second bias source end is connected to a ground end through the second series voltage-dividing circuit 3011, a second end of the second bias amplifying transistor M2 is connected to a power supply end, and a third end of the second bias amplifying transistor M2 is connected to the second resistor R2.
Optionally, the first bias source terminal is configured to receive a bias signal source provided from a first bias power source and provide the bias signal source to the first bias amplifying transistor M1. The first bias power supply may be a bias current source or a bias voltage source. When the bias current source is used, the bias signal source for the first bias amplifying transistor M1 is a bias current, and when the bias voltage source is used, the bias signal source for the first bias amplifying transistor M1 is a bias voltage. The first bias amplifying transistor M1 may be a select bipolar transistor (BJT) and a Field Effect Transistor (FET). When the first bias amplifying transistor M1 is a Bipolar Junction Transistor (BJT), the first bias source terminal is connected to the base of the first bias amplifying transistor M1, and is configured to provide a bias signal source to the base of the first bias amplifying transistor M1, and the emitter of the first bias amplifying transistor M1 is connected to the first resistor R1, thereby realizing that the bias signals are provided to the first amplifying units, respectively. When the first bias amplifying transistor M1 is a Field Effect Transistor (FET), the first bias source terminal is connected to the gate of the first bias amplifying transistor M1, and is configured to supply a bias signal source to the gate of the first bias amplifying transistor M1, and the source terminal of the first bias amplifying transistor M1 is connected to the first resistor R1, thereby realizing the supply of the bias signal to the first amplifying unit.
Further, the first bias unit 201 further includes a first serial voltage dividing circuit 2011 disposed between the first bias source terminal and the ground terminal, and a connection node between the first bias source terminal and the first serial voltage dividing circuit 2011 is connected to a first terminal of the first bias amplifying transistor M1. The first serial voltage dividing circuit 2011 includes a first voltage dividing unit and a second voltage dividing unit connected in series, a first end of the first voltage dividing unit is connected to the first bias source terminal, a second end of the first voltage dividing unit is connected to the first end of the second voltage dividing unit, and a second end of the second voltage dividing unit is connected to the ground terminal. The first serial voltage divider circuit 2011 can stabilize the quiescent operating point of the bias signal. It should be noted that, in addition to this embodiment, the first voltage division unit and the second voltage division unit may be diodes, or may be replaced by triodes.
Likewise, the second bias supply terminal is configured to receive a source of bias signal from the second bias supply and provide the source of bias signal to the second bias amplifier transistor M2. The second bias power supply may be a bias current source or a bias voltage source. When the bias current source is used, the bias signal source for the second bias amplifying transistor M2 is a bias current, and when the bias voltage source is used, the bias signal source for the second bias amplifying transistor M2 is a bias voltage. The second bias amplifying transistor M2 may be a select bipolar transistor (BJT) and a Field Effect Transistor (FET). When the second bias amplifying transistor M2 is a Bipolar Junction Transistor (BJT), the second bias source terminal is connected to the base of the second bias amplifying transistor M2, and is configured to provide a bias signal source to the base of the second bias amplifying transistor M2, and the emitter of the second bias amplifying transistor M2 is connected to the second resistor R2, thereby realizing that bias signals are provided to the second amplifying units, respectively. When the second bias amplifying transistor M2 is a Field Effect Transistor (FET), the second bias source terminal is connected to the gate of the second bias amplifying transistor M2, and is configured to supply a bias signal source to the gate of the second bias amplifying transistor M2, and the source of the second bias amplifying transistor M2 is connected to the second resistor R2, thereby realizing the supply of the bias signal to the second amplifying unit.
Further, the second bias unit 301 further includes a second series voltage-dividing circuit 3011 disposed between the second bias source terminal and the ground terminal, and a connection node between the second bias source terminal and the second series voltage-dividing circuit 3011 is connected to the first terminal of the second bias amplifying transistor M2. The second series voltage division circuit comprises a third voltage division transistor and a fourth voltage division transistor which are connected in series, wherein the first end of the third voltage division transistor is connected with the second bias source end, the second end of the third voltage division transistor is connected with the first end of the fourth voltage division transistor, and the second end of the fourth voltage division transistor is connected with the grounding end. The second series voltage divider circuit 3011 can stabilize the quiescent operating point of the bias signal. It should be noted that, in addition to this embodiment, the third voltage division transistor and the fourth voltage division transistor may be diodes, or may be replaced by a triode.
It should be noted that the first bias power supply providing the bias signal source for the first bias unit 201 and the second bias power supply providing the bias signal source for the second bias unit 301 may be the same bias power supply or different bias power supplies. That is, the first bias amplifying transistor M1 in the first bias unit 201 and the second bias amplifying transistor M2 in the second bias unit 301 may be connected to one bias power source through the same bias power source terminal, or may be connected to two different bias power sources through two different bias power source terminals, respectively. The first bias power supply and the second bias power supply can adopt constant current sources for providing constant current as input current and ensuring the stability of the output first bias current and the output second bias current.
As shown in fig. 3, as an example, the second amplification unit 302 includes: a second differential amplifying transistor M4 and a second amplifying-terminal inductor L4; a first terminal of the second differential amplifying transistor M4 serves as an input terminal of the second amplifying unit 302; a second terminal of the second differential amplifying transistor M4 is connected to a first terminal of a second amplifying terminal inductor L4, a second terminal of the second amplifying terminal inductor L4 is connected to a second power supply terminal VCC, and a third terminal of the second differential amplifying transistor M4 is used as a second amplifying ground terminal 32.
As an example, the first differential amplification transistor is a BJT transistor, and includes a base, a collector, and an emitter, the base of the first differential amplification transistor being an input terminal of the first amplification unit; the collector of the first differential amplifying transistor is connected with the first amplifying end inductor, and the emitter of the first differential amplifying transistor is used as a first amplifying grounding end.
The second differential amplification transistor is a BJT (bipolar junction transistor) and comprises a base electrode, a collector electrode and an emitter electrode, and the base electrode of the second differential amplification transistor is used as the input end of the second amplification unit; the collector of the second differential amplifying transistor is connected with the second amplifying end inductor, and the emitter of the second differential amplifying transistor is used as a second amplifying grounding end.
In some embodiments, the first bias unit 201 and the second bias unit 301 may use bias circuits with the same structure. For example, in fig. 3, the first serial voltage-dividing circuit 2011 may also be replaced by another constant current source circuit, and the second serial voltage-dividing circuit 3011 may also be replaced by another constant current source circuit, and since various devices for amplification, such as transistors, and the like, and their functional or functional equivalent replacement devices belong to common knowledge in the art, they will not be described in detail below.
As an example, the first amplification unit 202 further includes a first metal region disposed at one side of the first differential amplification transistor; at least one first through hole is arranged on the first metal area; the emitter of the first differential amplification transistor is connected with the first metal area and is grounded through the first through hole of the first metal area; the second amplifying unit further includes a second metal region disposed at one side of the second differential amplifying transistor; at least one second through hole is formed in the second metal area; the emitter of the second differential amplifying transistor is connected with the second metal area and grounded through the second through hole of the second metal area.
As an example, the number of the first through holes and the number of the second through holes are the same.
Optionally, the first through hole and the second through hole are both circular, and the diameter of the first through hole is equal to the diameter of the second through hole. However, the shapes of the first through hole and the second through hole may be square, triangular or other shapes as required. Further, the diameter of the first through hole may be set according to the size of the first metal region, and the larger the diameter of the first through hole in the first metal region, the better. The diameter of the second through hole may be set according to the size of the second metal region, and the larger the diameter of the first through hole in the second metal region, the better. The emitter e of the first differential amplifier transistor may be connected to any position of the first metal region as required, as long as the effect of grounding the emitter e of the first differential amplifier transistor through the first metal region is achieved. Similarly, the emitter e of the second differential amplifier transistor may be connected to any position of the second metal region as required, as long as the effect of grounding the emitter e of the second differential amplifier transistor through the second metal region is achieved.
Optionally, the center points of all the first vias in the first metal region are arranged at intervals on a first straight line parallel to the first metal region; the center points of all the second through holes in the second metal area are arranged on a second straight line parallel to the second metal area at intervals. The first metal area and the second metal area may be strip-shaped, but may also be arranged in other shapes according to requirements, for example, the first metal area and the second metal area may include a plurality of metal sections arranged at intervals, and each metal section of the first metal area is provided with a first through hole; and each metal section of the second metal area is provided with a second through hole. Further, the sizes of the first through hole and the second through hole may be set to be uniform.
Optionally, the first distances between the center points of any two adjacent first through holes are equal, and the second distances between the center points of any two adjacent second through holes are equal; the first pitch is equal to the second pitch. That is, the first through holes and the second through holes are uniformly spaced on the first metal area and the second metal area. In the present embodiment, when the emitter e of the first differential amplifier transistor is grounded, one end of the emitter e of the first differential amplifier transistor is connected to the first metal region 2 designed with the single row of uniformly arranged first through holes 21; when the emitter e of the second differential amplification transistor is grounded, the other end of the emitter e of the second differential amplification transistor is connected with the second metal area 3 provided with the second through holes 31 which are uniformly distributed in a single row, so that the first differential amplification transistor and the second differential amplification transistor can be better cooled, the parasitic inductance generated by the first differential amplification transistor and the second differential amplification transistor in the push-pull power amplification circuit is effectively reduced, and the circuit performance is further improved.
As an example, the push-pull power amplifying circuit 100 further includes a second stage differential amplifying circuit including a third bias amplifying unit and a fourth bias amplifying unit, an output terminal of the third bias amplifying unit is coupled to an input terminal of the first bias amplifying unit, and an output terminal of the fourth bias amplifying unit is coupled to an input terminal of the second bias amplifying unit.
As an example, the push-pull power amplification circuit 100 further includes a pre-conversion unit configured to output the first input signal to the third offset amplification unit and output the second input signal to the fourth offset amplification unit according to the input signal.
It is understood that the second stage differential amplifier circuit is a front stage differential power amplifier circuit in the push-pull power amplifier circuit 100, and the first stage differential amplifier circuit is a rear stage differential power amplifier circuit in the push-pull power amplifier circuit 100. In a practical application, since the third amplification ground terminal of the third bias amplification unit and the fourth amplification ground terminal of the fourth bias amplification unit in the preceding stage differential power amplification circuit are connected to the ground terminal, and are usually grounded through only one or two ground vias, the potential difference between the third bias amplification unit and the fourth bias amplification unit is small, and the first amplification ground terminal of the first bias amplification unit and the second amplification ground terminal of the second bias amplification unit in the later stage differential power amplification circuit are connected to the ground terminal, and are usually connected through a plurality of ground vias (e.g., including 6 ground vias), so that the potential difference between the first bias amplification unit and the second bias amplification unit is large, the present application connects the first bias ground terminal of the later stage differential power amplification circuit in the push-pull power amplification circuit 100 to the second amplification ground terminal, the second amplification grounding terminal is grounded, the second bias is connected to the first amplification grounding terminal, and the first grounding terminal is grounded, so that the grounding terminal between the first bias amplification unit and the second bias amplification unit is partially shared, the potential difference between the first bias amplification unit and the second bias amplification unit is eliminated, the voltage difference between a first radio-frequency amplification signal obtained by performing differential amplification on a first radio-frequency signal by using the first bias amplification unit and a second radio-frequency amplification signal obtained by performing differential amplification on a second radio-frequency signal by using the second bias amplification unit is eliminated, and the linearity and the power addition efficiency of the push-pull power amplification circuit are improved.
The following explains a specific operation principle of the push-pull power amplifying circuit 100 provided in the present embodiment with reference to fig. 2 to 3.
In FIG. 2, the first bias unit 201 provides a bias voltage to the first amplifying unit 202 at a first node P1, and the second bias unit 301 provides a bias voltage to the second amplifying unit 302 at a second node P2. Since the first potential difference exists between the first amplifier unit 202 and the second amplifier unit 302, the first bias ground terminal 21 of the first bias unit 201 and the second bias ground terminal 32 of the second amplifier unit 302 are commonly grounded, and the first amplifier ground terminal 22 of the first amplifier unit 202 and the second bias ground terminal 31 of the second bias unit 301 are commonly grounded, so that the second potential difference exists between the first bias unit 201 and the second bias unit 301, and the second potential difference and the first potential difference are opposite numbers, thereby eliminating the potential difference between the first node P1 and the second node P2.
As shown in fig. 3, an input signal is input through the first end 1011 of the primary coil L1 of the balun unit 101, and a first rf signal is output to the first bias amplifying unit 20 through the first capacitor C1 and a second rf signal is output to the second bias amplifying unit 30 through the second capacitor C2 according to the input signal through the secondary coil L2 of the balun unit 101. The first end of the first resistor R1 is connected to the second end of the first bias amplifying transistor M1, and the second end of the first resistor R1 is used as the bias signal output end of the first bias unit 201 and is connected to the input end of the first amplifying unit 202, that is, the controlled end of the first differential amplifying transistor M3. Since the first terminal of the first offset terminal capacitor C3 is connected to the controlled terminal of the first bias amplifying transistor M1, the second terminal of the first offset terminal capacitor C3 is connected to the second amplifying ground terminal 32 as the first bias ground terminal 21, and the second amplifying ground terminal 32 is grounded to the GND2, the voltage of the first terminal of the first offset terminal capacitor C3 is affected by the common ground connection, so as to affect the controlled terminal of the first bias amplifying transistor M1 and the voltages of the two segments of the first resistor R1, i.e., the voltage of the first node P1. Similarly, in the bias circuit of the second bias amplifying unit 30, a first terminal of the second resistor R2 is connected to the second terminal of the second bias amplifying transistor M2, and a second terminal of the second resistor R2 is used as the bias signal output terminal of the second bias unit 301, and is connected to the input terminal of the second amplifying unit 302, that is, to the controlled terminal of the second differential amplifying transistor M4. Since the first terminal of the second offset terminal capacitor C4 is connected to the controlled terminal of the second bias amplifying transistor M2, the second terminal of the second offset terminal capacitor C4 is connected to the first amplifying ground terminal 22 as the second bias ground terminal 31, and the first amplifying ground terminal 22 is grounded to the GND1, the voltage of the first terminal of the second offset terminal capacitor C4 is affected by the common ground connection, so as to affect the controlled terminal of the second bias amplifying transistor M2 and the voltages of the two segments of the second resistor R2, i.e., the voltage of the second node P2. Since there is a voltage difference between the ground GND2 and the ground GND1, a potential difference between the first node P1 and the second node P2 is eliminated. Further, the voltage difference between the first radio-frequency amplified signal obtained by performing differential amplification on the first radio-frequency signal by using the first bias amplifying unit 20 and the second radio-frequency amplified signal obtained by performing differential amplification on the second radio-frequency signal by using the second bias amplifying unit 30 is eliminated, and the linearity and the power added efficiency of the push-pull power amplifying circuit are improved.
Fig. 4 shows a schematic structural diagram of a push-pull power amplification chip provided in an embodiment of the present application. As shown in fig. 4, a push-pull power amplifier chip 300 includes the push-pull power amplifier circuit 100 in the above-described embodiment.
It can be understood that, since the contents and implementation manners related to the present application have been described in detail in the above contents, details of the push-pull power amplifier chip 300 provided in this embodiment are not repeated herein.
The units in the terminal of the embodiment of the application can be combined, divided and deleted according to actual needs.
While the invention has been described with reference to specific embodiments, the scope of the invention is not limited thereto, and those skilled in the art can easily conceive various equivalent modifications or substitutions within the technical scope of the invention, and these modifications or substitutions are intended to be included in the scope of the invention. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A push-pull power amplification circuit, comprising: a first stage differential amplification circuit, the first stage differential amplification circuit comprising:
the first bias amplification unit is provided with a first bias grounding end and a first amplification grounding end and is used for amplifying the first radio-frequency signal and outputting a first radio-frequency amplified signal;
the second bias amplification unit is provided with a second bias grounding end and a second amplification grounding end and is used for amplifying the second radio-frequency signal and outputting a second radio-frequency amplified signal;
the first bias grounding end is connected to the second amplification grounding end, the second amplification grounding end is grounded, the second bias is connected to the first amplification grounding end, and the first grounding end is grounded; the first radio frequency amplified signal and the second radio frequency amplified signal form a differential amplified signal pair.
2. Push-pull power amplification circuit according to claim 1, wherein the first bias amplification unit comprises: a first bias unit and a first amplifying unit;
the bias signal output end of the first bias unit is connected with the input end of the first amplification unit to form a first node, the first node is used as the input end of the first bias amplification unit, the bias signal grounding end of the first bias unit is the first bias grounding end of the first bias amplification unit, and the amplification signal grounding end of the first amplification unit is the first amplification grounding end of the first bias amplification unit;
the second bias amplifying unit includes: a second bias unit and a second amplifying unit;
the bias signal output end of the second bias unit is connected with the input end of the second amplification unit to form a second node, the second node is used as the input end of the second bias amplification unit, the bias signal grounding end of the second bias unit is the second bias grounding end of the second bias amplification unit, and the amplification signal grounding end of the second amplification unit is the second amplification grounding end of the second bias amplification unit.
3. The push-pull power amplification circuit of claim 2, wherein the first bias unit comprises a first bias amplification transistor and a first bias terminal capacitance; the first end of the first bias amplifying transistor is connected with a first bias source end, the second end of the first bias amplifying transistor is connected with a first power supply end, and the third end of the first bias amplifying transistor is coupled to the input end of the first amplifying unit; one end of the first bias end capacitor is connected with the first end of the first bias transistor, and the other end of the first bias end capacitor is connected with the first bias grounding end;
the second bias unit comprises a second bias amplifying transistor and a second bias end capacitor; the first end of the second bias amplifying transistor is connected with a second bias source end, the second end of the second bias amplifying transistor is connected with a second power supply end, and the third end of the second bias amplifying transistor is coupled to the input end of the second amplifying unit; one end of the second bias end capacitor is connected with the first end of the second bias transistor, and the other end of the second bias end capacitor is connected with the second bias grounding end.
4. The push-pull power amplification circuit according to claim 3, wherein the first bias unit further comprises a first series voltage-dividing circuit provided between the first bias source terminal and a ground terminal, the first series voltage-dividing circuit comprising a plurality of first voltage-dividing units connected in series;
the second bias unit further comprises a second series voltage division circuit, the second series voltage division circuit is arranged between the second bias source end and the grounding end, and the second series voltage division circuit comprises a plurality of second voltage division units which are connected in series.
5. Push-pull power amplification circuit according to claim 4, wherein the first amplification unit comprises: a first differential amplifying transistor and a first amplifying terminal inductor; a first end of the first differential amplifying transistor is used as an input end of the first amplifying unit; a second end of the first differential amplification transistor is connected with a first end of the first amplification end inductor, a second end of the first amplification end inductor is connected with a first power supply end, and a third end of the first differential amplification transistor is used as a first amplification grounding end;
the second amplification unit includes: a second differential amplifying transistor and a second amplifying terminal inductor; a first end of the second differential amplifying transistor is used as an input end of the second amplifying unit; the second end of the second differential amplification transistor is connected with the first end of the second amplification end inductor, the second end of the second amplification end inductor is connected with a second power supply end, and the third end of the second differential amplification transistor is used as the second amplification grounding end.
6. The push-pull power amplification circuit of claim 5, wherein the first differential amplification transistor is a BJT transistor comprising a base, a collector and an emitter, the base of the first differential amplification transistor being used as the input terminal of the first amplification unit; a collector of the first differential amplification transistor is connected with the first amplification end inductor, and an emitter of the first differential amplification transistor is used as the first amplification grounding end;
the second differential amplification transistor is a BJT (bipolar junction transistor) and comprises a base electrode, a collector electrode and an emitter electrode, and the base electrode of the second differential amplification transistor is used as the input end of the second amplification unit; and the collector of the second differential amplification transistor is connected with the second amplification end inductor, and the emitter of the second differential amplification transistor is used as the second amplification grounding end.
7. Push-pull power amplification circuit according to claim 6, wherein the first amplification unit further comprises a first metal region provided at one side of the first differential amplification transistor; at least one first through hole is formed in the first metal area; an emitter of the first differential amplification transistor is connected with the first metal area and is grounded through the first through hole of the first metal area; the second amplifying unit further includes a second metal region disposed at one side of the second differential amplifying transistor; at least one second through hole is formed in the second metal area; the emitter of the second differential amplifier transistor is connected with the second metal area and grounded through the second through hole of the second metal area.
8. Push-pull power amplification circuit according to claim 7, wherein the number of the first through holes and the number of the second through holes are the same.
9. The push-pull power amplification circuit of claim 1, further comprising a second stage differential amplification circuit comprising a third bias amplification unit and a fourth bias amplification unit, an output of the third bias amplification unit coupled to an input of the first bias amplification unit, and an output of the fourth bias amplification unit coupled to an input of the second bias amplification unit.
10. A push-pull power amplifier chip, characterized in that the push-pull power amplifier chip comprises a push-pull power amplifier circuit according to any one of claims 1 to 9.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117353683A (en) * | 2022-06-28 | 2024-01-05 | 锐石创芯(深圳)科技股份有限公司 | Radio frequency front end module and electronic equipment |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103368601A (en) * | 2013-06-03 | 2013-10-23 | 深圳清华大学研究院 | Front end of wireless communication transceiver |
| CN104506150A (en) * | 2014-10-30 | 2015-04-08 | 华为技术有限公司 | Ultralow working voltage rail to rail operational amplifier, differential input amplification stage circuit and output stage circuit |
| CN112187194A (en) * | 2020-09-30 | 2021-01-05 | 锐石创芯（深圳）科技有限公司 | Push-pull power amplifier, radio frequency front-end circuit and wireless device |
| CN112838832A (en) * | 2020-12-31 | 2021-05-25 | 锐石创芯（深圳）科技有限公司 | Differential amplification circuit |
| CN112968679A (en) * | 2021-02-08 | 2021-06-15 | 锐石创芯（深圳）科技有限公司 | Push-pull power amplification system and radio frequency front-end module |
| CN113193844A (en) * | 2021-05-31 | 2021-07-30 | 锐石创芯（深圳）科技有限公司 | Push-pull power amplifying circuit |
-
2021
- 2021-09-09 CN CN202111054176.1A patent/CN113922762A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103368601A (en) * | 2013-06-03 | 2013-10-23 | 深圳清华大学研究院 | Front end of wireless communication transceiver |
| CN104506150A (en) * | 2014-10-30 | 2015-04-08 | 华为技术有限公司 | Ultralow working voltage rail to rail operational amplifier, differential input amplification stage circuit and output stage circuit |
| CN112187194A (en) * | 2020-09-30 | 2021-01-05 | 锐石创芯（深圳）科技有限公司 | Push-pull power amplifier, radio frequency front-end circuit and wireless device |
| CN112838832A (en) * | 2020-12-31 | 2021-05-25 | 锐石创芯（深圳）科技有限公司 | Differential amplification circuit |
| CN112968679A (en) * | 2021-02-08 | 2021-06-15 | 锐石创芯（深圳）科技有限公司 | Push-pull power amplification system and radio frequency front-end module |
| CN113193844A (en) * | 2021-05-31 | 2021-07-30 | 锐石创芯（深圳）科技有限公司 | Push-pull power amplifying circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117353683A (en) * | 2022-06-28 | 2024-01-05 | 锐石创芯(深圳)科技股份有限公司 | Radio frequency front end module and electronic equipment |
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Address after: 518000 room 2001, building 3, Shenzhen new generation industrial park, 136 Zhongkang Road, Meidu community, Meilin street, Futian District, Shenzhen City, Guangdong Province Applicant after: Ruishi Chuangxin (Shenzhen) Technology Co.,Ltd. Address before: 518000 room 2001, building 3, Shenzhen new generation industrial park, 136 Zhongkang Road, Meidu community, Meilin street, Futian District, Shenzhen City, Guangdong Province Applicant before: AN ADVANCED RF POWER AMPLIFIER AND COMMUNICATION DEVICE |