CN113890783A - Data transmitting and receiving system and method, electronic equipment and storage medium - Google Patents
Data transmitting and receiving system and method, electronic equipment and storage medium Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
- H04L12/40013—Details regarding a bus controller
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/403—Bus networks with centralised control, e.g. polling
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L2012/40208—Bus networks characterized by the use of a particular bus standard
- H04L2012/40215—Controller Area Network CAN
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L2012/40267—Bus for use in transportation systems
- H04L2012/4028—Bus for use in transportation systems the transportation system being an aircraft
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Abstract
The application discloses a data receiving and transmitting system, a method, an electronic device and a storage medium, wherein the system comprises: the microcontroller sends a data receiving instruction to the processing unit through the first bus; the bus control unit receives target data of a target length from an external node in real time through a second bus; the processing unit puts the target data meeting the conditions into a cache for storage based on the read data identification; the processing unit judges whether the total data length of the target data stored in the cache reaches an interruption triggering length or not; if the interrupt trigger length is reached, the processing unit generates a first interrupt signal; the microcontroller reads the target data stored in the buffer memory based on the first interrupt signal. By adopting the data receiving and sending system, the data receiving and sending method, the electronic equipment and the storage medium, the problems that when a certain node on the CAN bus receives a large amount of data, the receiving time is long, and the data processing of the microcontroller is delayed due to triggering of multiple interrupts are solved.
Description
Technical Field
The present application relates to the field of data processing technologies, and in particular, to a data transceiving system, a data transceiving method, an electronic device, and a storage medium.
Background
A Controller Area Network (CAN) is a serial communication field bus, and is primarily used for data communication between a plurality of control and measurement instruments in an automobile, and with the application and popularization of the CAN bus, the CAN bus has the advantages of good real-time performance, high reliability, strong anti-interference capability and the like, is also recognized by the aerospace field, and is widely applied to the aerospace field. The CAN bus is introduced into an integrated electronic system at home and abroad, and a large number of micro satellites use the CAN bus as an on-satellite backbone network to complete information interaction between on-satellite equipment.
In the prior art, when satellite equipment is used as a node on a CAN bus to receive and transmit data, a microcontroller generally controls CAN bus data, the CAN controllers are integrated in most microcontrollers, and CAN bus communication is realized through the externally connected CAN transceivers. However, the communication frequency of the CAN bus is low, the reliable communication frequency of the high-speed CAN bus widely used in the aerospace field is only 500KHZ, and the operation dominant frequency of the high-speed CAN bus is 50MHz to 100MHz lower than that of the current mainstream microcontroller. Meanwhile, the main task of the microcontroller is not to transmit and receive data, but to analyze and compute the data packet, and when receiving data, the data processing task needs to be interrupted and the data transmitting and receiving task needs to be executed, where a single frame of data of the CAN bus only contains 8 bytes of target data, that is, each time the 8 bytes of target data are received, an interrupt needs to be triggered.
In the above data transmission and reception method, when a node on the CAN bus needs to receive a large amount of data, not only a long time is required, but also a problem occurs in that data processing of the microcontroller is delayed due to triggering multiple interrupts.
Disclosure of Invention
In view of the above, the present application provides a data transceiving system, a method, an electronic device, and a storage medium, which aims to receive all target data into a cache by using a node buffer, and complete the receiving of the target data by a microcontroller by triggering an interrupt once, thereby solving the problems that a node on a CAN bus receives a large amount of data for a long time and data processing of the microcontroller is delayed due to triggering multiple interrupts.
In a first aspect, an embodiment of the present application provides a data transceiving system, including a microcontroller and a node buffer, where the node buffer includes a processing unit and a bus control unit;
the microcontroller sends a data receiving instruction to the processing unit through the first bus, wherein the data receiving instruction comprises a data reading identifier;
the bus control unit receives target data of a target length from an external node in real time through a second bus;
the processing unit puts the target data meeting the conditions into a cache for storage based on the read data identification;
the processing unit judges whether the total data length of the target data stored in the cache reaches an interruption triggering length or not;
if the interrupt trigger length is reached, the processing unit generates a first interrupt signal and sends the first interrupt signal to the microcontroller;
the microcontroller reads the target data stored in the buffer memory based on the first interrupt signal.
Optionally, the clock frequency of the first bus is the same frequency as the master frequency of the microcontroller, and the communication rate of the first bus is higher than that of the second bus.
Optionally, the bus control unit generates a second interrupt signal every time the bus control unit receives target data of a target length from the external node through the second bus; and after detecting the second interrupt signal, the processing unit reads the target data with the target length from the bus control unit.
Alternatively, the processing unit may store the target data by: extracting a target data identifier carried by the target data from the read target data; determining whether the target data identification is consistent with the read data identification; if the target data identification is consistent with the read data identification, determining that the target data meets the condition, and storing the target data meeting the condition in a cache; and if the target data identification is not consistent with the read data identification, determining that the target data is not in accordance with the condition.
Optionally, the processing unit may include a first bus interface, a second bus interface, and an interrupt interface, the processing unit being connected to the bus interface of the microcontroller through the first bus interface to receive the data reception instruction from the microcontroller; the processing unit is connected to the bus interface of the bus control unit through the second bus interface so as to receive the target data from the bus control unit; the processing unit is connected to an interrupt trigger pin of the microcontroller through an interrupt interface to send a first interrupt signal to the microcontroller through the interrupt interface.
Optionally, the data transceiving system may further comprise a bus transceiver; wherein the bus control unit is connected to the bus transceiver through a second bus to receive the target data from the external node through the bus transceiver in real time.
In a second aspect, an embodiment of the present application provides a data synchronization method, including:
receiving a data receiving instruction from the microcontroller through the first bus, wherein the data receiving instruction comprises a read data identifier;
receiving target data of a target length from a bus control unit through a second bus;
based on the read data identification, putting the target data meeting the conditions into a cache for storage;
judging whether the total data length of the target data stored in the cache reaches an interruption triggering length or not;
and if the interrupt trigger length is reached, generating a first interrupt signal, and sending the first interrupt signal to the microcontroller so that the microcontroller reads the target data stored in the cache based on the first interrupt signal.
Optionally, the step of storing the qualified target data based on the read data identification may include: extracting a target data identifier carried by the target data from the read target data; determining whether the target data identification is consistent with the read data identification; if the target data identification is consistent with the read data identification, determining that the target data meets the condition, and storing the target data meeting the condition in a cache; and if the target data identification is not consistent with the read data identification, determining that the target data is not in accordance with the condition.
In a third aspect, an embodiment of the present application provides an electronic device, including: a processor, a memory and a bus, the memory storing machine-readable instructions executable by the processor, the processor and the memory communicating via the bus when the electronic device is operating, the machine-readable instructions being executable by the processor to perform the steps of the data transceiving method as described above.
In a fourth aspect, the present application provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and the computer program is executed by a processor to perform the steps of the data transceiving method.
The embodiment of the application brings the following beneficial effects:
the embodiment of the application provides a data transceiving system, a data transceiving method, electronic equipment and a storage medium, wherein the data transceiving system comprises a microcontroller and a node buffer, and the node buffer comprises a processing unit and a bus control unit; the microcontroller sends a data receiving instruction to the processing unit through the first bus, wherein the data receiving instruction comprises a data reading identifier; the bus control unit receives target data of a target length from an external node in real time through a second bus; the processing unit puts the target data meeting the conditions into a cache for storage based on the read data identification; the processing unit judges whether the total data length of the target data stored in the cache reaches an interruption triggering length or not; if the interrupt trigger length is reached, the processing unit generates a first interrupt signal and sends the first interrupt signal to the microcontroller; the microcontroller reads the target data stored in the buffer memory based on the first interrupt signal. According to the method and the device, all target data are received into the cache by using the node buffer, and the target data CAN be received by the microcontroller through one-time triggering interruption, so that the problems that a certain node on a CAN bus is long in receiving time when receiving a large amount of data, and data processing of the microcontroller is delayed due to triggering interruption for many times are solved.
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments are briefly described below, and it is obvious that the following drawings are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other related drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a first embodiment of a data transceiving system in the prior art;
fig. 2 is a schematic structural diagram of a second embodiment of a data transceiving system in the prior art;
fig. 3 is a schematic structural diagram of a data transceiving system according to an embodiment of the present application;
fig. 4 is a schematic hardware structure diagram of a node buffer according to an embodiment of the present disclosure;
fig. 5 is a schematic flowchart of a data transceiving method according to an embodiment of the present application;
fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
To make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions of the present application will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the prior art, when satellite equipment is used as a node on a CAN bus to receive and transmit data, a microcontroller generally controls CAN bus data, the CAN controllers are integrated in most microcontrollers, and CAN bus communication is realized through the externally connected CAN transceivers.
Fig. 1 is a schematic structural diagram of a first embodiment of a data transceiver system in the prior art, as shown in fig. 1, a microcontroller with a CAN function directly communicates with a CAN transceiver through a CAN bus and controls the CAN transceiver to receive and transmit data, however, the communication frequency that CAN be realized by the CAN bus is low, the reliable communication frequency of a high-speed CAN bus widely used in the aerospace field is only 500KHZ, which is lower than the operating main frequency of the current mainstream microcontroller by 50MHz to 100MHz, the method for directly connecting the microcontroller to the CAN transceiver to obtain effective data from the CAN bus binds the baud rate of data obtained by the microcontroller to the operating baud rate of the CAN bus, which reduces the data receiving efficiency, and when a certain node on the CAN bus needs to receive a large amount of data, it takes a long time to receive all the data. Meanwhile, the main task of the microcontroller is not to transmit and receive data, but to analyze and compute the data packet, when receiving data, the data processing task needs to be interrupted and then the data transmitting and receiving task is executed, and the single frame data of the CAN bus only contains 8 bytes of target data, that is, each time 8 bytes of target data are received, one interrupt needs to be triggered, if 128 bytes of data need to be received, 16 interrupts need to be triggered, which may cause the problem that the data processing of the microcontroller is delayed due to triggering multiple interrupts. In addition, when the amount of received data is large, the cache design of the data inside the microcontroller is also complex, and not only the data which is not completely processed needs to be stored, but also the data which triggers the receiving interruption at present needs to be cached, so that the cache logic of the receiving end needs to be optimally designed, and the algorithm complexity of the microcontroller is increased.
Fig. 2 is a schematic structural diagram of a second embodiment of a data transceiver system in the prior art, as shown in fig. 2, a microcontroller without a CAN function communicates with a CAN transceiver through a CAN controller, and transmits and receives data through the CAN transceiver, when the microcontroller transmits and receives data from a CAN bus, the microcontroller is required to perform chip timing operation on the CAN controller, which occupies chip pins and instruction resources of the microcontroller, and causes a problem of data processing delay of the microcontroller.
Based on this, embodiments of the present application provide a data transceiving system, method, electronic device, and storage medium, where a node buffer is used to receive all target data into a cache, and the target data CAN be received by a microcontroller through one-time triggering interrupt, so as to solve the problems that a certain node on a CAN bus receives a large amount of data for a long time, and data processing of the microcontroller is delayed due to triggering multiple interrupts.
To facilitate understanding of the present embodiment, first, a detailed description is given of a data transceiving system disclosed in the present embodiment, and fig. 3 is a schematic structural diagram of the data transceiving system provided in the present embodiment, as shown in fig. 3, the data transceiving system 10 includes a microcontroller 100, a node buffer 200, and a bus transceiver 300, and the node buffer 200 includes a processing unit 201 and a bus control unit 202.
The microcontroller 100 sends a data reception instruction to the processing unit 201 through the first bus. The data receiving instruction includes reading a data identification.
Specifically, when information interaction is performed between satellite devices, each device CAN be regarded as a node, the nodes communicate with each other through a CAN bus, when a certain node is to receive target data sent by an external node, the microcontroller 100 of the node serves as an upper computer and sends a data receiving instruction to the processing unit 201 through the first bus so as to instruct the processing unit 201 to execute a data receiving task, and after the processing unit 201 receives the data receiving instruction, the bus control unit 202 is controlled to receive the target data sent by the external node. In addition, if the microcontroller 100 does not require the node buffer 200 to operate, the microcontroller 100 may send a shutdown command to the node buffer 200 through the first bus, so that the node buffer 200 stops operating.
Illustratively, the first Bus may be an Advanced Peripheral Bus (APB Bus), and the clock frequency of the first Bus is the same frequency as the master frequency of the microcontroller, and it CAN be understood that since the clock frequency of the first Bus is the same frequency as the master frequency of the microcontroller, the microcontroller 100 is no longer limited by the baud rate when reading and writing the CAN Bus data, and the efficiency of reading and writing the data of the microcontroller 100 is improved. The processing unit 201 may be a Field Programmable Gate Array (FPGA) capable of receiving a data receiving instruction sent by the microcontroller 100 and controlling the bus control unit 202 to receive target data sent by an external node according to the data receiving instruction, and the bus control unit 202 may be a CAN controller and together with the processing unit 201, forms the node buffer 200. It is understood that the node buffer 200 performs the transceiving process of data on the CAN bus, and the microcontroller 100 only needs to perform data writing or reading operation on a specific address, which not only simplifies the interrupt processing operation of the microcontroller 100, but also frees up the instruction resources of the bus processing consumed by the microcontroller 100 when receiving data.
In one example, the sending of the data receiving instruction is implemented by the microcontroller 100 by writing data to specific addresses, each specific address corresponding to a specific function, for example: the address 0x00 is used for controlling the enabling of the CAN bus node buffer 200, the bit width is 2 bits, the low bit 1 is open, and 0 is closed; the high level 1 is a CAN extended frame, and 0 is a CAN standard frame. Address 0x10 is used to set the interrupt trigger length, the bit width is related to the depth of the receiving interrupt buffer, if the depth of the receiving buffer is 128 bytes, the bit width is 8 bits, and the value is the interrupt trigger length, for example: if the total length of the target data is 9 bytes, this interrupt trigger length may be set to 9. The address 0x20 is used to read the target data in the buffer, and has a bit width of 8 bits, and when reading the address 0x20, the target data in the receiving buffer will be sent to the first bus in a first-in-first-out manner. The address 0x30 is used to write the target data into the issue buffer, and has a bit width of 8 bits, and when writing bytes into 0x30, the target data will be written into the issue buffer byte by byte. The address 0x40 is used for transmission control, has a bit width of 1 bit, and when 0x01 is written into the address 0x40, enables the transmission function to transmit target data in the transmission buffer onto the second bus one by one according to the transmission logic of the bus controller 202. The address 0x50 is used to set the read data identification, and the processing unit 201 will filter the target data according to the read data identification.
The bus control unit 202 receives target data of a target length in real time from an external node through the second bus.
Specifically, the bus control unit 202 is connected to the bus transceiver 300 through a second bus, so as to receive the target data from the external node through the bus transceiver 300 in real time, the bus control unit 202 generates a second interrupt signal every time the bus control unit 202 receives the target data of the target length from the external node through the second bus, and the processing unit 201 reads the target data of the target length from the bus control unit 202 after detecting the second interrupt signal.
Illustratively, the second bus may be a CAN bus, the communication rate of the first bus is higher than that of the second bus, the bus transceiver 300 may be a CAN transceiver, the data received by the bus control unit 202 from the external node in real time is a CAN data frame, the CAN data frame includes the target data identifier and the target data, the length of the target data is 8 bytes, and the 8 bytes are the target length of the target data. The bus control unit 202 triggers a hardware reception interrupt every time it receives 8 bytes of target data, the hardware reception interrupt is a second interrupt signal, the processing unit 201 detects whether the bus control unit 202 triggers the hardware reception interrupt, and if it is detected that the bus control unit 202 triggers the hardware reception interrupt, the 8 bytes of target data are read from the bus control unit 202.
Taking the above example as an example, the processing unit 201 is an FPGA, the bus control unit 202 is a CAN controller, the processing unit 201 sets the trigger mode as falling edge trigger, CAN sense the level change of the hardware reception interrupt pin in real time, and if the falling edge from high level to low level of the hardware reception interrupt pin is triggered, the processing unit 201 reads the target data from the bus control unit 202.
The processing unit 201 stores the eligible target data in the cache based on the read data identifier.
Specifically, after the processing unit 201 reads the target data from the bus control unit 202, the processing unit extracts the target data identifier carried by the target data from the read target data, determines whether the target data identifier is consistent with the read data identifier, determines that the target data meets the condition if the target data identifier is consistent with the read data identifier, and stores the target data meeting the condition in the cache, and determines that the target data does not meet the condition if the target data identifier is not consistent with the read data identifier.
Taking the above example as an example, if the read data identifier in the data receiving command sent by the microcontroller 100 is ID3, the processing unit 201 will extract the target data identifier from the received CAN data frame, determine whether the target data identifier and the read data identifier are both ID3, if the target data identifier and the read data identifier are both ID3, determine that the target data is eligible, and put the target data into the buffer for storage, and if the target data identifier is not ID3, determine that the target data is ineligible, filter the target data, and do not store the target data in the buffer. The cache includes a receiving cache and a sending cache, and when receiving the target data, the target data is stored in the receiving cache, and when sending the target data, the target data is stored in the sending cache.
The processing unit 201 determines whether the total data length of the target data stored in the cache memory reaches the interrupt trigger length.
Specifically, the data receiving instruction further includes an interrupt trigger length, where the interrupt trigger length is also written into the designated address by the microcontroller 100, and the processing unit 201 determines whether the total data length of the target data stored in the cache memory reaches the length of the data to be received by the microcontroller 100 according to the interrupt trigger length.
If the interrupt trigger length is reached, the processing unit 201 generates a first interrupt signal and sends the first interrupt signal to the microcontroller 100.
Specifically, if the processing unit 201 determines that the total data length of the target data stored in the cache memory reaches the interrupt trigger length, a first interrupt signal is generated, and the processing unit 201 is connected to the interrupt trigger pin of the microcontroller 100 through the interrupt interface to send the first interrupt signal to the microcontroller 100 through the interrupt interface, and if the processing unit 201 determines that the total data length of the target data stored in the cache memory does not reach the interrupt trigger length, the data receiving process is repeatedly performed until the total data length of the target data stored in the cache memory reaches the interrupt trigger length. It should be noted that the processing unit 201 may include a first bus interface, a second bus interface, and an interrupt interface, the processing unit 201 is connected to the bus interface of the microcontroller 100 through the first bus interface to receive a data receiving instruction from the microcontroller 100, the processing unit 201 is connected to the bus interface of the bus control unit 202 through the second bus interface to receive target data from the bus control unit 202, and the processing unit 201 is connected to an interrupt trigger pin of the microcontroller 100 through the interrupt interface to send a first interrupt signal to the microcontroller 100 through the interrupt interface.
Taking the above example as an example, if the processing unit 201 determines that the total data length of the target data stored in the buffer memory reaches 9 bytes, the processing unit 201 generates a first interrupt signal and sends the first interrupt signal to the microcontroller 100 through the interrupt interface.
The microcontroller 100 reads the target data stored in the buffer based on the first interrupt signal.
Specifically, after receiving the first interrupt signal, the microcontroller 100 reads all the target data byte by byte from the buffer. It CAN be understood that the microcontroller 100 CAN read all data from the cache through one interrupt processing, which not only CAN simplify the processing function of the CAN bus for receiving the interrupt, but also CAN avoid the problem that the microcontroller 100 cannot process the main task in time due to triggering multiple interrupts when receiving a large amount of data.
The data transceiving system 10 can also implement a function of the microcontroller 100 to transmit data to an external node. Here, the microcontroller 100 transmits a transmission data command to the processing unit 201 through the first bus, and directly writes all target data to be transmitted into the transmission buffer, the processing unit 201 detects whether the transmission buffer is empty, and if the transmission buffer is not empty, automatically reads the target data from the transmission buffer, packetizes the read target data, and then transmits the packetized target data to the bus control unit 202 in the form of a data frame, and the bus control unit 202 transmits the target data to an external node through the bus transceiver 300. Here, packetizing processing is performed in accordance with a target length, which is still 8 bytes in the above example, and if target data to be transmitted is 10 bytes, the target data is divided into 2 packets, and the 2 packets respectively include data of 8 bytes and data of 2 bytes, and then the 2 packets are transmitted to the external node via the bus controller 202.
Fig. 4 is a schematic diagram of a hardware structure of a node buffer provided in the embodiment of the present application, and as shown in fig. 4, a processing unit 201 selects an FPGA, a bus control unit 202 selects an SJA1000T chip, and a bus transceiver selects a CAN transceiver, since an operating voltage of the SJA1000T is 5V, and a pin level of the FPGA is mostly 3.3V or less, a level conversion chip is added between the FPGA and the SJA1000T chip to implement conversion of a pin level standard. The SJA1000T chip implements the address data bus multiplexing method, so the time-sharing multiplexing pin is a tri-state gate pin with direction control, and the level conversion chip is also required to have the function of bidirectional level conversion for transceiving. Combining these requirements, the level shifting chip is identified as SN74LVC16T 245.
Here, the level protocol conversion chip SN74LVC16T245 has 2 partitions, and can independently control the signal transmission direction and the level conversion protocol. Because the signal transmission direction in the node buffer comprises three conditions, namely transmission from the FPGA to SJA1000T, transmission from SJA1000T to the FPGA and bidirectional transmission time division multiplexing, the three partitions utilizing the 2-chip SN74LVC16T245 are respectively adapted to the three conditions.
Therefore, when the node buffer is matched with the microcontroller and the CAN transceiver for use, the external interface only has CAN bus interfaces CANH and CANL at the bus transceiver end, which are consistent with the interface of the CAN bus realized by the microcontroller by utilizing an internal CAN control algorithm to be matched with the CAN transceiver, the node buffer CAN be directly compatible with the node design of the original CAN bus, and has good compatibility.
Fig. 5 is a schematic flowchart of a data transceiving method according to an embodiment of the present application, where the data transceiving method may be executed in the processing unit 201 in the data transceiving system, as shown in fig. 5, the method includes:
And step 403, based on the read data identifier, putting the target data meeting the conditions into a cache for storage.
In step 404, it is determined whether the total data length of the target data stored in the cache reaches the interrupt trigger length.
If the interrupt trigger length is reached, step 405 is executed: and generating a first interrupt signal and sending the first interrupt signal to the microcontroller so that the microcontroller reads the target data stored in the cache based on the first interrupt signal.
If the interrupt trigger length is not reached, step 406 is performed: and continuously receiving target data with the target length from the external node in real time.
Because the principle of solving the problem of the method in the embodiment of the present application is similar to that of the data transceiving system in the embodiment of the present application, the implementation of the method can refer to the implementation of the system, and repeated details are not repeated.
Corresponding to the data transceiving method in fig. 5, an embodiment of the present application further provides a schematic structural diagram of an electronic device 500, where the electronic device 500 may be the processing unit 201 in the data transceiving system 10, as shown in fig. 6, and the electronic device 500 includes a processor 510, a memory 520, and a bus 530. The memory 520 stores machine-readable instructions executable by the processor 510, when the electronic device 500 operates, the processor 510 communicates with the memory 520 through the bus 530, and when the machine-readable instructions are executed by the processor 510, the data transceiving method CAN be executed, all target data are received into a cache by using a node buffer, and the target data CAN be received by the microcontroller through triggering interrupt once, so that the problems that a certain node on a CAN bus has a long receiving time when receiving a large amount of data, and data processing of the microcontroller is delayed due to triggering multiple interrupts are solved.
Corresponding to the data transceiving method in fig. 5, an embodiment of the present application further provides a computer readable storage medium, where a computer program is stored on the computer readable storage medium, and the computer program is executed by a processor to perform the steps of the data transceiving method.
Specifically, the storage medium CAN be a general storage medium, such as a mobile disk, a hard disk, and the like, when a computer program on the storage medium is run, the data transceiving method CAN be executed, all target data are received into a cache by using a node buffer, and the target data CAN be received by the microcontroller by triggering interrupt once, so that the problems that a certain node on a CAN bus receives a large amount of data for a long time, and data processing of the microcontroller is delayed due to triggering interrupt for many times are solved.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the foregoing systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, a division of a unit is merely a division of one logic function, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments provided in the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing an electronic device (which may be a personal computer, a server, or a network device) to perform all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus once an item is defined in one figure, it need not be further defined and explained in subsequent figures, and moreover, the terms "first", "second", "third", etc. are used merely to distinguish one description from another and are not to be construed as indicating or implying relative importance.
Finally, it should be noted that: the above-mentioned embodiments are only specific embodiments of the present application, and are used for illustrating the technical solutions of the present application, but not limiting the same, and the scope of the present application is not limited thereto, and although the present application is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: any person skilled in the art can modify or easily conceive the technical solutions described in the foregoing embodiments or equivalent substitutes for some technical features within the technical scope disclosed in the present application; such modifications, changes or substitutions do not depart from the spirit and scope of the exemplary embodiments of the present application, and are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A data transceiving system, characterized in that the data transceiving system comprises a microcontroller and a node buffer, the node buffer comprises a processing unit and a bus control unit;
the microcontroller sends a data receiving instruction to the processing unit through the first bus, wherein the data receiving instruction comprises a data reading identifier;
the bus control unit receives target data of a target length from an external node in real time through a second bus;
the processing unit puts the target data meeting the conditions into a cache for storage based on the read data identification;
the processing unit judges whether the total data length of the target data stored in the cache reaches an interruption triggering length or not;
if the interrupt trigger length is reached, the processing unit generates a first interrupt signal and sends the first interrupt signal to the microcontroller;
the microcontroller reads the target data stored in the buffer memory based on the first interrupt signal.
2. The data transceiving system of claim 1, wherein a clock frequency of the first bus is the same frequency as a master frequency of the microcontroller, and a communication rate of the first bus is higher than a communication rate of the second bus.
3. The data transceiving system of claim 1, wherein the bus control unit generates a second interrupt signal every time target data of a target length is received from the external node through the second bus;
and after detecting the second interrupt signal, the processing unit reads the target data with the target length from the bus control unit.
4. A data transceiving system according to claim 3, wherein the processing unit stores the target data by:
extracting a target data identifier carried by the target data from the read target data;
determining whether the target data identification is consistent with the read data identification;
if the target data identification is consistent with the read data identification, determining that the target data meets the condition, and storing the target data meeting the condition in a cache;
and if the target data identification is not consistent with the read data identification, determining that the target data is not in accordance with the condition.
5. The data transceiving system of claim 1, wherein the processing unit comprises a first bus interface, a second bus interface, and an interrupt interface,
the processing unit is connected to a bus interface of the microcontroller through a first bus interface so as to receive a data receiving instruction from the microcontroller;
the processing unit is connected to the bus interface of the bus control unit through the second bus interface so as to receive the target data from the bus control unit;
the processing unit is connected to an interrupt trigger pin of the microcontroller through an interrupt interface to send a first interrupt signal to the microcontroller through the interrupt interface.
6. The data transceiving system of claim 1, wherein the data transceiving system further comprises a bus transceiver;
wherein the bus control unit is connected to the bus transceiver through a second bus to receive the target data from the external node through the bus transceiver in real time.
7. A data transceiving method, characterized in that the data transceiving method comprises:
receiving a data receiving instruction from a microcontroller through a first bus, wherein the data receiving instruction comprises a reading data identifier;
receiving target data of a target length from a bus control unit through a second bus;
based on the read data identification, putting the target data meeting the conditions into a cache for storage;
judging whether the total data length of the target data stored in the cache reaches an interruption triggering length or not;
and if the interrupt trigger length is reached, generating a first interrupt signal, and sending the first interrupt signal to the microcontroller so that the microcontroller reads the target data stored in the cache based on the first interrupt signal.
8. The data transceiving method of claim 7, wherein the storing of the eligible target data based on the read data identification comprises:
extracting a target data identifier carried by the target data from the read target data;
determining whether the target data identification is consistent with the read data identification;
if the target data identification is consistent with the read data identification, determining that the target data meets the condition, and storing the target data meeting the condition in a cache;
and if the target data identification is not consistent with the read data identification, determining that the target data is not in accordance with the condition.
9. An electronic device comprising a processor, a memory and a bus, the memory storing machine-readable instructions executable by the processor, the processor and the memory communicating over the bus when the electronic device is run, the machine-readable instructions when executed by the processor performing the steps of the data transceiving method according to claim 7 or 8.
10. A computer-readable storage medium, characterized in that the computer-readable storage medium has stored thereon a computer program which, when being executed by a processor, carries out the steps of the data transceiving method according to claim 7 or 8.
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