CN105243033A - Data processing method and electronic device - Google Patents
Data processing method and electronic device Download PDFInfo
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- CN105243033A CN105243033A CN201510629598.5A CN201510629598A CN105243033A CN 105243033 A CN105243033 A CN 105243033A CN 201510629598 A CN201510629598 A CN 201510629598A CN 105243033 A CN105243033 A CN 105243033A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/16—Memory access
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/36—Arbitration
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention discloses a data processing method and an electronic device. The method comprises: based on a priority of instructions in an instruction queue buffer, selecting an executable instruction, and aimed at the selected instruction, transmitting a bus request to request for a bus; when the bus is received by the request, transmitting the executable instruction to a corresponding target memory unit in a memory by using the bus, reading timing information of the executable instruction to a polling queue buffer; when random timing information in the polling queue buffer is arrived, transmitting the bus request to request for the bus, so that when the bus is received by the request, by using the bus, whether the target memory unit corresponding to the instruction that the timing information belongs to is executed is inquired; and when the bus is free, based on a preset policy, performing arbitration on the received bus, and based on an arbitration result, distributing the bus. By implementing the data processing method, out-of-order execution of the instructions in the memory units can be implemented in an efficient and low-power way, thus increasing the bus utilization rate and further increasing the read and write speed of the memory.
Description
Technical field
The present invention relates to memory technology, particularly relate to a kind of data processing method and electronic equipment.
Background technology
Electronic equipment such as smart mobile phone, panel computer etc. generally use flash memory (Flash) if the storage unit such as NANDflash are as storage medium, flash memory from top under framework be: chip (Chip), logical block (LU), sheet (Plane), block (Block), page (Page), the framework (except the bottom) on each upper strata can comprise the framework of one or more lower floor, and such as a chip can comprise one or more logical block; Wherein logical block can adopt logical unit number (LUN, LogicUnitNumber) identify, be the base unit of erasing with block in flash memory, with the addressing unit (also namely page is the base unit of read operation) that page is basic, wherein, logical block is can minimum (substantially) unit of instruction of separate responses processor;
A characteristic feature of flash disk operation is that the time of each storage unit execution needed for instruction, also namely delay (latency) was larger, the delay of such as reading page (Page) in chip is Microsecond grade (as 50us), be Microsecond grade (as 500us) to the delay that namely (Program) also write data of programming of page in chip, in chip, the delay of block erasing (BlockErase) is millisecond (ms) level; Be idle in the bus of timing period electronic equipment, in order to improve bus utilization, correlation technique introduces interleaved pages programming (InterleavePageProgram) technology;
Example is read as with page, for same logical block, at a time can only read the page of in this logical block, sending reading command to make this logical block perform to read data and in the waiting time returned by bus to logical block, instruction (such as inserting the instruction that the page of other logical blocks is read) can be sent by bus other logical block in flash memory, thus achieve the Out-of-order execution of the instruction between Different Logic unit, also the instruction sent after being may complete early than the instruction first sent (logical block performing transmission instruction is different logical blocks from the logical block sending instruction after execution).
By using following scheme to realize interleaved pages programming technique in correlation technique:
1) realized by microcode, need very large buffer memory (SRAM), and independent SRAM space is needed to the passage of each logic unit operation; Microcode Design is complicated simultaneously, amendment difficulty, and it is more difficult that the Out-of-order execution for different instruction realizes;
2) realized by processor (CPU) scheduling, processor is needed to safeguard queue, carry out alternately by interrupting with flash memory, and need the state of inquiring about flash memory, therefore limited speed, is not suitable for the occasion that bandwidth requirement is higher, poor real, require also higher to processor performance, thus cause the high power consumption of processor.
To sum up, realize the Out-of-order execution of instruction for mode that is efficient, low-power consumption, to promote the utilization factor of bus, and then promote the read or write speed to flash memory, correlation technique there is no effective solution.
Summary of the invention
The embodiment of the present invention provides a kind of data processing method and electronic equipment, can efficiently, the mode of low-power consumption realizes the Out-of-order execution of instruction, to promote the utilization factor of bus, and then promotes the read or write speed to storer.
The technical scheme of the embodiment of the present invention is achieved in that
The embodiment of the present invention provides a kind of data processing method, and described method comprises:
Priority based on instruction in instruction queue buffer memory chooses executable instruction, sends bus request to ask bus for selected instruction;
In request to being sent Destination Storage Unit corresponding in described executable instruction to storer during bus by bus, and the clocking information of described executable instruction is read to snoop queue buffer memory;
In described snoop queue buffer memory, arbitrary clocking information sends bus request to ask bus after arriving, and with when asking bus, whether the Destination Storage Unit corresponding to instruction being inquired about described clocking information ownership by bus is finished;
The bus request received is arbitrated based on preset strategy when bus free, and based on arbitration result distribution bus.
The embodiment of the present invention provides a kind of electronic equipment, and described electronic equipment comprises:
Command supervisor, for choosing executable instruction based on the priority of instruction in instruction queue buffer memory, sends bus request to ask bus for selected instruction;
Interface controller, in described command supervisor request to be sent in described executable instruction to storer corresponding Destination Storage Unit during bus by bus, and the clocking information of described executable instruction is read to snoop queue buffer memory;
Poll manager, bus request is sent to ask bus after arriving for clocking information arbitrary in described snoop queue buffer memory, with when asking bus, by described interface controller, to inquire about described clocking information ownership via bus instruction corresponding to Destination Storage Unit whether be finished;
Moderator, for arbitrating the bus request received based on preset strategy when bus free, and based on arbitration result distribution bus.
In the embodiment of the present invention, by the data processing structure of pure hardware implementing (FPGA or CPLD realization) to from host side write command and read instruction and respond, arbitrated based on the bus of preset strategy to the free time by moderator, executable instruction is sent to Destination Storage Unit to realize reading and writing data according to arbitration result, or whether to be finished the instruction sent according to arbitration result query aim storage unit; Thus the interactive operation achieved different storage unit, execution efficiency and real-time high.
Accompanying drawing explanation
Fig. 1 is the structural representation one of electronic equipment in the embodiment of the present invention;
Fig. 2 is the structural representation two of electronic equipment in the embodiment of the present invention;
Fig. 3 is the realization flow schematic diagram one of data processing method in the embodiment of the present invention;
Fig. 4 is the realization flow schematic diagram two of data processing method in the embodiment of the present invention;
Fig. 5 is the realization flow schematic diagram three of data processing method in the embodiment of the present invention;
Fig. 6 is the realization flow schematic diagram four of data processing method in the embodiment of the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.
The electronic equipment that the embodiment of the present invention is recorded can be implemented in a variety of manners, such as, above-mentioned electronic equipment can be smart mobile phone, panel computer, notebook computer or Wearable (as intelligent glasses, intelligent watch etc.), and the operating system of electronic equipment can be Android operation system, the operating system (as mobile edition linux system, blackberry, blueberry QNX operating system etc.) that can run on micro-computer architecture (at least comprising processor and internal memory) of IOS or other any third parties exploitation; Above-mentioned electronic equipment can also be the electronic equipment for storing data such as solid state hard disc.
By arranging the data processing method of logic-based programmable gate array (FPGA) or the record of Complex programmable logical device (CPLD) the technology enforcement embodiment of the present invention in electronic equipment, see Fig. 1, the electronic equipment implementing the data processing method that the embodiment of the present invention is recorded at least comprises following functions unit: command supervisor 200, interface controller 300, moderator 100, storer 400 and poll manager 500; Above-mentioned functions unit constitutes the data processing structure of response data read-write in electronic equipment; As front, above-mentioned command supervisor 200, interface controller 300, moderator 100 and poll manager 500 logic-based programmable gate array or Complex programmable logical device realize, there is independently data processing structure and data store organisation, above-mentioned storer 400 is for storing the main devices of data in electronic equipment, can be realized by flash memory (as NandFlash);
Certainly, according to the specific product form of electronic equipment, as shown in Figure 2, processor (CPU) 600 can also be comprised in electronic equipment, when electronic equipment is smart mobile phone, panel computer, this processor uses as application processor (AP), be responsible for carrying out data processing between data processing structure and the application layer of electronic equipment operating system, such as read instruction according to the read request of application layer to the transmission of above-mentioned data structure, corresponding for data structure data are passed to application layer; Or send write command according to the write request of application layer to above-mentioned data structure, make data structure write target data; That is, data processing structure be to come self processor 600 read instruction or write command responds, main frame (Host) end is equivalent to for processor data processing structure.
Based on the electronic equipment shown in Fig. 1 and Fig. 2, see Fig. 3, the data processing method that the embodiment of the present invention is recorded is realized by following steps:
Step 101, command supervisor 200 chooses executable instruction based on the priority of instruction in instruction queue buffer memory, sends bus request to ask bus for selected instruction.
Command supervisor 200 reads instruction (the also namely pending instruction for storer 400 from processor 600, comprise and read instruction and write command), and the instruction queue buffer memory instruction of acquisition being stored in command supervisor 200 is (as front, instruction queue buffer memory is the buffer structure realized with FPGA or CPLD), the quantity of the instruction that command supervisor 200 reads from processor 600 depends on the quantity of the instruction that can store the instruction queue buffer memory of command supervisor 200, when the instruction of in instruction queue buffer memory is sent to Destination Storage Unit in storer 400 by interface controller 300 by command supervisor 200, (interface controller 300 produces clock signal according to instruction, Destination Storage Unit is made to perform instruction) and after being finished by Destination Storage Unit, instruction corresponding in command supervisor 200 meeting delete instruction queue buffer memory, and read from processor 600 tail of the queue that an instruction is stored to instruction queue buffer memory, storage unit 400 refers in storer 400 can the base unit (as logical block, a storage unit at a time can only respond an instruction of self processor 600) of answer processor 600 instruction.
In instruction queue buffer memory, the format sample of each instruction is as shown in table 1:
| Command identification (ID) | Part can be performed | Poll identifies | Stand-by period |
Table 1
See table 1, each instruction in instruction queue buffer memory comprises:
1) command identification, for the instruction that unique identification reads from processor 600;
2) part can be performed, namely executable instruction field;
3) poll mark, after showing that this instruction is sent to Destination Storage Unit (also namely performing the storage unit of this instruction), is finished the need of being inquired about this instruction by bus;
The stand-by period of reading the instruction (instruction as reading cells ID) outside instruction and write command is shorter, can think after such instruction is sent to Destination Storage Unit and be finished, command supervisor 200 can according to priority, (sequencing that the priority and instruction of the instruction of instruction queue buffer memory reads to instruction queue buffer memory be consistent from instruction queue buffer memory, the priority being namely introduced into the instruction of instruction queue buffer memory higher than after enter the priority of the instruction of instruction queue buffer memory) extract to should Destination Storage Unit instruction (if existence) and be sent to this Destination Storage Unit by interface controller 300 and perform, therefore, the poll reading instruction outside instruction and write command corresponding is designated no, (after transmission, namely think that instruction is finished by Destination Storage Unit) after presentation directives is sent to Destination Storage Unit, the instruction sent by bus inquiry is not needed whether to be finished by Destination Storage Unit,
It is relatively long that storage unit 400 performs the stand-by period of reading instruction and write command needs, after command supervisor 200 reads instruction or write command to Destination Storage Unit by interface controller 300 transmission, the instruction sent by bus inquiry is needed whether whether to be finished (such as Destination Storage Unit is finished for preparing state representation instruction, and Destination Storage Unit is that busy state characterizing instructions is not yet finished) by Destination Storage Unit; Therefore, the poll reading instruction and write command is designated and is, characterizing instructions manager 200 also needs inquiry (to be inquired about by poll manager 500 after sending instruction to Destination Storage Unit by interface controller 300, follow-uply to be described) whether the instruction that sends be finished, just extract from instruction queue buffer memory when being finished to should Destination Storage Unit instruction (if existence) and be sent to this Destination Storage Unit by interface controller 300 and perform.
The priority of command supervisor 200 instruction in based on instruction buffer queue is (as front, the priority and instruction of the instruction of instruction queue buffer memory is stored to the sequence consensus of instruction queue buffer memory, the priority being namely introduced into the instruction of instruction queue buffer memory higher than after enter the priority of the instruction of instruction queue buffer memory) choose executable instruction time, in the storer 400 also needing referenced interface controller 300 to transmit to command supervisor 200, (state of storage unit comprises the standby condition that can perform instruction for the status information of each storage unit, and performing the busy state of instruction),
Wherein, interface controller 300 often sends once command (also namely producing corresponding clock signal) to the storage unit in storer 400 or executes the status poll of a storage unit, just can by the state transfer of storage unit each in storer 400 to command supervisor 200, command supervisor 200 is according to the status information of storage unit 400 each in storer 400, whether the Destination Storage Unit that in decision instruction queue buffer memory, the instruction of limit priority is corresponding is in standby condition, if so, then judge that the instruction of limit priority is as executable instruction, if not, whether the Destination Storage Unit that then instruction of continuation judgement time high priority is corresponding is in standby condition, until judge the Destination Storage Unit being in standby condition, and be that the instruction of the limit priority of the Destination Storage Unit being in standby condition is defined as executable instruction by Action Target, bus is asked to moderator 100, after moderator 100 distribution bus, executable instruction instruction is sent to interface controller 300 in request to during bus by (process of moderator 100 distribution bus illustrates in step 105), to make Interface Controller, executable instruction is sent to Destination Storage Unit (clock signal namely making interface controller 300 produce corresponding instruction makes Destination Storage Unit perform).
Step 102, command supervisor 200 is when asking bus, by interface controller 300 and via Destination Storage Unit corresponding in bus transmission executable instruction to storer 400, and by interface controller 300, the clocking information of executable instruction is read to snoop queue buffer memory.
Command supervisor 200 sends executable instruction to interface controller 300 when asking bus by bus, produce clock signal corresponding to executable instruction by interface controller 300 and sent to by bus Destination Storage Unit to perform instruction (executable instruction) to make Destination Storage Unit, as front, interface controller 300 send instruction (executable instruction) for need when reading instruction or write command query aim storage unit whether be finished send instruction, with the new instruction sent after determining to be finished, Given this, after sending executable instruction to Destination Storage Unit, see Fig. 4, interface controller 300 performs following process for different executable instructions:
Step 201, executable instruction resolved by interface controller 300, obtains the poll mark of executable instruction.
Step 202, if poll mark characterizes the state (characterizing instructions is for reading instruction or write command) of the Destination Storage Unit that executable instruction needs inquiry corresponding, then the clocking information of executable instruction (can be the time delay of executable instruction) is read to snoop queue buffer memory (whether performing instruction graduates with the object element that the instruction belonged to based on each clocking information of snoop queue caching query by poll manager 500 is corresponding) by interface controller 300, and in instruction queue buffer memory, delete executable instruction; After interface controller 300 deletes executable instruction from the instruction queue buffer memory of command supervisor 200, command supervisor 200 also reads from processor 600 tail of the queue that pending instruction is filled to instruction queue buffer memory.
Step 203, if (characterize executable instruction is read the instruction outside instruction and write command to the state of the Destination Storage Unit that poll mark sign executable instruction does not need inquiry corresponding, send in executable instruction and can think that instruction is finished), in instruction queue buffer memory, delete executable instruction; After interface controller 300 deletes executable instruction from the instruction queue buffer memory of command supervisor 200, command supervisor 200 also reads from processor 600 tail of the queue that pending instruction is filled to instruction queue buffer memory.
Step 103, sends bus request to ask bus after poll manager 500 arbitrary clocking information in snoop queue buffer memory arrives.
Snoop queue buffer memory is safeguarded by poll manager 500, and in snoop queue buffer memory, the example of clocking information is as shown in table 2,
| Member 1 (command identification 1) | Member 2 (command identification 2) |
| Clocking information 1 (timer 1) | Clocking information 2 (timer 2) |
Table 2
See table 2, each clocking information in snoop queue buffer memory belongs to the instruction (executable instruction) that (correspondence) interface controller 300 sends, the prioritization of clocking information is corresponding with the sequencing that clocking information is read in instruction queue buffer memory by interface controller 300, the priority namely first reading to the clocking information in snoop queue buffer memory higher than after read to the priority of the clocking information in snoop queue buffer memory; When clocking information is read to snoop queue buffer memory, safeguarded the clocking information of each instruction by run timing device by poll manager 500, when each clocking information in snoop queue buffer memory arrives, ask bus with the arbitration making moderator 100 carry out bus assignment to moderator 100, whether to be finished by the Destination Storage Unit corresponding to the instruction of bus inquiry clocking information ownership when being assigned to bus.
Step 104, poll manager 500 is when asking bus, and whether the Destination Storage Unit corresponding to instruction being inquired about clocking information ownership by interface controller 300 is finished (executable instruction received).
In fact, poll manager 500 is the states coordinating query aim storage unit with interface controller 300, poll manager 500 makes the logical clock signal producing corresponding Destination Storage Unit status poll of interface controller 300, and make interface controller 300 by bus transmission timing signal, whether to be finished instruction to detect Destination Storage Unit.
See Fig. 5, whether the Destination Storage Unit corresponding to instruction being inquired about clocking information ownership by interface controller 300 is finished, and comprises the following steps:
Step 301, inquires about the state of the Destination Storage Unit corresponding to instruction of clocking information ownership by interface controller 300; When Destination Storage Unit is in standby condition, characterizes Destination Storage Unit and perform instruction graduates, perform step 302; When Destination Storage Unit is in busy state, characterizes Destination Storage Unit and perform instruction, perform step 303 and proceed to step 301.
Step 302, when poll manager 500 is finished by interface controller 300 Destination Storage Unit inquired corresponding to the instruction of clocking information ownership, without the need to the state of query aim storage unit again, deletes clocking information from snoop queue buffer memory.
Step 302, when poll manager 500 is not finished by interface controller 300 Destination Storage Unit inquired corresponding to the instruction of clocking information ownership, also need the state continuing query aim storage unit, therefore, upgrade the clocking information in snoop queue buffer memory and carry out timing process for the clocking information after upgrading; Alternatively, because Destination Storage Unit performs the time period corresponding to timing time for the executable instruction received, the time that Destination Storage Unit performs residing for instruction afterwards reduces relatively, if the stand-by period of the clocking information after upgrading is less than the stand-by period upgrading front timing time, will avoid not detecting that Destination Storage Unit is in the situation of standby condition in time, thus new instruction can be sent to Destination Storage Unit by interface controller 300 by command supervisor 200, promote the efficiency performing instruction.
Step 105, moderator 100 is arbitrated the bus request received based on preset strategy when bus free, and based on arbitration result distribution bus.
See step 101 and step 102, moderator 100 can receive the bus request from command supervisor 200, and see step 103 and step 104, moderator 100 can receive the bus request from poll manager 500; When to receive two bus request simultaneously, see Fig. 6, bus arbitration comprises following two kinds of situations:
Step 401, when receiving the bus request sent after arriving for the clocking information in snoop queue buffer memory for the bus request of executable instruction and poll manager 500 from command supervisor 200, it is the bus request distribution bus for executable instruction simultaneously.
That is, when command supervisor 200 and poll manager 500 send bus request to moderator 100 simultaneously, the priority of command supervisor 200 is always higher than the priority of poll manager 500.
Step 402, when receiving at least two bus request simultaneously sent after poll manager 500 arrives at least two clocking informations in snoop queue buffer memory, it is the bus request distribution bus of the clocking information for limit priority at least two clocking informations simultaneously.
The sequencing that priority and the clocking information of clocking information enter snoop queue buffer memory is consistent, the priority being namely introduced into the clocking information of snoop queue buffer memory higher than after enter the priority of the clocking information of snoop queue buffer memory.
The concrete example of carrying out data processing in conjunction with electronic equipment is more below described, and comprises the following steps:
Step 501, first command supervisor 200 is put into instruction queue buffer memory from host side (processor 600) reading command, sets up instruction queue buffer memory.
Step 502, command supervisor 200 is according to the state (state of each storage unit passes to command supervisor 200 by interface controller 300) of storage unit each in storer 400, from instruction queue buffer memory, choose executable instruction, propose bus request to moderator 100.
Step 503, moderator 100 carries out bus arbitration.
If Current bus is idle, and receiving only the bus request from command supervisor 200, is then command supervisor 200 distribution bus;
If receive two or more bus request simultaneously, then carry out bus arbitration according to the mode of abovementioned steps 105.
Step 504, after command supervisor 200 gets bus, by interface controller 300 perform instruction can the sequential of the corresponding instruction of the mitogenetic one-tenth of enforcement division to Destination Storage Unit; If poll is designated 1 (whether the Destination Storage Unit that sign needs query statement corresponding is finished), then command identification, clocking information are stored to snoop queue buffer memory; This instruction is deleted by command supervisor 200, reads an instruction (if existence) insert instruction queue buffer memory from host side
Step 501 to step 504 often performs once can add a clocking information (and mark of executable instruction corresponding to clocking information) in snoop queue buffer memory, while execution instruction, set up snoop queue buffer memory.
Subsequent step is described the process of poll manager 500 for snoop queue buffer memory.
Step 505, poll manager 500 is after snoop queue buffer memory often adds a clocking information, then the time parameter starting corresponding timer corresponding to clocking information carries out timing.
Step 505, when the clocking information in snoop queue storage queue reaches, produces a bus request to moderator 100, and application takies the state that bus reads Destination Storage Unit corresponding to clocking information.
Step 506, after poll manager 500 gets bus, then makes interface controller 300 perform (making interface controller 300 perform sequential corresponding to the instruction of query aim state of memory cells) query aim storage unit and whether is in equipment state; If so, illustrate that this instruction completes, then clocking information is then deleted from snoop queue buffer memory.
If it is busy to inquire Destination Storage Unit, declarative instruction not yet completes, then clocking information when being updated to reclocking, again proposes bus request from moderator 100 after full after timing time arrives.
In the embodiment of the present invention by the data processing structure of pure hardware implementing (FPGA or CPLD realization) to from host side write command and read instruction and respond, arbitrated based on the bus of preset strategy to the free time by moderator 100, executable instruction is sent to Destination Storage Unit to realize reading and writing data according to arbitration result, or whether to be finished the instruction sent according to arbitration result query aim storage unit; Thus the interactive operation achieved different storage unit, execution efficiency and real-time high;
Compare with the mode that software coordinates with dependence processor single in correlation technique, because queue safeguarded by needs processor, mutual by interrupting with the carrying out of storage unit, and the state (storage unit whether be finished the instruction sent) of inquiry storage unit, cause execution efficiency lower; In the present embodiment based on independent of the pure hardware implementing outside processor to the interactive operation of different storage unit, do not need to rely on interrupt with storage unit mutual, execution efficiency and real-time high, the high power consumption of processor can not be caused;
With correlation technique by compared with microcode mode, state due to each cycle sending to storage unit needs to realize safeguarding in the buffer, therefore need very large storage space to store the state of each order in each cycle, and the hardware mode by having independent data process structure and data store organisation in the present embodiment realizes, spatial cache extra in electronic equipment can not be taken, by hardware mode, there is simplicity of design simultaneously and be convenient to the advantage of amendment.
The embodiment of the present invention also records a kind of electronic equipment, and see Fig. 1, electronic equipment comprises:
Command supervisor 100, for choosing executable instruction based on the priority of instruction in instruction queue buffer memory, sends bus request to ask bus for selected instruction;
Interface controller 300, for sending Destination Storage Unit corresponding in executable instruction to storer 400 when command supervisor 100 asks bus by bus, and reads to snoop queue buffer memory by the clocking information of executable instruction;
Poll manager 500, bus request is sent to ask bus after arriving for clocking information arbitrary in snoop queue buffer memory, with ask to bus time, by interface controller 300, via bus inquiry clocking information ownership instruction corresponding to Destination Storage Unit whether be finished;
Moderator 200, for arbitrating the bus request received based on preset strategy when bus free, and based on arbitration result distribution bus.
Exemplarily, interface controller 300, also for reporting the status information of each storage unit in storer 400 to command supervisor 100;
Command supervisor 100, also for the status information of each storage unit in the storer 400 that reports based on interface controller 300, whether the Destination Storage Unit that in decision instruction queue buffer memory, the instruction of limit priority is corresponding is in standby condition,
If so, then judge that the instruction of limit priority is as executable instruction;
If not, whether the Destination Storage Unit that then instruction of continuation judgement time high priority is corresponding is in standby condition, until judge the Destination Storage Unit being in standby condition, and be that the instruction of the limit priority of the Destination Storage Unit being in standby condition is defined as executable instruction by Action Target.
Exemplarily, command supervisor 100, also for from reading pending instruction in instruction queue buffer memory, wherein, the priority and instruction of the instruction in instruction queue buffer memory is read to the sequencing in instruction queue buffer memory consistent;
When interface controller 300 sends Destination Storage Unit corresponding in executable instruction to storer 400, delete executable instruction at instruction queue buffer memory, and continue to read pending instruction to instruction queue buffer memory from processor.
Exemplarily, interface controller 300, also for resolving executable instruction, obtains the poll mark of executable instruction;
Interface controller 300, also for characterizing the state of the Destination Storage Unit that executable instruction needs inquiry corresponding when poll mark, then reads to snoop queue buffer memory by the clocking information of executable instruction, and delete executable instruction in instruction queue buffer memory;
Interface controller 300, also for characterizing the state that executable instruction does not need to inquire about corresponding Destination Storage Unit when poll mark, deletes executable instruction in instruction queue buffer memory; Wherein, the prioritization of the clocking information in snoop queue buffer memory is read to the sequencing in instruction queue buffer memory corresponding with clocking information.
Exemplarily, poll manager 500, time also for being read at clocking information to snoop queue buffer memory, carries out timing process to clocking information; Bus is asked to moderator 200 when clocking information arrives.
Exemplarily, moderator 200 also for receive at the same time arrive for the clocking information in snoop queue buffer memory for the bus request of executable instruction and poll manager 500 from command supervisor 100 after send bus request time, be the bus request distribution bus for executable instruction;
When moderator 200 is also for receiving at least two bus request sent after poll manager 500 arrives at least two clocking informations in snoop queue buffer memory at the same time simultaneously, it is the bus request distribution bus of the clocking information for limit priority at least two clocking informations.
Exemplarily, poll manager 500, also for inquired by interface controller 300 clocking information ownership instruction corresponding to Destination Storage Unit be finished time, from snoop queue buffer memory, delete clocking information;
Poll manager 500, also for inquired by interface controller 300 clocking information ownership instruction corresponding to Destination Storage Unit be not finished time, upgrade the clocking information in snoop queue buffer memory and carry out timing process for the clocking information after upgrading, the stand-by period of the clocking information after wherein upgrading is less than the stand-by period upgrading front timing time.
Based in the embodiment of the present invention to the description of the function of the execution of above-mentioned functions unit, above-mentioned functional unit can have other forms of realization (as merge into two functional units, or be split as the functional unit of four or more); Therefore, in the embodiment of the present invention, being described embodiment of the present invention record method of the electronic equipment shown in composition graphs 1, does not form limitation of the invention.
In the embodiment of the present invention, by the data processing structure of pure hardware implementing (FPGA or CPLD realization) to from host side write command and read instruction and respond, arbitrated based on the bus of preset strategy to the free time by moderator, executable instruction is sent to Destination Storage Unit to realize reading and writing data according to arbitration result, or whether to be finished the instruction sent according to arbitration result query aim storage unit; Thus the interactive operation achieved different storage unit, execution efficiency and real-time high.
One of ordinary skill in the art will appreciate that: all or part of step realizing said method embodiment can have been come by the hardware that programmed instruction is relevant, aforesaid program can be stored in a computer read/write memory medium, this program, when performing, performs the step comprising said method embodiment; And aforesaid storage medium comprises: movable storage device, ROM (read-only memory) (ROM, Read-OnlyMemory), random access memory (RAM, RandomAccessMemory), magnetic disc or CD etc. various can be program code stored medium.
Or, if the above-mentioned integrated unit of the present invention using the form of software function module realize and as independently production marketing or use time, also can be stored in a computer read/write memory medium.Based on such understanding, the technical scheme of the embodiment of the present invention can embody with the form of software product the part that prior art contributes in essence in other words, this computer software product is stored in a storage medium, comprises some instructions and performs all or part of of each embodiment method of the present invention in order to make a computer equipment (can be personal computer, server or the network equipment etc.).And aforesaid storage medium comprises: movable storage device, ROM, RAM, magnetic disc or CD etc. various can be program code stored medium.
Above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; change can be expected easily or replace, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of claim.
Claims (14)
1. a data processing method, is characterized in that, described method comprises:
Priority based on instruction in instruction queue buffer memory chooses executable instruction, sends bus request to ask bus for selected instruction;
In request to being sent Destination Storage Unit corresponding in described executable instruction to storer during bus by bus, and the clocking information of described executable instruction is read to snoop queue buffer memory;
In described snoop queue buffer memory, arbitrary clocking information sends bus request to ask bus after arriving, and with when asking bus, whether the Destination Storage Unit corresponding to instruction being inquired about described clocking information ownership by bus is finished;
The bus request received is arbitrated based on preset strategy when bus free, and based on arbitration result distribution bus.
2. data processing method as claimed in claim 1, it is characterized in that, the described priority based on instruction in instruction queue buffer memory chooses executable instruction, comprising:
Based on the status information of storage unit each in described storer, judge whether Destination Storage Unit corresponding to the instruction of limit priority in described instruction queue buffer memory is in standby condition,
If so, then judge that the instruction of described limit priority is as executable instruction;
If not, whether the Destination Storage Unit that then instruction of continuation judgement time high priority is corresponding is in standby condition, until judge the Destination Storage Unit being in standby condition, and by Action Target for described in be in the limit priority of the Destination Storage Unit of standby condition instruction be defined as described executable instruction.
3. data processing method as claimed in claim 1, it is characterized in that, described method also comprises:
Read in pending instruction to described instruction queue buffer memory, wherein, priority and the described instruction of the instruction in instruction queue buffer memory are read to the sequencing in described instruction queue buffer memory consistent;
When sending Destination Storage Unit corresponding in described executable instruction to described storer, delete described executable instruction at described instruction queue buffer memory, and continue from reading pending instruction to described instruction queue buffer memory.
4. data processing method as claimed in claim 1, it is characterized in that, the described clocking information by executable instruction reads to snoop queue buffer memory, comprising:
Resolve described executable instruction, obtain the poll mark of described executable instruction;
If described poll mark characterizes the state of the Destination Storage Unit that described executable instruction needs inquiry corresponding, then the clocking information of described executable instruction is read to described snoop queue buffer memory, and delete described executable instruction in described instruction queue buffer memory;
If described poll mark characterizes the state that described executable instruction does not need to inquire about corresponding Destination Storage Unit, in described instruction queue buffer memory, delete described executable instruction; Wherein, the prioritization of the clocking information in described snoop queue buffer memory is read to the sequencing in described instruction queue buffer memory corresponding with described clocking information.
5. data processing method as claimed in claim 1, is characterized in that, described in snoop queue buffer memory arbitrary clocking information arrive after transmission bus request to ask bus, comprising:
When described clocking information is read to described snoop queue buffer memory, timing process is carried out to described clocking information;
Bus request is sent to ask bus when described clocking information arrives.
6. data processing method as claimed in claim 1, is characterized in that, describedly arbitrates the bus request received based on preset strategy when bus free, and based on arbitration result distribution bus, comprising:
When receiving the bus request for described executable instruction and the bus request for transmission after the clocking information arrival in described snoop queue buffer memory, it is the bus request distribution bus for described executable instruction simultaneously;
When receiving at least two bus request simultaneously sent after arriving at least two clocking informations in described snoop queue buffer memory, it is the bus request distribution bus for the clocking information of limit priority in described at least two clocking informations simultaneously.
7. the data processing method as described in any one of claim 1 to 6, is characterized in that, whether the described Destination Storage Unit inquiring about instruction that described clocking information belongs to corresponding by bus is finished, and comprising:
By bus inquire described clocking information ownership instruction corresponding to Destination Storage Unit be finished time, from described snoop queue buffer memory, delete described clocking information;
By bus inquire described clocking information ownership instruction corresponding to Destination Storage Unit be not finished time, upgrade the described clocking information in described snoop queue buffer memory and carry out timing process for the clocking information after described renewal, the stand-by period of the described clocking information after wherein upgrading is less than the stand-by period upgrading front described timing time.
8. an electronic equipment, is characterized in that, described electronic equipment comprises:
Command supervisor, for choosing executable instruction based on the priority of instruction in instruction queue buffer memory, sends bus request to ask bus for selected instruction to moderator;
Interface controller, in described command supervisor request to be sent in described executable instruction to storer corresponding Destination Storage Unit during bus by bus, and the clocking information of described executable instruction is read to snoop queue buffer memory;
Poll manager, bus request is sent to ask bus after arriving for clocking information arbitrary in described snoop queue buffer memory, with when asking bus, by described interface controller, to inquire about described clocking information ownership via bus instruction corresponding to Destination Storage Unit whether be finished;
Moderator, for arbitrating the bus request received based on preset strategy when bus free, and based on arbitration result distribution bus.
9. electronic equipment as claimed in claim 8, is characterized in that,
Described interface controller, also for reporting the status information of each storage unit in described storer to described command supervisor;
Described command supervisor, also for the status information of each storage unit in the described storer that reports based on described interface controller, judges whether Destination Storage Unit corresponding to the instruction of limit priority in described instruction queue buffer memory is in standby condition,
If so, then judge that the instruction of described limit priority is as executable instruction;
If not, whether the Destination Storage Unit that then instruction of continuation judgement time high priority is corresponding is in standby condition, until judge the Destination Storage Unit being in standby condition, and by Action Target for described in be in the limit priority of the Destination Storage Unit of standby condition instruction be defined as described executable instruction.
10. electronic equipment as claimed in claim 8, is characterized in that,
Described command supervisor, also for from reading pending instruction in described instruction queue buffer memory, wherein, priority and the described instruction of the instruction in described instruction queue buffer memory are read to the sequencing in described instruction queue buffer memory consistent;
Described command supervisor, time also for sending Destination Storage Unit corresponding in described executable instruction to described storer at described interface controller, delete described executable instruction at described instruction queue buffer memory, and continue to read pending instruction to described instruction queue buffer memory from described processor.
11. electronic equipments as claimed in claim 8, is characterized in that,
Described interface controller, also for resolving described executable instruction, obtains the poll mark of described executable instruction;
Described interface controller, also for when described poll mark characterizes the state of the Destination Storage Unit that described executable instruction needs inquiry corresponding, the clocking information of described executable instruction is read to described snoop queue buffer memory, and delete described executable instruction in described instruction queue buffer memory;
Described interface controller, also for when described poll mark characterizes the state of the Destination Storage Unit that described executable instruction does not need inquiry corresponding, deletes described executable instruction in described instruction queue buffer memory; Wherein, the prioritization of the clocking information in described snoop queue buffer memory is read to the sequencing in described instruction queue buffer memory corresponding with described clocking information.
12. electronic equipments as claimed in claim 8, is characterized in that,
Described poll manager, time also for being read to described snoop queue buffer memory at described clocking information, carries out timing process to described clocking information; When described clocking information arrives to described moderator request bus.
13. electronic equipments as claimed in claim 8, is characterized in that,
Described moderator, also for receive at the same time arrive for the clocking information in described snoop queue buffer memory for the bus request of described executable instruction and described poll manager from described command supervisor after send bus request time, be the bus request distribution bus for described executable instruction;
Described moderator, time also for receiving at least two bus request sent after described poll manager arrives at least two clocking informations in described snoop queue buffer memory at the same time simultaneously, it is the bus request distribution bus for the clocking information of limit priority in described at least two clocking informations.
14. electronic equipments as described in any one of claim 8 to 13, is characterized in that,
Described poll manager, also for inquired by described interface controller described clocking information ownership instruction corresponding to Destination Storage Unit be finished time, from described snoop queue buffer memory, delete described clocking information;
Described poll manager, also for inquired by described interface controller described clocking information ownership instruction corresponding to Destination Storage Unit be not finished time, upgrade the described clocking information in described snoop queue buffer memory and carry out timing process for the clocking information after described renewal, the stand-by period of the described clocking information after wherein upgrading is less than the stand-by period upgrading front described timing time.
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