CN105243033B - Data processing method and electronic equipment - Google Patents
Data processing method and electronic equipment Download PDFInfo
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- CN105243033B CN105243033B CN201510629598.5A CN201510629598A CN105243033B CN 105243033 B CN105243033 B CN 105243033B CN 201510629598 A CN201510629598 A CN 201510629598A CN 105243033 B CN105243033 B CN 105243033B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/16—Memory access
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/36—Arbitration
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a kind of data processing method and electronic equipment, method includes：The priority instructed in being cached based on instruction queue chooses executable instruction, sends bus request for selected instruction to ask bus；Executable instruction corresponding Destination Storage Unit into memory is sent by bus when request is to bus, and the clocking information of executable instruction is read to snoop queue and is cached；Bus request is sent to ask bus after arbitrary clocking information arrival in snoop queue caching, with when request is to bus, whether the Destination Storage Unit inquired about by bus corresponding to the instruction of clocking information ownership is finished；The bus request received is arbitrated based on preset strategy in bus free, and bus is distributed based on arbitration result.Implement the present invention, can efficiently, the mode of low-power consumption realize Out-of-order execution of the instruction between storage unit, to promote the utilization rate of bus, and then promotion is to the read or write speed of memory.
Description
Technical field
The present invention relates to memory technology more particularly to a kind of data processing method and electronic equipments.
Background technology
Electronic equipment such as smart mobile phone, tablet computer etc. generally use flash memory (Flash) such as NAND flash storages list
Member as storage medium, flash memory from top and under framework be：Chip (Chip), logic unit (LU), piece (Plane), block
(Block), page (Page), the framework (removing the bottom) on each upper strata can include the framework of one or more lower floors, such as one
A chip can include one or more logic units；Wherein logical unit number (LUN, Logic may be employed in logic unit
Unit Number) mark, using block for the base unit of erasing in flash memory, using page as basic addressing unit, (namely page is reading
The base unit of operation), wherein, logic unit is minimum (basic) unit for the instruction for being capable of separate responses processor；
One characteristic feature of flash disk operation is that each storage unit executes instruction required time namely delay
(latency) it is larger, such as the delay of page (Page) in chip is read as Microsecond grade (such as 50us), page in chip is programmed
(Program) namely the delay of data is write as Microsecond grade (such as 500us), the delay of block erasing (Block Erase) in chip
For millisecond (ms) grade；It is idle in the bus of timing period electronic equipment, in order to improve bus utilization, correlation technique introduces
Interleaved pages programmings (Interleave Page Program) technology；
By taking page is read as an example, for same logic unit, at a time can only to a page in the logic unit into
Row is read, and is instructed sending to read to a logic unit by bus so that the logic unit performs what is read data and return
It, can into flash memory, other logic units send instruction and (such as are inserted into other logic units by bus in waiting time
The instruction that is read out of page), it is achieved thereby that the Out-of-order execution of instruction between Different Logic unit namely the finger sent afterwards
Order may (it be different to perform the logic unit for sending instruction from the logic unit that instruction is sent after execution earlier than the instruction first sent
Logic unit) complete.
Interleaved pages programming technique is realized by using following scheme in correlation technique：
1) caching (SRAM), it is necessary to very big is realized by microcode, and the passage of each logic unit operation is needed
Want individual SRAM space；Microcode Design is complicated simultaneously, and modification is difficult, and it is more difficult to be realized for the Out-of-order execution of different instruction；
2) dispatched and realized, it is necessary to processor safeguards queue by processor (CPU), handed over by interrupting with flash memory
Mutually, and need to inquire about the state of flash memory, therefore limited speed, be not suitable for the higher occasion of bandwidth requirement, real-time is poor, right
Processor performance requirement is also higher, so as to cause the high power consumption of processor.
To sum up, the Out-of-order execution of instruction is realized for efficient, low-power consumption mode, to promote the utilization rate of bus, and then
The read or write speed to flash memory is promoted, correlation technique there is no effective solution.
The content of the invention
The embodiment of the present invention provides a kind of data processing method and electronic equipment, can efficiently, the mode of low-power consumption realizes
The Out-of-order execution of instruction to promote the utilization rate of bus, and then promotes the read or write speed to memory.
What the technical solution of the embodiment of the present invention was realized in：
The embodiment of the present invention provides a kind of data processing method, the described method includes：
The priority instructed in being cached based on instruction queue chooses executable instruction, and bus is sent for selected instruction
It asks to ask bus；
The executable instruction corresponding Destination Storage Unit into memory is sent by bus when request is to bus,
And the clocking information of the executable instruction is read to snoop queue and is cached；
Arbitrary clocking information sends bus request to ask bus in snoop queue caching after reaching, to ask
When seeking bus, whether the Destination Storage Unit inquired about by bus corresponding to the instruction of the clocking information ownership has performed
Finish；
The bus request received is arbitrated based on preset strategy in bus free, and is distributed based on arbitration result
Bus.
The embodiment of the present invention provides a kind of electronic equipment, and the electronic equipment includes：
Command supervisor, the priority for instructing in being cached based on instruction queue chooses executable instruction, for selected
The instruction taken sends bus request to ask bus；
Interface controller, for sending the executable instruction by bus when described instruction manager request is to bus
The corresponding Destination Storage Unit into memory, and the clocking information of the executable instruction is read to snoop queue and is cached；
Poll manager, in snoop queue caching arbitrary clocking information reach after send bus request with
Bus is asked, when request is to bus, to inquire about the finger that the clocking information belongs to by the interface controller, via bus
Whether the corresponding Destination Storage Unit of order is finished；
Moderator for being arbitrated in bus free based on preset strategy to the bus request received, and is based on
Arbitration result distributes bus.
In the embodiment of the present invention, by the data processing structure of pure hardware realization (FPGA or CPLD are realized) to coming from host
The write command and reading instruction at end are responded, and idle bus are arbitrated based on preset strategy by moderator, with according to secondary
It cuts out result and executable instruction is sent to Destination Storage Unit to realize reading and writing data or inquire about target storage according to arbitration result
Whether unit is finished the instruction sent；It is achieved thereby that the interactive operation to different storage units, execution efficiency and reality
Shi Xinggao.
Description of the drawings
Fig. 1 is the structure diagram one of electronic equipment in the embodiment of the present invention；
Fig. 2 is the structure diagram two of electronic equipment in the embodiment of the present invention；
Fig. 3 is the realization flow diagram one of data processing method in the embodiment of the present invention；
Fig. 4 is the realization flow diagram two of data processing method in the embodiment of the present invention；
Fig. 5 is the realization flow diagram three of data processing method in the embodiment of the present invention；
Fig. 6 is the realization flow diagram four of data processing method in the embodiment of the present invention.
Specific embodiment
The present invention is described in further detail in the following with reference to the drawings and specific embodiments.
The electronic equipment that the embodiment of the present invention is recorded can be implemented in a variety of manners, for example, above-mentioned electronic equipment can
To be smart mobile phone, tablet computer, laptop or Wearable (such as intelligent glasses, smartwatch), electronic equipment
Operating system can be Android operation system, IOS operating system or any other third party exploitation can run on it is miniature
Operating system (such as the mobile edition linux system, blackberry, blueberry QNX operating systems of computer configuation (including at least processor and memory)
Deng)；Above-mentioned electronic equipment can also be solid state disk etc. for storing the electronic equipment of data.
By setting logic-based programmable gate array (FPGA) or Complex programmable logical device (CPLD) skill in electronic equipment
Art implements the data processing method that the embodiment of the present invention is recorded, and referring to Fig. 1, implements the data processing side that the embodiment of the present invention is recorded
The electronic equipment of method includes at least following functions unit：Command supervisor 200, interface controller 300, moderator 100, memory
400 and poll manager 500；Above-mentioned functional unit constitutes the data processing structure that response data is read and write in electronic equipment；Such as
Before, above-mentioned command supervisor 200,500 logic-based programmable gate of interface controller 300, moderator 100 and poll manager
Array or Complex programmable logical device realize there is independent data processing structure and data store organisation, above-mentioned memory 400
It is that can be realized in electronic equipment for storing the main devices of data by flash memory (such as Nand Flash)；
Certainly, according to the specific product form of electronic equipment, as shown in Fig. 2, processor can also be included in electronic equipment
(CPU) 600, when electronic equipment for smart mobile phone, tablet computer when the processor as application processor (AP) use, be responsible for
Data processing, such as the read request according to application layer are carried out between data processing structure and electronic device systematic difference layer
Reading instruction is sent to above-mentioned data structure, by the corresponding data transfer of data structure to application layer；Or writing according to application layer
It asks to send write command to above-mentioned data structure, data structure is made to write target data；That is, data processing structure is
Reading instruction from processor 600 or write command are responded, processor is equivalent to host for data processing structure
(Host) hold.
Based on the electronic equipment shown in Fig. 1 and Fig. 2, referring to Fig. 3, the data processing method that the embodiment of the present invention is recorded passes through
Following steps are realized：
Step 101, the priority that command supervisor 200 is instructed in being cached based on instruction queue chooses executable instruction, pin
Bus request is sent to selected instruction to ask bus.
Command supervisor 200 from processor 600 read for memory 400 instruction (namely pending instruction, including
Reading instruction and write command), and the instruction of acquisition is stored in the instruction queue caching of command supervisor 200 (as before, instruction queue
Caching is with the buffer structure of FPGA or CPLD realizations), the quantity of command supervisor 200 from the instruction that processor 600 is read takes
The quantity for the instruction that can be certainly stored in the instruction queue caching of command supervisor 200, when command supervisor 200 will instruct team
An instruction in row caching is sent to the Destination Storage Unit (interface controller in memory 400 by interface controller 300
300 generate clock signal according to instruction, execute instruction Destination Storage Unit) and after being finished by Destination Storage Unit,
Command supervisor 200 can delete corresponding instruction in instruction queue caching, and read an instruction from processor 600 and store to finger
The tail of the queue that queue is made to cache；Storage unit 400 refers to be capable of the base unit of the instruction of answer processor 600 (such as in memory 400
Logic unit, a storage unit can only at a time respond an instruction from processor 600).
The format sample each instructed in instruction queue caching is as shown in table 1：
| Command identification (ID) | Executable part | Poll identifies | Stand-by period |
Table 1
Referring to table 1, each instruction in instruction queue caching includes：
1) command identification, the instruction read for unique mark from processor 600；
2) part, that is, executable instruction field be can perform；
3) poll identify, show the instruction be sent to Destination Storage Unit (namely performing the storage unit of the instruction) it
Afterwards, if need to inquire about the instruction by bus and be finished；
The stand-by period of instruction (instruction as read storage unit ID) outside reading instruction and write command is shorter, at such
Instruction is sent to after Destination Storage Unit i.e. it is believed that being finished, and command supervisor 200 can be from instruction queue
According to priority, (priority of the instruction of instruction queue caching reads the sequencing cached to instruction queue with instruction in caching
Unanimously, that is, be introduced into instruction queue caching instruction priority be higher than after into instruction queue caching instruction it is preferential
Grade) the corresponding Destination Storage Unit of extraction instruction (if present) and pass through interface controller 300 and be sent to target storage
Unit performs, and therefore, the corresponding poll of instruction outside reading instruction and write command is identified as no, represents that instruction is sent to target and deposits
(think that instruction is finished by Destination Storage Unit after sending) after storage unit, need not be inquired about and sent out by bus
Whether the instruction sent is finished by Destination Storage Unit；
Storage unit 400 performs reading instruction and the stand-by period of write command needs is relatively long, and command supervisor 200 passes through
Interface controller 300 sends reading instruction or write command to Destination Storage Unit afterwards, it is necessary to the instruction sent by bus inquiry
Whether whether be finished by Destination Storage Unit (such as Destination Storage Unit is finished to prepare state representation instruction, mesh
Mark storage unit has not carried out for busy state characterization instruction and finishes)；Therefore, the poll of reading instruction and write command is identified as,
Characterization command supervisor 200, which sends a command to by interface controller 300 after Destination Storage Unit to also need to inquire about, (passes through wheel
Ask manager 500 to inquire about, subsequently illustrate) whether the instruction that sends be finished, when being finished just from instruction queue
The instruction (if present) of the corresponding Destination Storage Unit is extracted in caching and passes through interface controller 300 and is sent to the target and is deposited
Storage unit performs.
The priority that command supervisor 200 is instructed in based on instruction buffer queue is (as before, the instruction of instruction queue caching
Priority and instruction store the sequence consensus cached to instruction queue, that is, be introduced into instruction queue caching instruction it is excellent
First grade be higher than after into instruction queue caching instruction priority) choose executable instruction when, it is also necessary to referenced interface control
(state of storage unit includes the status information of each storage unit into the memory 400 that command supervisor 200 transmits of device 300
The preparation state that can execute instruction and the busy state for being carrying out instruction)；
Wherein, often storage unit into memory 400 sends once command and (namely generates correspondence interface controller 300
Clock signal) or performed the status inquiry of a storage unit, it is possible to by the shape of each storage unit in memory 400
State passes to command supervisor 200；Command supervisor 200 is sentenced according to the status information of each storage unit 400 in memory 400
Whether the corresponding Destination Storage Unit of instruction of highest priority is in preparation state in disconnected instruction queue caching, if so, sentencing
The instruction for determining highest priority is executable instruction；If it is not, then continue to judge that the corresponding target of instruction of time high priority stores
Whether unit in preparation state, until judge the Destination Storage Unit in preparation state, and will operation target be in
The instruction of the highest priority of the Destination Storage Unit of preparation state is determined as executable instruction, and bus is asked to moderator 100,
(processing that moderator 100 distributes bus illustrates in step 105) can hold when request is to bus after moderator 100 distributes bus
Row instruction instruction is sent to interface controller 300, so that executable instruction is sent to Destination Storage Unit (also by Interface Controller
It is that the clock signal that interface controller 300 is made to generate corresponding instruction performs Destination Storage Unit).
Step 102, command supervisor 200 request to bus when, by interface controller 300 and via bus transmission can
Corresponding Destination Storage Unit is executed instruction into memory 400, and passes through timing of the interface controller 300 by executable instruction
Information reads to snoop queue and caches.
Command supervisor 200 sends executable instruction to interface controller 300 when request is to bus by bus, by connecing
Mouth controller 300, which generates the corresponding clock signal of executable instruction and passes through bus, is sent to Destination Storage Unit so that target is deposited
Storage unit executes instruction (executable instruction), as before, the instruction (executable instruction) that sends of interface controller 300 for reading instruction or
It needs to inquire about Destination Storage Unit during write command whether to be finished the instruction of transmission, it is new with what is sent after determining to be finished
Instruction, in consideration of it, after executable instruction is sent to Destination Storage Unit, referring to Fig. 4, interface controller 300 is not for
Same executable instruction performs following processing：
Step 201, interface controller 300 parses executable instruction, obtains the poll mark of executable instruction.
Step 202, if poll mark characterization executable instruction needs to inquire about the state (characterization of corresponding Destination Storage Unit
Instruct as reading instruction or write command), then the clocking information of executable instruction (can be executable instruction by interface controller 300
Time delay) read to snoop queue caching (with by poll manager 500 be based on each clocking information of snoop queue caching query
Whether the corresponding object element of instruction of ownership, which executes instruction, finishes), and delete executable instruction in instruction queue caching；When
After interface controller 300 deletes executable instruction from the instruction queue caching of command supervisor 200, command supervisor 200
Also pending instruction filling is read to the tail of the queue of instruction queue caching from processor 600.
Step 203, if poll mark characterization executable instruction need not inquire about the state (table of corresponding Destination Storage Unit
Executable instruction is levied as the instruction outside reading instruction and write command, is sent i.e. in executable instruction it is believed that instruction has performed
Finish), delete executable instruction in instruction queue caching；When the instruction queue of interface controller 300 from command supervisor 200 is delayed
It deposits after deleting executable instruction, command supervisor 200 also reads pending instruction from processor 600 and fills to instruction team
Arrange the tail of the queue of caching.
Step 103, poll manager 500 sends bus request in snoop queue caching after arbitrary clocking information reaches
To ask bus.
Snoop queue is cached and safeguarded by poll manager 500, example such as 2 institute of table of clocking information in snoop queue caching
Show,
| Member 1 (command identification 1) | Member 2 (command identification 2) |
| Clocking information 1 (timer 1) | Clocking information 2 (timer 2) |
Table 2
Referring to table 2, each clocking information in snoop queue caching belongs to the one of the transmission of (correspondence) interface controller 300
A instruction (executable instruction), the priority ranking of clocking information are read by interface controller 300 to instruction team with clocking information
Row caching in sequencing correspond to, that is, first read to snoop queue cache in clocking information priority be higher than after read
The priority of clocking information in caching is taken to snoop queue；Clocking information be read to snoop queue cache when, by poll pipe
The clocking information that reason device 500 is each instructed by run timing device maintenance, each clocking information in snoop queue caching arrive
Up to when, to moderator 100 ask bus so that moderator 100 carry out bus assignment arbitration, to pass through when being assigned to bus
Whether the Destination Storage Unit corresponding to the instruction of bus inquiry clocking information ownership is finished.
Step 104, poll manager 500 is inquired about clocking information by interface controller 300 and is belonged to when request is to bus
Instruction corresponding to Destination Storage Unit whether be finished (executable instruction received).
In fact, poll manager 500 is the state for coordinating inquiry Destination Storage Unit with interface controller 300, poll
Manager 500 makes interface controller 300 is logical to generate the clock signal of corresponding Destination Storage Unit status inquiry, and makes Interface Controller
Whether device 300 is finished instruction with detecting Destination Storage Unit by bus transmission timing signal.
Referring to Fig. 5, the Destination Storage Unit inquired about by interface controller 300 corresponding to the instruction of clocking information ownership is
It is no to be finished, comprise the following steps：
Step 301, the Destination Storage Unit corresponding to the instruction of clocking information ownership is inquired about by interface controller 300
State；When Destination Storage Unit is in preparation state, characterization Destination Storage Unit, which executes instruction, to be finished, and performs step 302；When
When Destination Storage Unit is in busy state, characterization Destination Storage Unit is carrying out instructing, and performs step 303 and is transferred to step
301。
Step 302, poll manager 500 is inquired by interface controller 300 corresponding to the instruction of clocking information ownership
Destination Storage Unit when being finished, without inquiring about the state of Destination Storage Unit again, deleted from snoop queue caching
Clocking information.
Step 302, poll manager 500 is inquired by interface controller 300 corresponding to the instruction of clocking information ownership
Destination Storage Unit when being not carried out finishing, it is also necessary to continue to inquire about the state of Destination Storage Unit, therefore, update snoop queue
Clocking information in caching simultaneously carries out timing processing for updated clocking information；Optionally, due to Destination Storage Unit
Through performing the period corresponding to timing time for the executable instruction of reception, Destination Storage Unit executes instruction institute afterwards
The opposite reduction of the time at place, if stand-by period of the stand-by period of updated clocking information less than timing time before update,
It will avoid not detecting the situation that Destination Storage Unit is in preparation state in time, so as to which command supervisor 200 can incite somebody to action
New instruction is sent to by interface controller 300 to Destination Storage Unit, promotes the efficiency executed instruction.
Step 105, moderator 100 arbitrates the bus request received based on preset strategy in bus free,
And distribute bus based on arbitration result.
Referring to step 101 and step 102, moderator 100 can receive the bus request from command supervisor 200, ginseng
See step 103 and step 104, moderator 100 can receive the bus request from poll manager 500；It is received when simultaneously
During two bus requests, referring to Fig. 6, bus arbitration includes following two situations：
Step 401, at the same receive from command supervisor 200 be directed to executable instruction bus request and poll
During the bus request that manager 500 is sent after being reached for the clocking information in snoop queue caching, to be directed to executable instruction
Bus request distribution bus.
That is, when command supervisor 200 and poll manager 500 send bus request to moderator 100 simultaneously, refer to
The priority of manager 200 is made to be always above the priority of poll manager 500.
Step 402, at the same receive poll manager 500 for snoop queue caching at least two clocking informations arrive
During up at least two bus request that is rear while sending, to be directed to the clocking information of highest priority at least two clocking informations
Bus request distribution bus.
The sequencing that the priority of clocking information enters snoop queue caching with clocking information is consistent, that is, is introduced into
The priority for the clocking information that the priority of the clocking information of snoop queue caching caches after being higher than into snoop queue.
The specific example for carrying out data processing in conjunction with electronic equipment below illustrates, and comprises the following steps：
Step 501, command supervisor 200 reads instruction from host side (processor 600) first and is put into instruction queue caching,
Establish instruction queue caching.
Step 502, command supervisor 200 is according to the state (state of each storage unit of each storage unit in memory 400
Command supervisor 200 is passed to by interface controller 300), executable instruction is chosen from instruction queue caching, to moderator
100 propose bus request.
Step 503, moderator 100 carries out bus arbitration.
If Current bus is idle, and receives only the bus request from command supervisor 200, then managed for instruction
Device 200 distributes bus；
If receiving two or more bus requests simultaneously, bus arbitration is carried out according to the mode of abovementioned steps 105.
Step 504, after command supervisor 200 gets bus, the executable part that is executed instruction by interface controller 300
The sequential of corresponding instruction is generated to Destination Storage Unit；If poll is identified as 1, (characterization needs the corresponding target of inquiry instruction to deposit
Whether storage unit is finished), then command identification, clocking information are stored to snoop queue and cached；Command supervisor 200 should
Instruction is deleted, and is read an instruction (if present) from host side and is inserted instruction queue caching
Step 501 is often performed to step 504 once can one clocking information of addition (and timing in snoop queue caching
The mark of the corresponding executable instruction of information), snoop queue caching is set up while executing instruction.
Subsequent step illustrates processing of the poll manager 500 for snoop queue caching.
Step 505, poll manager 500 then starts corresponding after snoop queue caches and often adds a clocking information
Timer carries out timing to the corresponding time parameter of clocking information.
Step 505, when the clocking information in snoop queue storage queue reaches, a bus request is generated to moderator
100, application occupies the state that bus reads the corresponding Destination Storage Unit of clocking information.
Step 506, after poll manager 500 gets bus, then performing interface controller 300 (makes interface controller
300 perform the corresponding sequential of instruction of inquiry Destination Storage Unit state) inquire about whether Destination Storage Unit is in equipment state；
If so, illustrating that the instruction is completed, then clocking information then from snoop queue is cached and deleted.
If it is busy to inquire Destination Storage Unit, illustrate that instruction is not yet completed, then update clocking information then and again
Timing proposes bus request from moderator 100 again after full after timing time arrival.
By the data processing structure of pure hardware realization (FPGA or CPLD are realized) to coming from host in the embodiment of the present invention
The write command and reading instruction at end are responded, and idle bus are arbitrated based on preset strategy by moderator 100, with basis
Executable instruction is sent to Destination Storage Unit and is deposited with realizing reading and writing data or inquiring about target according to arbitration result by arbitration result
Whether storage unit is finished the instruction sent；It is achieved thereby that the interactive operation to different storage units, execution efficiency and
Real-time is high；
Compared with the single mode for relying on processor and software cooperation in correlation technique, since processor being needed to safeguard team
Row, by interrupting, come the state for interacting and inquiring about storage unit with storage unit, (whether storage unit is finished
The instruction sent), cause execution efficiency relatively low；Based on independently of the pure hardware realization pair outside processor in the present embodiment
The interactive operation of different storage units needs not rely on interruption and is interacted with storage unit, and execution efficiency and real-time are high, will not lead
Cause the high power consumption of processor；
Compared with correlation technique is by microcode mode, it is required for due to being sent to the state in each cycle of storage unit
Realization is safeguarded in the buffer, it is therefore desirable to which very big memory space stores each state of the order in each cycle, and this reality
It applies in example and is realized by the hardware mode with independent data processing structure and data store organisation, will not be occupied in electronic equipment
Additional spatial cache, while have the advantages that design is simple and is easily modified by hardware mode.
The embodiment of the present invention also records a kind of electronic equipment, and referring to Fig. 1, electronic equipment includes：
Command supervisor 100, the priority for instructing in being cached based on instruction queue chooses executable instruction, for institute
The instruction of selection sends bus request to ask bus；
Interface controller 300, for sending executable instruction extremely by bus when the request of command supervisor 100 is to bus
Corresponding Destination Storage Unit in memory 400, and the clocking information of executable instruction is read to snoop queue and is cached；
Poll manager 500, sent after being reached for arbitrary clocking information in being cached in snoop queue bus request with
Bus is asked, when request is to bus, to inquire about the instruction institute that clocking information belongs to by interface controller 300, via bus
Whether corresponding Destination Storage Unit is finished；
Moderator 200, for being arbitrated in bus free based on preset strategy to the bus request received, and base
Bus is distributed in arbitration result.
Illustratively, interface controller 300 are additionally operable to report each storage unit in memory 400 to command supervisor 100
Status information；
Command supervisor 100 is additionally operable to the shape of each storage unit in the memory 400 reported based on interface controller 300
State information, whether the corresponding Destination Storage Unit of instruction of highest priority is in preparation state during decision instruction queue caches,
If so, the instruction for judging highest priority is executable instruction；
If it is not, then continue to judge whether the corresponding Destination Storage Unit of instruction of time high priority is in preparation state, directly
To judging the Destination Storage Unit in preparation state, and will operate target is in the Destination Storage Unit for preparing state
The instruction of highest priority is determined as executable instruction.
Illustratively, command supervisor 100 are additionally operable in being cached from the pending instruction of reading to instruction queue, wherein,
The priority of instruction in instruction queue caching is consistent with the sequencing that instruction is read to instruction queue in caching；
When interface controller 300 sends executable instruction corresponding Destination Storage Unit into memory 400, instructing
Queue caching deletes executable instruction, and continues to read pending instruction into instruction queue caching from processor.
Illustratively, interface controller 300 are additionally operable to parsing executable instruction, obtain the poll mark of executable instruction；
Interface controller 300 is additionally operable to need to inquire about corresponding target storage list when poll mark characterization executable instruction
The clocking information of executable instruction is then read to snoop queue and cached by the state of member, and deletion can in instruction queue caching
It executes instruction；
Interface controller 300 is additionally operable to that when poll mark characterization executable instruction corresponding target storage need not be inquired about
The state of unit deletes executable instruction in instruction queue caching；Wherein, the clocking information in snoop queue caching is preferential
Grade sequence is corresponding with the sequencing that clocking information is read to instruction queue in caching.
Illustratively, poll manager 500 is additionally operable to when clocking information is read to snoop queue and caches, to timing
Information carries out timing processing；Bus is asked to moderator 200 when clocking information is reached.
Illustratively, moderator 200 is additionally operable to be received at the same time from command supervisor 100 for executable instruction
During the bus request that bus request and poll manager 500 are sent after being reached for the clocking information in snoop queue caching,
Bus is distributed to be directed to the bus request of executable instruction；
Moderator 200 is additionally operable to receive poll manager 500 at the same time at least two in snoop queue caching
During at least two bus request that clocking information is sent simultaneously after reaching, to be directed to highest priority at least two clocking informations
Clocking information bus request distribution bus.
Illustratively, poll manager 500 is additionally operable to the finger for inquiring clocking information by interface controller 300 and belonging to
When the corresponding Destination Storage Unit of order is finished, clocking information is deleted from snoop queue caching；
Poll manager 500 is additionally operable to inquire corresponding to the instruction of clocking information ownership by interface controller 300
When Destination Storage Unit is not carried out finishing, update snoop queue caching in clocking information and for updated clocking information into
Row timing is handled, wherein the stand-by period of updated clocking information is less than the stand-by period of timing time before update.
Based on the description to the function of the execution of above-mentioned functional unit in the embodiment of the present invention, above-mentioned functional unit can be with
There is the realization (such as merge into two functional units or be split as the functional unit of four or more) of other forms；Therefore, this hair
The electronic equipment shown in Fig. 1 is combined in bright embodiment to illustrate record method of the embodiment of the present invention, is not formed to this hair
Bright restriction.
In the embodiment of the present invention, by the data processing structure of pure hardware realization (FPGA or CPLD are realized) to coming from host
The write command and reading instruction at end are responded, and idle bus are arbitrated based on preset strategy by moderator, with according to secondary
It cuts out result and executable instruction is sent to Destination Storage Unit to realize reading and writing data or inquire about target storage according to arbitration result
Whether unit is finished the instruction sent；It is achieved thereby that the interactive operation to different storage units, execution efficiency and reality
Shi Xinggao.
One of ordinary skill in the art will appreciate that：Realizing all or part of step of above method embodiment can pass through
The relevant hardware of program instruction is completed, and foregoing program can be stored in a computer read/write memory medium, the program
Upon execution, the step of execution includes above method embodiment；And foregoing storage medium includes：It is movable storage device, read-only
Memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disc or
The various media that can store program code such as person's CD.
If alternatively, the above-mentioned integrated unit of the present invention is realized in the form of software function module and is independent product
Sale in use, can also be stored in a computer read/write memory medium.Based on such understanding, the present invention is implemented
The technical solution of example substantially in other words can be embodied the part that the prior art contributes in the form of software product,
The computer software product is stored in a storage medium, and being used including some instructions (can be with so that computer equipment
It is personal computer, server or network equipment etc.) perform all or part of each embodiment method of the present invention.It is and preceding
The storage medium stated includes：Various Jie that can store program code such as movable storage device, ROM, RAM, magnetic disc or CD
Matter.
More than, it is only specific embodiment of the invention, but protection scope of the present invention is not limited thereto, and it is any to be familiar with
Those skilled in the art in the technical scope disclosed by the present invention, can readily occur in change or replacement, should all cover
Within protection scope of the present invention.Therefore, protection scope of the present invention should be subject to the protection scope in claims.
Claims (14)
1. a kind of data processing method, which is characterized in that the described method includes：
The priority instructed in being cached based on instruction queue chooses executable instruction, and bus request is sent for selected instruction
To ask bus；
The executable instruction corresponding Destination Storage Unit into memory is sent by bus when request is to bus, and will
The clocking information of the executable instruction reads to snoop queue and caches；
Arbitrary clocking information sends bus request to ask bus in snoop queue caching after reaching, to be arrived in request
During bus, whether the Destination Storage Unit inquired about by bus corresponding to the instruction of the clocking information ownership is finished；
The bus request received is arbitrated based on preset strategy in bus free, and it is total based on arbitration result distribution
Line.
2. data processing method as described in claim 1, which is characterized in that instructed in the caching based on instruction queue excellent
First grade chooses executable instruction, including：
Based on the status information of each storage unit in the memory, the finger of highest priority in described instruction queue caching is judged
Make whether corresponding Destination Storage Unit is in preparation state,
If so, judge the instruction of the highest priority for executable instruction；
If it is not, then continue to judge whether the corresponding Destination Storage Unit of instruction of time high priority is in preparation state, until sentencing
Disconnected source will operate target as the Destination Storage Unit in preparation state in the Destination Storage Unit for preparing state
The instruction of highest priority is determined as the executable instruction.
3. data processing method as described in claim 1, which is characterized in that the method further includes：
Read pending instruction to described instruction queue cache in, wherein, instruction queue caching in instruction priority with
The sequencing that described instruction is read to described instruction queue in caching is consistent；
When sending executable instruction corresponding Destination Storage Unit into the memory, cached in described instruction queue
The executable instruction is deleted, and continues to read pending instruction into described instruction queue caching from processor.
4. data processing method as described in claim 1, which is characterized in that the clocking information by executable instruction is read
It is cached to snoop queue, including：
The executable instruction is parsed, obtains the poll mark of the executable instruction；
It needs to inquire about the state of corresponding Destination Storage Unit if the poll mark characterizes the executable instruction, by described in
The clocking information of executable instruction reads to the snoop queue and caches, and can be held described in deletion in described instruction queue caching
Row instruction；
If the poll mark, which characterizes the executable instruction, need not inquire about the state of corresponding Destination Storage Unit, described
The executable instruction is deleted in instruction queue caching；Wherein, the priority row of the clocking information in the snoop queue caching
Sequence is corresponding with the sequencing that the clocking information is read to described instruction queue in caching.
5. data processing method as described in claim 1, which is characterized in that the arbitrary timing in snoop queue caching
Information sends bus request to ask bus after reaching, including：
When the clocking information is read to the snoop queue and caches, timing processing is carried out to the clocking information；
Bus request is sent when the clocking information reaches to ask bus.
6. data processing method as described in claim 1, which is characterized in that described that preset strategy pair is based in bus free
The bus request received is arbitrated, and distributes bus based on arbitration result, including：
Timing in being received simultaneously for the bus request of the executable instruction and being cached for the snoop queue is believed
During the bus request that breath is sent after reaching, bus is distributed to be directed to the bus request of the executable instruction；
At least two after at least two clocking informations in being cached for the snoop queue reach while sent are received simultaneously
It is total to be directed to the distribution of the bus request of the clocking information of highest priority at least two clocking information during a bus request
Line.
7. such as claim 1 to 6 any one of them data processing method, which is characterized in that it is described inquired about by bus described in
Whether the corresponding Destination Storage Unit of instruction that clocking information is belonged to is finished, including：
When the Destination Storage Unit inquired by bus corresponding to the instruction that the clocking information belongs to is finished, from described
The clocking information is deleted in snoop queue caching；
When the Destination Storage Unit inquired by bus corresponding to the instruction of the clocking information ownership is not carried out finishing, update
The clocking information in snoop queue caching simultaneously carries out timing processing for the updated clocking information, wherein more
The stand-by period of the clocking information after new is less than the stand-by period of the timing time before update.
8. a kind of electronic equipment, which is characterized in that the electronic equipment includes：
Command supervisor, the priority for instructing in being cached based on instruction queue chooses executable instruction, for selected
It instructs and sends bus request to moderator to ask bus；
Interface controller, for sending the executable instruction to depositing by bus when described instruction manager request is to bus
Corresponding Destination Storage Unit in reservoir, and the clocking information of the executable instruction is read to snoop queue and is cached；
Poll manager, in snoop queue caching arbitrary clocking information reach after send bus request to ask
Bus, when request is to bus, to inquire about the instruction institute that the clocking information belongs to by the interface controller, via bus
Whether corresponding Destination Storage Unit is finished；
Moderator, for being arbitrated in bus free based on preset strategy to the bus request received, and based on arbitration
As a result bus is distributed.
9. electronic equipment as claimed in claim 8, which is characterized in that the interface controller is additionally operable to described instruction pipe
Reason device reports the status information of each storage unit in the memory；
Described instruction manager is additionally operable to the state of each storage unit in the memory reported based on the interface controller
Whether information judges the corresponding Destination Storage Unit of instruction of highest priority in described instruction queue caching in preparation shape
State,
If so, judge the instruction of the highest priority for executable instruction；
If it is not, then continue to judge whether the corresponding Destination Storage Unit of instruction of time high priority is in preparation state, until sentencing
Disconnected source will operate target as the Destination Storage Unit in preparation state in the Destination Storage Unit for preparing state
The instruction of highest priority is determined as the executable instruction.
10. electronic equipment as claimed in claim 8, which is characterized in that
Described instruction manager is additionally operable in being cached from the pending instruction of reading to described instruction queue, wherein, described instruction
The priority of instruction in queue caching is consistent with the sequencing that described instruction is read to described instruction queue in caching；
Described instruction manager is additionally operable to corresponding into the memory in the interface controller transmission executable instruction
Destination Storage Unit when, delete the executable instruction in described instruction queue caching, and continue to read from processor to wait to hold
During capable instruction is cached to described instruction queue.
11. electronic equipment as claimed in claim 8, which is characterized in that the interface controller is additionally operable to hold described in parsing
Row instruction obtains the poll mark of the executable instruction；
The interface controller is additionally operable to deposit when poll mark characterizes the executable instruction and needs to inquire about corresponding target
During the state of storage unit, the clocking information of the executable instruction is read to the snoop queue and is cached, and in described instruction
The executable instruction is deleted in queue caching；
The interface controller is additionally operable to that when poll mark characterizes the executable instruction corresponding target need not be inquired about
During the state of storage unit, the executable instruction is deleted in described instruction queue caching；Wherein, the snoop queue caching
In priority ranking and the clocking information of clocking information be read to described instruction queue sequencing pair in caching
It should.
12. electronic equipment as claimed in claim 8, which is characterized in that the poll manager is additionally operable to believe in the timing
Breath be read to the snoop queue cache when, to the clocking information progress timing processing；When the clocking information reaches
Bus is asked to the moderator.
13. electronic equipment as claimed in claim 8, which is characterized in that the moderator is additionally operable to receive at the same time and comes from
Described instruction manager is directed to the snoop queue for the bus request of the executable instruction and the poll manager
It is total to be directed to the distribution of the bus request of the executable instruction during bus request that the clocking information in caching is sent after reaching
Line；
The moderator is additionally operable to receive the poll manager at the same time at least two in snoop queue caching
During at least two bus request that a clocking information is sent simultaneously after reaching, to be directed to highest at least two clocking information
The bus request distribution bus of the clocking information of priority.
14. such as claim 8 to 13 any one of them electronic equipment, which is characterized in that the poll manager is additionally operable to lead to
When crossing the Destination Storage Unit that the interface controller is inquired corresponding to the instruction of clocking information ownership and being finished, from
The clocking information is deleted in the snoop queue caching；
The poll manager is additionally operable to inquire corresponding to the instruction of the clocking information ownership by the interface controller
Destination Storage Unit when being not carried out finishing, update the clocking information in the snoop queue caching and for the update
Clocking information afterwards carries out timing processing, wherein the stand-by period of the updated clocking information is less than the timing before update
The stand-by period of time.
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| CN201510629598.5A CN105243033B (en) | 2015-09-28 | 2015-09-28 | Data processing method and electronic equipment |
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| CN201510629598.5A CN105243033B (en) | 2015-09-28 | 2015-09-28 | Data processing method and electronic equipment |
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| CN109408243A (en) * | 2018-11-13 | 2019-03-01 | 郑州云海信息技术有限公司 | A kind of data processing method based on RDMA, device and medium |
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