CN113871384A - 晶体管器件结构 - Google Patents

晶体管器件结构 Download PDF

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CN113871384A
CN113871384A CN202010611970.0A CN202010611970A CN113871384A CN 113871384 A CN113871384 A CN 113871384A CN 202010611970 A CN202010611970 A CN 202010611970A CN 113871384 A CN113871384 A CN 113871384A
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翁文寅
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Abstract

本发明涉及晶体管器件结构，涉及半导体集成电路技术，在包括核心器件和输入输出器件的晶体管器件，由场氧化层在半导体衬底上隔离出核心器件区域的有源区和输入输出器件区域的有源区，在核心器件区域的有源区内形成栅极环绕的栅极结构，在输入输出器件区域的有源区内形成的鳍式栅极结构，如此可改善核心器件的短沟道效应，且输入输出器件的鳍式栅极结构的栅介质层的厚度不受栅极环绕的栅极结构的沟道线体之间的间距的影响，而使得在改善核心器件的短沟道效应的基础上输入输出器件的导通电流和关断电流性能不受影响。

Description

晶体管器件结构
技术领域
本发明涉及半导体集成电路技术，尤其涉及一种晶体管器件结构。
背景技术
现有先进逻辑芯片中，通常包括n型场效应晶体管(FET)即nFET和p型场效应晶体管即pFET，且通常包括作为核心(Core)器件的nFET和pFET以及作为输入输出(I/O)器件的nFET和pFET。请参阅图1，图1为现有的晶体管器件结构示意图，如图1所示，在半导体衬底100上形成有场氧化层101，场氧化层101通常采用浅沟槽隔离(STI)工艺形成。场氧化层101隔离出有源区，有源区包括核心(Core)器件区域的有源区和输入输出(I/O)器件区域的有源区，核心器件区域的有源区中形成有核心器件，输入输出器件区域的有源区中形成有输入输出器件。如图1所示，在核心(Core)器件区域的有源区中形成有核心nFET的栅极结构131和核心pFET的栅极结构141，在输入输出(I/O)器件区域的有源区中形成有输入输出nFET的栅极结构111和输入输出pFET的栅极结构121。每一所述栅极结构包括多晶硅栅112、由氮化层113和氧化层114叠加而成的硬质掩模层和侧墙115。其中多晶硅栅112覆盖区域的半导体衬底100的表面形成沟道区，如图1所示，输入输出(I/O)器件的沟道长度较核心(Core)器件的沟道长度长。
随着半导体技术的不断发展，如图1所示的平面性器件已经不能满足人们对高性能器件的需求。FinFET(Fin Field-Effect Transistor，鳍式场效应晶体管)应运而生，其是一种立体型器件，相对于平面式晶体管，鳍式场效应晶体管(FinFET)具有立体式沟道结构，故具有更好的导通电流和关断电流特性，也能改善短沟道效应(SCE)。鳍式晶体管通常包括鳍体，鳍体由形成于半导体衬底上的纳米条或纳米片组成。同一半导体衬底上的鳍体平行排列且各鳍体之间隔离有介质层。栅极结构覆盖在部分长度的鳍体的顶部表面和侧面，被栅极结构覆盖的鳍体的表面用于形成沟道，也即在鳍体的顶部表面和两个侧面都具有沟道。通常栅极结构包括叠加而成的栅介质层和栅导电材料层。源区和漏区形成在栅极结构两侧的鳍体中。
随着半导体技术的发展及市场需求，器件尺寸不断缩小。5nm工艺节点以下时，鳍式场效应晶体管会应用采用了纳米线(nanowire)或纳米片(nanosheet)的栅极环绕(Gate-All-Around，GAA)结构，其可进一步改善短沟道效应(SCE)。请参阅图2，图2为栅极环绕结构的示意图，如图2所示，栅极环绕结构包括形成于半导体衬底上的鳍体110上的线体144。半导体器件的沟道区形成在线体144中，在沟道区即线体144的周侧形成有栅介质层122。在栅介质层122的周侧及栅介质层122与半导体衬底之间形成有功函数层133。GAA结构可有效改善器件的短沟道效应(SCE)。
如图2所示，线体144包括了垂直堆叠在鳍体110上的两个，两线体144之间有一定间隙。如图2所示，假设线体144的直径d1为10nm，两线体144之间的间距d2为20nm，则栅介质层122的厚度必须小于5nm，若栅介质层122的厚度大于5nm，则栅介质层122就会连在一起，如图3所示的栅介质层较厚时的栅极环绕结构的示意图，如此会影响器件的导通电流和关断电流(Ion/Ioff)性能，否者就要牺牲线体144的尺寸来增大栅介质层122的厚度。因此对于输入输出(I/O)器件来说，采用GAA结构将影响其器件性能。
发明内容
本发明提供的晶体管器件结构，包括：半导体衬底，半导体衬底内形成有场氧化层，场氧化层隔离出有源区，有源区包括核心器件区域的有源区和输入输出器件区域的有源区，核心器件区域的有源区用于形成核心器件，输入输出器件区域的有源区用于形成输入输出器件；多个鳍体，包括位于输入输出器件区域的鳍体以及位于核心器件区域的鳍体，多个鳍体为对半导体衬底上的外延层进行光刻刻蚀后形成的条状结构，各鳍体平行排列，所述多个鳍体的底部通过形成于半导体衬底上的第一绝缘层彼此隔离，其中，位于核心器件区域的鳍体的位于第一绝缘层上方的部分包括由半导体材料组成的线体，线体的部分长度的周侧被第一栅介质层包覆，在第一栅介质层的周侧及第一栅介质层与第一绝缘层之间形成有第一功函数层，位于输入输出器件区域的鳍体的位于第一绝缘层上方的部分的顶表面和侧面形成有第二栅介质层，第二栅介质层的表面形成有第二功函数层；以及金属栅，覆盖第一功函数层和第二功函数层的顶表面和侧面，并填充第一功函数层之间的间隙、第二功函数层之间的间隙以及第一功函数层与第二功函数层之间的间隙，所述金属栅覆盖的位于输入输出器件区域的鳍体的部分形成输入输出器件的沟道区，所述金属栅覆盖的位于核心器件区域的线体的部分形成核心器件的沟道区。
更进一步的，位于输入输出器件区域的鳍体的位于第一绝缘层上方的部分包括至少一个硅和锗硅外延层的叠加层。
更进一步的，线体包括垂直堆叠的两个，两个线体的部分长度的周侧均被第一栅介质层包覆，在第一栅介质层的周侧、第一栅介质层之间及第一栅介质层与第一绝缘层之间形成有第一功函数层，位于输入输出器件区域的鳍体的位于第一绝缘层上方的部分包括两个硅和锗硅外延层的叠加层。
更进一步的，半导体衬底为硅衬底，线体的半导体材料为硅。
更进一步的，第一栅介质层和第二栅介质层包括高介电常数层。
更进一步的，所述第一绝缘层为氧化层。
更进一步的，在位于核心器件区域的鳍体的核心器件的沟道区的两侧包括形成的源极和漏极，而形成n型栅极环绕结构场效应晶体管和p型栅极环绕结构场效应晶体管；在位于输入输出器件区域的鳍体的输入输出器件的沟道区的两侧包括形成的源极和漏极，而形成n型鳍式场效应晶体管和p型鳍式场效应晶体管。
更进一步的，所述源极和所述漏极都为嵌入式结构，n型鳍式场效应晶体管和n型栅极环绕结构场效应晶体管的源极和漏极由第一嵌入式外延层组成，p型鳍式场效应晶体管和p型栅极环绕结构场效应晶体管的源极和漏极由第二嵌入式外延层组成。
更进一步的，线体的剖面结构包括圆形或多边形。
更进一步的，所述晶体管器件为5nm以下工艺节点的器件。
在包括核心器件和输入输出器件的晶体管器件，由场氧化层在半导体衬底上隔离出核心(Core)器件区域的有源区和输入输出(I/O)器件区域的有源区，在核心(Core)器件区域的有源区内形成栅极环绕的栅极结构，在输入输出(I/O)器件区域的有源区内形成的鳍式栅极结构，如此可改善核心(Core)器件的短沟道效应(SCE)，且输入输出(I/O)器件的鳍式栅极结构的栅介质层的厚度不受栅极环绕的栅极结构的沟道线体之间的间距的影响，而使得在改善核心(Core)器件的短沟道效应(SCE)的基础上输入输出(I/O)器件的导通电流和关断电流(Ion/Ioff)性能不受影响。
附图说明
图1为现有的晶体管器件结构示意图。
图2为栅极环绕结构的示意图。
图3为栅介质层较厚时的栅极环绕结构的示意图。
图4为本发明一实施例的晶体管器件的平面示意图。
图5为本发明一实施例的晶体管器件的剖面图。
图中主要组件附图标记说明如下：
200、半导体衬底；201、场氧化层；210、鳍体；220、第一绝缘层；211、第一氧化层线体；222、第一栅介质层；233、第一功函数层；322、第二栅介质层；333、第二功函数层；230、金属栅。
具体实施方式
下面将结合附图，对本发明中的技术方案进行清楚、完整的描述，显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在不做出创造性劳动的前提下所获得的所有其它实施例，都属于本发明保护的范围。
本发明一实施例中，在于提供一种晶体管器件结构，包括：半导体衬底，半导体衬底内形成有场氧化层，场氧化层隔离出有源区，有源区包括核心器件区域的有源区和输入输出器件区域的有源区，核心器件区域的有源区用于形成核心器件，输入输出器件区域的有源区用于形成输入输出器件；多个鳍体，包括位于输入输出器件区域的鳍体以及位于核心器件区域的鳍体，多个鳍体为对半导体衬底上的外延层进行光刻刻蚀后形成的条状结构，各鳍体平行排列，所述多个鳍体的底部通过形成于半导体衬底上的第一绝缘层彼此隔离，其中，位于核心器件区域的鳍体的位于第一绝缘层上方的部分包括由半导体材料组成的线体，线体的部分长度的周侧被第一栅介质层包覆，在第一栅介质层的周侧及第一栅介质层与第一绝缘层之间形成有第一功函数层，位于输入输出器件区域的鳍体的位于第一绝缘层上方的部分的顶表面和侧面形成有第二栅介质层，第二栅介质层的表面形成有第二功函数层；以及金属栅，覆盖第一功函数层和第二功函数层的顶表面和侧面，并填充第一功函数层之间的间隙、第二功函数层之间的间隙以及第一功函数层与第二功函数层之间的间隙，所述金属栅覆盖的位于输入输出器件区域的鳍体的部分形成输入输出器件的沟道区，所述金属栅覆盖的位于核心器件区域的线体的部分形成核心器件的沟道区。
请参阅图4和图5，图4为本发明一实施例的晶体管器件的平面示意图，图5为本发明一实施例的晶体管器件的剖面图，图5为沿图4的虚线AA处的剖面图。本发明的晶体管器件结构包括：
半导体衬底200，半导体衬底200上形成有场氧化层201，场氧化层201隔离出有源区，有源区包括核心(Core)器件区域的有源区和输入输出(I/O)器件区域的有源区，核心器件区域的有源区用于形成核心器件，输入输出器件区域的有源区用于形成输入输出器件；
多个鳍体210，包括位于输入输出(I/O)器件区域的鳍体以及位于核心(Core)器件区域的鳍体，多个鳍体210为对半导体衬底200上的外延层进行光刻刻蚀后形成的条状结构，各鳍体210平行排列，所述多个鳍体210的底部通过形成于半导体衬底200上的第一绝缘层220彼此隔离，其中，位于核心(Core)器件区域的鳍体210的位于第一绝缘层220上方的的部分包括由半导体材料组成的线体211，线体211的部分长度的周侧被第一栅介质层222包覆，在第一栅介质层222的周侧及第一栅介质层222与第一绝缘层220之间形成有第一功函数层233，位于输入输出(I/O)器件区域的鳍体210的位于第一绝缘层220上方的部分的顶表面和侧面形成有第二栅介质层322，第二栅介质层322的表面形成有第二功函数层333；以及
金属栅230，覆盖第一功函数层233和第二功函数层333的顶表面和侧面，并填充第一功函数层233之间的间隙、第二功函数层333之间的间隙以及第一功函数层233与第二功函数层333之间的间隙，所述金属栅230覆盖的位于输入输出(I/O)器件区域的鳍体210的部分形成输入输出(I/O)器件的沟道区，所述金属栅230覆盖的位于核心(Core)器件区域的线体211的部分形成核心(Core)器件的沟道区。
在一实施例中，半导体衬底200为硅衬底。在一实施例中，场氧化层201通常采用浅沟槽隔离(STI)工艺形成。
在一实施例中，位于输入输出(I/O)器件区域的鳍体210的位于第一绝缘层220上方的部分包括至少一个硅(Si)和锗硅(SiGe)外延层的叠加层。
在一实施例中，线体211包括垂直堆叠的两个，两个线体211的部分长度的周侧均被第一栅介质层222包覆，在第一栅介质层222的周侧、第一栅介质层222之间及第一栅介质层222与第一绝缘层220之间形成有第一功函数层233，则位于输入输出(I/O)器件区域的鳍体210的位于第一绝缘层220上方的部分包括两个硅(Si)和锗硅(SiGe)外延层的叠加层。本发明还可包括大于两个的垂直堆叠的线体211，本发明对此不作限定。
在本发明一实施例中，线体211的半导体材料为硅。在本发明一实施例中，线体211的剖面结构包括圆形或多边形,多边形如正方形，长方形，Σ形。
在一实施例中，第一栅介质层222和第二栅介质层322包括高介电常数层，所述高介电常数层的材料包括二氧化硅，氮化硅，三氧化二铝，五氧化二钽，氧化钇，硅酸铪氧化合物，二氧化铪，氧化镧，二氧化锆，钛酸锶，硅酸锆氧化合物。
在一实施例中，所述第一绝缘层220为氧化层。
更进一步地，在本发明一实施例中，在位于核心(Core)器件区域的鳍体的核心(Core)器件的沟道区的两侧包括形成的源极301和漏极302，而形成核心(Core)器件的栅极环绕(Gate-All-Around，GAA)结构场效应晶体管，在位于输入输出(I/O)器件区域的鳍体的输入输出(I/O)器件的沟道区的两侧包括形成的源极401和漏极402，而形成输入输出(I/O)器件的鳍式场效应晶体管。
在一实施例中，核心(Core)器件的栅极环绕(Gate-All-Around，GAA)结构场效应晶体管包括n型栅极环绕(Gate-All-Around，GAA)结构场效应晶体管311和p型栅极环绕(Gate-All-Around，GAA)结构场效应晶体管322，输入输出(I/O)器件的鳍式场效应晶体管包括n型鳍式场效应晶体管411和p型鳍式场效应晶体管422。在本发明一实施例中，所述源极和所述漏极都为嵌入式结构。n型鳍式场效应晶体管411和n型栅极环绕(Gate-All-Around，GAA)结构场效应晶体管311的源极和漏极由第一嵌入式外延层组成，所述第一嵌入式外延层的材料为SixPy，SimCn或SioCpPq，下标x，y，m，n，o，p，q分别表示对应原子在材料分子中的个数。p型鳍式场效应晶体管422和p型栅极环绕(Gate-All-Around，GAA)结构场效应晶体管322的源极和漏极由第二嵌入式外延层组成，所述第二嵌入式外延层的材料为SihGei，下标h，i分别表示对应原子在材料分子中的个数。
另，本发明的晶体管器件为5nm以下工艺节点的器件。
如上所述，在包括核心器件和输入输出器件的晶体管器件，由场氧化层在半导体衬底上隔离出核心(Core)器件区域的有源区和输入输出(I/O)器件区域的有源区，在核心(Core)器件区域的有源区内形成栅极环绕的栅极结构，在输入输出(I/O)器件区域的有源区内形成的鳍式栅极结构，如此可改善核心(Core)器件的短沟道效应(SCE)，且输入输出(I/O)器件的鳍式栅极结构的栅介质层的厚度不受栅极环绕的栅极结构的沟道线体之间的间距的影响，而使得在改善核心(Core)器件的短沟道效应(SCE)的基础上输入输出(I/O)器件的导通电流和关断电流(Ion/Ioff)性能不受影响。
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (10)

1.一种晶体管器件结构，其特征在于，包括：
半导体衬底，半导体衬底内形成有场氧化层，场氧化层隔离出有源区，有源区包括核心器件区域的有源区和输入输出器件区域的有源区，核心器件区域的有源区用于形成核心器件，输入输出器件区域的有源区用于形成输入输出器件；
多个鳍体，包括位于输入输出器件区域的鳍体以及位于核心器件区域的鳍体，多个鳍体为对半导体衬底上的外延层进行光刻刻蚀后形成的条状结构，各鳍体平行排列，所述多个鳍体的底部通过形成于半导体衬底上的第一绝缘层彼此隔离，其中，位于核心器件区域的鳍体的位于第一绝缘层上方的部分包括由半导体材料组成的线体，线体的部分长度的周侧被第一栅介质层包覆，在第一栅介质层的周侧及第一栅介质层与第一绝缘层之间形成有第一功函数层，位于输入输出器件区域的鳍体的位于第一绝缘层上方的部分的顶表面和侧面形成有第二栅介质层，第二栅介质层的表面形成有第二功函数层；以及
金属栅，覆盖第一功函数层和第二功函数层的顶表面和侧面，并填充第一功函数层之间的间隙、第二功函数层之间的间隙以及第一功函数层与第二功函数层之间的间隙，所述金属栅覆盖的位于输入输出器件区域的鳍体的部分形成输入输出器件的沟道区，所述金属栅覆盖的位于核心器件区域的线体的部分形成核心器件的沟道区。
2.根据权利要求1所述的晶体管器件结构，其特征在于，位于输入输出器件区域的鳍体的位于第一绝缘层上方的部分包括至少一个硅和锗硅外延层的叠加层。
3.根据权利要求1所述的晶体管器件结构，其特征在于，线体包括垂直堆叠的两个，两个线体的部分长度的周侧均被第一栅介质层包覆，在第一栅介质层的周侧、第一栅介质层之间及第一栅介质层与第一绝缘层之间形成有第一功函数层，位于输入输出器件区域的鳍体的位于第一绝缘层上方的部分包括两个硅和锗硅外延层的叠加层。
4.根据权利要求1所述的晶体管器件结构，其特征在于，半导体衬底为硅衬底，线体的半导体材料为硅。
5.根据权利要求1所述的晶体管器件结构，其特征在于，第一栅介质层和第二栅介质层包括高介电常数层。
6.根据权利要求1所述的晶体管器件结构，其特征在于，所述第一绝缘层为氧化层。
7.根据权利要求1所述的晶体管器件结构，其特征在于，在位于核心器件区域的鳍体的核心器件的沟道区的两侧包括形成的源极和漏极，而形成n型栅极环绕结构场效应晶体管和p型栅极环绕结构场效应晶体管；在位于输入输出器件区域的鳍体的输入输出器件的沟道区的两侧包括形成的源极和漏极，而形成n型鳍式场效应晶体管和p型鳍式场效应晶体管。
8.根据权利要求7所述的晶体管器件结构，其特征在于，所述源极和所述漏极都为嵌入式结构，n型鳍式场效应晶体管和n型栅极环绕结构场效应晶体管的源极和漏极由第一嵌入式外延层组成，p型鳍式场效应晶体管和p型栅极环绕结构场效应晶体管的源极和漏极由第二嵌入式外延层组成。
9.根据权利要求1所述的晶体管器件结构，其特征在于，线体的剖面结构包括圆形或多边形。
10.根据权利要求1所述的晶体管器件结构，其特征在于，所述晶体管器件为5nm以下工艺节点的器件。
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