CN113867060B - Display panel and display device - Google Patents
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- CN113867060B CN113867060B CN202110863839.8A CN202110863839A CN113867060B CN 113867060 B CN113867060 B CN 113867060B CN 202110863839 A CN202110863839 A CN 202110863839A CN 113867060 B CN113867060 B CN 113867060B
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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Abstract
The application discloses a display panel and a display device, which comprise a common line, wherein a plurality of data lines and a plurality of scanning lines are crisscrossed to form a plurality of pixel regions, and each pixel region is correspondingly provided with a sub-common line; the number of the data lines is m, and the number of the scanning lines is n; each horizontal routing line is correspondingly crossed with the data line, and two adjacent sub-common lines in the direction of the scanning line are communicated; each vertical routing line is correspondingly crossed with the scanning line and connects two adjacent sub-common lines in the direction of the data line; the number of the horizontal routing lines is less than or equal to m; the number of the vertical wires is less than or equal to n-1; the plurality of horizontal routing lines and the vertical routing lines connect all the sub-common lines to form the common line, and the delay of the data lines and the scanning lines is reduced by reducing the number of the horizontal routing lines and the vertical routing lines.
Description
Technical Field
The application relates to the technical field of display, in particular to a display panel and a display device.
Background
A TFT-LCD (thin Film transistor Liquid Crystal display), which is one of active matrix type Liquid Crystal displays, has the advantages of excellent performance, good large-scale production characteristic, high automation degree, low cost of raw materials and wide development space, and becomes a mainstream product in the new century;
for the TFT-LCD, the scan lines and the data lines control the pixel charging through the thin film transistors, and during the charging, the load of the data lines and the scan lines has a decisive influence on the charging efficiency of the pixel, which determines whether the pixel is charged sufficiently, and the data lines and the scan lines have a larger load due to parasitic capacitance and resistance, which affects the charging effect, so that the pixel is not charged sufficiently.
Disclosure of Invention
The present application provides a display panel and a display device, which reduce the load of data lines and scan lines and improve the problem of insufficient pixel charging.
The application discloses a display panel, which comprises a plurality of data lines, a plurality of scanning lines and a common line, wherein the common line comprises a plurality of sub-common lines; the data lines and the scanning lines are crisscrossed to form a plurality of pixel regions, and each pixel region is correspondingly provided with one sub-common line; the number of the data lines is m, and the number of the scanning lines is n; the common line further includes: each horizontal routing line is correspondingly and crossly arranged with the data line, and two adjacent sub-common lines in the scanning line direction are communicated; each vertical routing line is correspondingly crossed with the scanning line and connects two adjacent sub-common lines along the direction of the data line; the number of the horizontal routing lines is less than or equal to m; the number of the vertical wires is less than or equal to n-1; the sub-common lines are communicated by a plurality of horizontal lines and vertical lines to form the common lines, and the common lines receive common voltage signals.
Optionally, the number of the horizontal traces along one scan line direction is m/2, and the number of the vertical traces along one data line direction is n/2; one data line is arranged at every interval of the horizontal wiring, and one scanning line is arranged at every interval of the vertical wiring.
Optionally, there are m pixel regions along one scan line direction, and n pixel regions along one data line direction, so as to form a pixel region matrix with n rows and m columns; in the pixel regions along the odd-numbered rows, m/2 horizontal routing lines are respectively arranged corresponding to the data lines in the odd-numbered columns; m/2 horizontal routing lines are arranged in the pixel regions along the even rows and respectively correspond to the data lines in the even columns; in the pixel regions of odd columns, n/2 vertical routing lines are respectively arranged corresponding to the scanning lines of odd rows; and in the pixel area of the even-numbered data lines, n/2 horizontal routing lines are respectively arranged corresponding to the scanning lines of the even-numbered rows.
Optionally, in the pixel region of each column, x consecutive pixel regions form a pixel region group; x sub-common lines in a pixel area group are communicated through x-1 vertical routing lines in the pixel area group; the horizontal routing lines are arranged between every two adjacent pixel area groups along the scanning line direction so as to communicate the sub-common lines corresponding to the pixel area groups along the scanning line direction; each column of the pixel regions are divided into n/x pixel region groups, x is a natural number which is greater than or equal to 2 and less than or equal to n, and n/x is an integer.
Optionally, the display area includes a plurality of pixels, and the pixels include vertically arranged red, green and blue sub-pixels; m pixel regions are arranged along the scanning line direction, n pixel regions are arranged along the data line direction, and an n-row and m-column pixel region matrix is formed; m/3 pixels are arranged along the direction of the data line, n pixels are arranged along the direction of the scanning line, and one red sub-pixel, one green sub-pixel or one blue sub-pixel is arranged in each pixel region; the value of x is 3, and each pixel area group comprises the red sub-pixels, the green sub-pixels and the blue sub-pixels which are vertically arranged; the vertical wiring is arranged between the red sub-pixel and the green sub-pixel, and the vertical wiring is arranged between the green sub-pixel and the blue sub-pixel so as to communicate the three sub-common lines in the pixel area group.
Optionally, m horizontal routing lines are arranged in the pixel regions in the 3y-2 th row and are respectively arranged between every two adjacent pixel region groups along the scanning line direction to connect the sub-common lines corresponding to the pixel region groups arranged along the scanning line direction, where y is not less than 3y and is a natural number greater than zero.
Optionally, each of the sub-common lines includes a first sub-common line segment and a third sub-common line segment parallel to the scan line, a second sub-common line segment and a fourth sub-common line segment parallel to the data line, and the first sub-common line segment, the second sub-common line segment, the third sub-common line segment and the fourth sub-common line segment are sequentially connected end to end and arranged around the pixel region; the horizontal routing is connected with a third sub-common line segment of one sub-common line and a first sub-common line segment of another adjacent sub-common line segment; the vertical routing is connected with a second sub-common line segment of one sub-common line and a fourth sub-common line segment of another adjacent sub-common line segment.
Optionally, the display panel includes a first metal layer, a second metal layer and a transparent electrode layer, which are sequentially arranged from bottom to top; the scan line and the common line are formed at the first metal layer; the data line is formed on the second metal layer; the pixel electrode is formed on the transparent electrode layer; the pixel electrode and the common line form a storage capacitor; the horizontal routing is formed on the first metal layer; the vertical routing lines are formed on the transparent electrode layer; the vertical routing line is connected with two adjacent sub-common lines through a via hole.
The application also discloses a display panel, including display area and non-display area, be provided with in the display area: m data lines, n scan lines, and a common line; the m data lines and the n scanning lines are crisscrossed to form a plurality of pixel regions; the common line receives a common voltage signal;
the common line includes: a plurality of sub common lines, a plurality of horizontal routing lines and a plurality of vertical routing lines; one sub-common line is correspondingly arranged in each pixel region; each horizontal routing line is correspondingly crossed with the data line and connects two adjacent sub-common lines along the scanning line direction; each vertical routing line is correspondingly crossed with the scanning line and is used for communicating two adjacent sub-common lines in the data line direction, and the horizontal routing lines and the vertical routing lines are used for communicating the sub-common lines to form the common lines;
each sub-common line comprises a first sub-common line segment and a third sub-common line segment which are parallel to the data line, a second sub-common line segment and a fourth sub-common line segment which are parallel to the scanning line, and the first sub-common line segment, the second sub-common line segment, the third sub-common line segment and the fourth sub-common line segment are arranged around the pixel area in an end-to-end communication mode; the horizontal routing is connected with a third sub-common line segment of one sub-common line and a first sub-common line segment of another adjacent sub-common line segment; the vertical routing is connected with a second sub-common line segment of one sub-common line and a fourth sub-common line segment of another adjacent sub-common line segment;
the number of the horizontal routing lines in the scanning line direction is m/2, and the number of the vertical routing lines in the data line direction is n/2; one horizontal routing line is arranged at every interval of one data line, and one vertical routing line is arranged at every interval of one scanning line; the number of the horizontal routing lines in the direction of one data line is n/2, and the number of the vertical routing lines in the direction of one scanning line is m/2; the horizontal routing lines are arranged at intervals of two scanning lines, and the vertical routing lines are arranged at intervals of two data lines;
the display panel comprises a first metal layer, a second metal layer and a transparent electrode layer which are sequentially arranged from bottom to top; the scan line and the common line are formed at the first metal layer; the data line is formed on the second metal layer; the pixel electrode is formed on the transparent electrode layer; the pixel electrode and the common line form a storage capacitor; the horizontal routing is formed on the first metal layer; the vertical routing is formed on the transparent electrode layer; the vertical routing line is connected with two adjacent sub-common lines through a via hole.
The application also discloses a display device, which comprises the display panel and a driving circuit for driving the display panel.
Compared with the traditional technical scheme of arranging complete latticed common lines (the sub-common lines in every two adjacent pixel regions are communicated through horizontal routing lines or vertical routing lines), the method and the device have the advantages that the number of the horizontal routing lines and the number of the vertical routing lines are reduced, so that parasitic capacitance generated between the horizontal routing lines and the data lines can be reduced, the load (loading) of the data lines is reduced, the parasitic capacitance generated between the vertical routing lines and the scanning lines can be reduced, and the load (loading) of the scanning lines is reduced; the overlapping area between the common line and the data line or the scanning line is reduced, so that the effect of reducing the parasitic capacitance is achieved, the load of the data line and/or the scanning line is reduced, the pixel charging efficiency is improved, and the problem of insufficient pixel charging is solved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the application, are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:
fig. 1 is a schematic diagram of a display panel according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a display device according to an embodiment of the present application;
FIG. 3 is a diagram of a seed common line according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a seed common line according to another embodiment of the present application;
FIG. 5 is a schematic diagram of a seed common line according to another embodiment of the present application;
FIG. 6 is a schematic diagram of a seed common line according to another embodiment of the present application;
fig. 7 is a schematic diagram of a seed common line according to another embodiment of the present application.
10, a display device; 100. a display panel; 101. a display area; 102. a non-display area; 103. a first metal layer; 104. a second metal layer; 105. a transparent electrode layer; 110. a data line; 120. scanning a line; 130. a common line; 131. a sub common line; 132. horizontally wiring; 133. vertically routing; 134. a first sub-common line segment; 135. a second sub-common line segment; 136. a third sub-common line segment; 137. a fourth sub-common line segment; 140. a pixel region; 150. a group of pixel regions; 160. a pixel; 161. a red sub-pixel; 162. a green sub-pixel; 163. a blue sub-pixel; 200. a drive circuit.
Detailed Description
It is to be understood that the terminology, the specific structural and functional details disclosed herein are for the purpose of describing particular embodiments only, and are representative, but that the present application may be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.
In the description of the present application, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating relative importance or as implicitly indicating the number of technical features indicated. Thus, unless otherwise specified, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "plurality" means two or more. The terms "comprises" and any variations thereof, are intended to cover a non-exclusive inclusion, which may have the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or combinations thereof.
Further, terms of orientation or positional relationship indicated by "center", "lateral", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, are described based on the orientation or relative positional relationship shown in the drawings, are simply for convenience of description of the present application, and do not indicate that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present application.
Furthermore, unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly and may include, for example, fixed connections, removable connections, and integral connections; can be mechanically or electrically connected; either directly or indirectly through intervening media, or through both elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
The present application is described in detail below with reference to the figures and alternative embodiments.
As shown in fig. 1, the RGB pixels of fig. 1 are vertically arranged, and have a tri-gate structure, that is, the number of gate scan lines 120 is 3 times that of the original pixels, the number of data lines 110 is one third that of the original pixels, because the number of the data lines is reduced, the number of the source driving chips can be reduced to one third of the original design architecture, the number of the source driving chips is reduced, the number of the gate driving chips is increased, but the source driving chips are more complicated than the gate driving chips, and is very expensive, so that the cost can be greatly reduced by reducing the number of source driving chips, but the vertical arrangement of RGB causes the charging time per line to be only one third of that of the original panel, which easily causes insufficient charging, therefore, the present application discloses a display panel 100 as shown in fig. 1, including a plurality of data lines 110, a plurality of scan lines 120, and a common line 130, the common line 130 including a plurality of sub-common lines 131; a plurality of data lines 110 and a plurality of scanning lines 120 are criss-cross to form a plurality of pixel regions 140, and each pixel region 140 is provided with one sub-common line 131 correspondingly; wherein, there are m data lines 110 and n scan lines 120; the common line 130 further includes a plurality of horizontal traces 132, each of the horizontal traces 132 is disposed to intersect with the data line 110, and connects two adjacent sub-common lines 131 along the scan line 120; a plurality of vertical routing lines 133, each vertical routing line 133 being disposed to intersect with the scanning line 120, and communicating two adjacent sub-common lines 131 in a data line direction; the horizontal routing lines 132 and the vertical routing lines connect all the sub-common lines 131 to form the common line 130, and the common line 130 is connected to a common voltage signal; in fig. 1, each of the sub common lines 131 is connected to two horizontal lines 132 and a vertical line 133, and all the sub common lines 131 are connected to increase the area of the common line 130, thereby reducing the resistance of the common line 130, and reducing the loss of the common line 130 of the display panel 100 with the triple-gate structure; however, parasitic capacitances may exist between the excessive horizontal and vertical traces 132 and 133 and the data and scan lines 110 and 120, resulting in an increase in the load of the data line 110, and for this, the applicant discloses the following several solutions.
As shown in fig. 2 and 3, the present application discloses a display device 10, which includes a driving circuit 200 and a display panel 100, wherein the display panel 100 includes a display area 101 and a non-display area 102; a plurality of data lines 110, a plurality of scan lines 120 and a common line 130 are disposed in the display region 101, and the common line 130 includes a plurality of sub-common lines 131; a plurality of pixel regions 140 are formed by crisscross arrangement of the data lines 110 and the scan lines 120, and one sub-common line 131 is correspondingly arranged in each pixel region 140; wherein, there are m data lines 110 and n scan lines 120; the common line 130 further includes a plurality of horizontal traces 132, each of the horizontal traces 132 is disposed to intersect with the data line 110, and connects two adjacent sub-common lines 131 along the scan line 120; a plurality of vertical traces 133, each of the vertical traces 133 being disposed to intersect with the scan lines 120 and connecting two adjacent sub-common lines 131 in a data line direction; the number of the horizontal routing lines 132 is less than or equal to m; the number of the vertical wires 133 is less than or equal to n-1; the plurality of horizontal routing lines 132 and the vertical routing lines connect all the sub-common lines 131 to form the common line 130, and the common line 130 is connected to a common voltage signal.
Compared with the traditional scheme that the whole common line 130 is arranged in the direction of the scanning line 120 or the data line, the parasitic capacitance generated between the horizontal routing line 132 and the data line 110 can be reduced by reducing the quantity of the horizontal routing line 132 and the vertical routing line 133, so that the load of the data line 110 is reduced, the parasitic capacitance generated between the vertical routing line 133 and the scanning line 120 is reduced, and the load of the scanning line 120 is reduced; that is, the overlapping area between the common line 130 and the data line 110 or the scan line 120 is reduced, thereby achieving an effect of reducing parasitic capacitance, and thus reducing the load of the data line 110 and the scan line 120.
As shown in fig. 3, the display panel 100 includes a first metal layer 103, a second metal layer 104 and a transparent electrode layer 105 sequentially arranged from bottom to top; the scan line 120 and the common line 130 are formed on the first metal layer 103; the data line 110 is formed on the second metal layer 104; the pixel electrode is formed on the transparent electrode layer 105; the scanning lines 120 and the data lines 110 intersect to form pixel regions 140; the pixel electrode and the common line 130 are correspondingly disposed in the pixel region 140; the display panel 100 includes a display area 101 and a non-display area 102; a plurality of data lines 110, a plurality of scanning lines 120 and a common line 130 are arranged in the display region 101, and the common line 130 includes a plurality of sub-common lines 131; the data lines 110 and the scan lines 120 are crisscross to form a plurality of pixel regions 140, and a sub-common line 131 is disposed in each pixel region 140.
As shown in fig. 3, the number of the horizontal traces 132 along one scan line 120 is m/2, and the number of the vertical traces 133 along one data line is n/2; the horizontal traces 132 are disposed one every other data line 110, and the vertical traces 133 are disposed one every other scan line 120.
In the above embodiment, a scheme in which four sides with respect to each sub common line 131 are communicated with the adjacent sub common line 131 through two horizontal routing lines 132 and two vertical routing lines 133; each of the sub common lines 131 is connected to the adjacent other sub common line 131 only by one horizontal routing line 132; each of the sub common lines 131 is connected to the adjacent other sub common line 131 only by one vertical routing line 133, such that each sub common line 131 is connected to only one horizontal trace 132 and vertical trace 133, all the sub common lines 131 may also be connected by half the number of the horizontal routing lines 132 of the data lines 110 and half the number of the vertical routing lines 133 of the scan lines 120, and one horizontal trace 132 is disposed at every other data line 110, one vertical trace 133 is disposed at every other scan line 120, and the number of the horizontal trace 132 and the vertical trace 133 is halved, so that not only the parasitic capacitance to the data line 110 and the scan line 120 can be reduced, and the spacing is uniform, so that the parasitic capacitance of the data lines 110 and the scan lines 120 of the display area 101 is more uniform, the display is more uniform, the problem of insufficient charging is solved by reducing the load of the data lines 110 and the scanning lines 120, and meanwhile, the problem of uneven display brightness caused by that the brightness of one part of the area is increased while the brightness of the other part is not increased is avoided.
As shown in fig. 3, on the basis of the above embodiment, further settings are made: m pixel regions 140 are arranged along one scanning line 120, and n pixel regions 140 are arranged along one data line; wherein, along the pixel region 140 of the odd row scan line 120, m/2 horizontal routing lines 132 are respectively disposed corresponding to the data lines 110 in the odd columns; along the pixel regions 140 of the even-numbered scan lines 120, m/2 horizontal routing lines 132 are respectively arranged corresponding to the data lines 110 in the even-numbered columns; along the pixel region 140 of the odd-numbered column data line 110, n/2 vertical routing lines 133 are respectively arranged corresponding to the scanning lines 120 of the odd-numbered rows; along the pixel region 140 of the even column data line 110, n/2 vertical traces 132 are respectively disposed corresponding to the scan lines 120 of the even rows.
As shown in fig. 3, in the above embodiment, the first row and first column sub common line 131 and the second row and first column sub common line 131 are communicated with each other through the vertical routing line 133, the second row and first column sub common line 131 is communicated with the second row and second column sub common line 131, the second row and second column sub common line 131 is communicated with the third row and second column sub common line 131 through the vertical routing line 133, and then the vertical routing line 133 sequentially communicates the sub common lines 131 on the diagonal lines of the display panel 100 to the common line 130, and all the sub common lines 131 are communicated with each other through the step-shaped connection routing line, so that the horizontal routing line 132 and the vertical routing line 133 are reduced, and at the same time, the problem that some regions are connected only in series to cause large resistance is avoided, the resistance loss is reduced through the parallel connection, and the loads of the data line 110 and the scan line 120 are also reduced, thereby enabling a uniform effect to be displayed.
It should be noted that, each pixel region 140 in fig. 3 is a red sub-pixel 161, a green sub-pixel 162, or a blue sub-pixel 163, and each pixel 160 includes a red sub-pixel 161, a green sub-pixel 162, and a blue sub-pixel 163, which are vertically arranged, in this embodiment, the pixels are arranged in a way of vertically arranging RGB, and the pixel is a tri-gate architecture, so that the number of scan lines 120 is 3 times that of the original, and the number of data lines 110 is 1/3, but the number of pixels in each column is not changed, so that the ultra high definition display in the original horizontal RGB arrangement still maintains the ultra high definition pixel standard after vertically arranging RGB, for the tri-gate architecture, the charging time of each line is only one third of the charging time of the horizontal RGB arrangement, which is easy to cause insufficient charging, and the application reduces the parasitic capacitance of the data lines 110 and the scan lines 120, so that the load of the data lines 110 and the scan lines 120 is reduced, so that the charging delay is reduced to improve the charging efficiency.
As shown in fig. 4, which is a partially enlarged schematic view of fig. 3 of the present application, each of the sub-common lines 131 in fig. 4 includes a first sub-common line segment 134 and a third sub-common line segment 136 parallel to the data line 110, a second sub-common line segment 135 and a fourth sub-common line segment 137 parallel to the scan line 120, and the first sub-common line segment 134, the second sub-common line segment 135, the third sub-common line segment 136 and the fourth sub-common line segment 137 are connected end to end; the horizontal routing line 132 connects the third sub-common line segment 136 of one sub-common line 131 with the first sub-common line segment 134 of another adjacent sub-common line 131; the vertical trace 133 connects the second sub-common line segment 135 of one sub-common line 131 with the fourth sub-common line segment 137 of another adjacent sub-common line 131; by lengthening the length of the sub common line 131, the overlapping area of the sub common line 131 and the pixel electrode is made larger, so that the storage capacitance is made larger, and more electric energy is stored when displaying. As shown in fig. 4, the horizontal trace 132 is disposed in the middle of the third sub-common line segment 136 and is far away from the active switch disposed in the pixel region 140, and the vertical trace 133 is also disposed at one end of the fourth sub-common line segment 137, which is far away from the active switch in the pixel region 140, so that the horizontal trace 132 and the vertical trace 133 avoid the active switch, prevent the trace from interfering with the active switch, and reduce the parasitic capacitance.
Referring to fig. 5, in another embodiment different from that shown in fig. 3, in each column of the pixel regions 140, x consecutive pixel region groups 150 are grouped into one pixel region group 150; x pieces of the sub-common lines 131 in one pixel area group 150 are communicated with each other through x-1 vertical wires 133 in the pixel area group 150; one horizontal routing line 132 is arranged between every two adjacent pixel area groups 150 along the scanning line 120 to communicate the sub common lines 131 corresponding to the pixel area groups 150 arranged along the scanning line 120; each column of the pixel regions 140 is divided into n/x pixel region groups 150, where x is a natural number greater than or equal to 2 and less than or equal to n, and n/x is an integer. Different from the previous embodiment, the number of the vertical wires 133 in this embodiment is relatively large, the number of the horizontal wires 132 is relatively small, the vertical wires 133 are disposed on the transparent electrode layer 105 and are far away from the scan lines 120 of the first metal layer 103, and the generated parasitic capacitance is small, the horizontal wires 132 are disposed on the first metal layer 103 and are close to the data lines 110 disposed on the second metal layer 104, and the generated parasitic capacitance is large, and the number of the horizontal wires 132 is set to be less, which is beneficial to reducing the load of the data lines 110, and therefore, the charging efficiency can also be improved.
As shown in fig. 5, in the case where x is equal to 3, the display region 101 includes a plurality of pixels including vertically arranged red, green, and blue sub-pixels; that is, one pixel region 140 is a red sub-pixel, a green sub-pixel, or a blue sub-pixel, and each of the pixel region groups 150 includes the red sub-pixel, the green sub-pixel, and the blue sub-pixel arranged vertically; m pixel regions 140 are arranged along the scanning line 120, and n pixel regions are arranged along the data line; m/3 pixels are arranged along the direction of the data line, n pixels are arranged along the direction of the scanning line 120, and one red sub-pixel, one green sub-pixel or one blue sub-pixel is arranged in each pixel region 140. In the present embodiment, the number of the scan lines 120 is 3 times that of the original scan lines 110, and the number of the data lines 110 is 1/3, but the number of the pixels in each column is not changed, so that the ultra high definition display in the horizontal RGB arrangement still maintains the ultra high definition pixel standard after the RGB arrangement, and for the tri-gate architecture, the charging time of each row is only one third of the charging time of the display panel 100(RGB sub-pixel horizontal arrangement) in the normal gate architecture, which is very easy to cause insufficient charging.
As shown in fig. 5, one embodiment of the present application is: m horizontal routing lines 132 are arranged between the 3y-2 th row of scanning lines 120 and the second row of scanning lines 120, where 3y is m, y is a natural number greater than zero, and m horizontal routing lines 132 are arranged every three scanning lines 120 along the direction of each data line 110; the horizontal routing 132 is provided with one horizontal routing 132 every three rows of the scanning lines 120, and the horizontal routing 132 is provided in the first row; adjacent two sub common lines 131 are communicated with each other by one horizontal routing line 132. The sub common lines 131 of every three rows in fig. 6 are communicated by the horizontal routing lines 132 of the first row such that the sub common line 131 of each pixel area group 150 corresponding to each pixel area 140 is communicated, and each pixel area group 150, that is, the inner sub common line 131 of each pixel is communicated together such that the common line 130 of the entire display area 101 is communicated by a small number of horizontal routing lines 132 and vertical routing lines 133, while reducing the load of the data lines 110 and the scan lines 120, ensuring that the function of the common line 130 is not affected.
Of course, the present application is also applicable to the laterally arranged RGB pixels, and as shown in fig. 6, the display region 101 includes a plurality of pixels 160 including horizontally arranged red, green and blue sub-pixels 161, 162 and 163; m pixel regions 140 are arranged along the data line direction, and n/3 pixel regions are arranged along the scanning line 120 direction; the number of the pixels is m along the data line direction, n/3 along the scan line 120 direction, and one pixel 160 is disposed in each pixel region 140.
It should be noted that the present embodiment also includes a first metal layer 103, a second metal layer 104 and a transparent electrode layer 105, which are sequentially arranged from bottom to top; the scan line 120 and the common line 130 are formed on the first metal layer 103; the data line 110 is formed on the second metal layer 104; the pixel electrode is formed on the transparent electrode layer 105; the pixel electrode forms a storage capacitor with the common line 130; the horizontal trace 132 is formed on the first metal layer 103; the vertical routing lines 133 are formed on the transparent electrode layer 105; the vertical routing line 133 connects the two adjacent sub-common lines 131 by a via.
As shown in fig. 7, the present application discloses a display panel 100,
the display device comprises a display area 101 and a non-display area 102, wherein the display area 101 is internally provided with: m data lines 110, n scan lines 120, and a common line 130; the m data lines 110 and the n scan lines 120 are crisscrossed to form a plurality of pixel regions 140, and one sub common line 131 is correspondingly arranged in each pixel region 140; the common line 130130 receives a common voltage signal;
the common line includes: a plurality of sub common lines 131, a plurality of horizontal routing lines 132, and a plurality of vertical routing lines 133; each horizontal routing line 132 is correspondingly arranged to intersect with the data line 110, and connects two adjacent sub-common lines 131 in the direction of the scan line 120; each of the vertical traces 133 is correspondingly disposed to intersect with the scan lines 120, and connects two adjacent sub-common lines 131 in the direction of the data lines 110, and the horizontal traces 132 and the vertical traces 133 connect all the sub-common lines 131 to form the common line 130;
wherein each of the sub common lines 131 includes a first sub common line segment 134 and a third sub common line segment 136 parallel to the data line 110, a second sub common line segment 135 and a fourth sub common line segment 137 parallel to the scan line, and the first sub common line segment 134, the second sub common line segment 135, the third sub common line segment 135 and the fourth sub common line segment 136 are disposed around the pixel region 140 in an end-to-end communication; the horizontal trace 132 connects the third sub-common line segment 136 of one sub-common line with the first sub-common line segment 134 of another adjacent sub-common line segment; the vertical trace 133 connects the second sub-common line segment 135 of one sub-common line with the fourth sub-common line segment 137 of another adjacent sub-common line segment;
the number of the horizontal routing lines 132 along one scanning line 120 is m/2, and the number of the vertical routing lines 133 along one data line 110 is n/2; one horizontal trace 132 is arranged at intervals of one data line 110, and one vertical trace 133 is arranged at intervals of one scanning line 120; the number of the horizontal routing lines 132 along one data line 110 is n/2, and the number of the vertical routing lines 133 along one scanning line 110 is m/2; every two scanning lines 120 are arranged between the horizontal routing lines 132, and every two data lines 110 are arranged between the vertical routing lines 133;
the display panel comprises a first metal layer 103, a second metal layer 104 and a transparent electrode layer 105 which are sequentially arranged from bottom to top; the scan line 120 and the common line 130 are formed on the first metal layer 103; the data line 110 is formed on the second metal layer 104; the pixel electrode is formed on the transparent electrode layer; the pixel electrode forms a storage capacitance with the common line 130; the horizontal trace 132 is formed on the first metal layer 103; the vertical routing lines 133 are formed on the transparent electrode layer 105; the vertical trace 133 connects two adjacent sub common lines 131 by a via.
Each of the sub common lines 131 includes a first sub common line segment 134 and a third sub common line segment 136 parallel to the data line 110, a second sub common line segment 135 and a fourth sub common line segment 137 parallel to the scan line 120, and the first sub common line segment 134, the second sub common line segment 135, the third sub common line segment 136 and the fourth sub common line segment 137 are connected end to end; the horizontal routing line 132 connects the third sub-common line segment 136 of one sub-common line 131 with the first sub-common line segment 134 of another adjacent sub-common line 131; the vertical trace 133 connects the second sub-common line segment 135 of one sub-common line 131 with the fourth sub-common line segment 137 of another adjacent sub-common line 131; the plurality of horizontal wires 132 and vertical wires 133 connect all the sub common lines 131 to form the common line 130, and the common line 130 is connected to a common voltage signal. The loads of the data lines 110 and the scanning lines 120 are reduced by reducing the horizontal routing lines 132 and the vertical routing lines 133, and the local resistance of the common lines 130 is prevented from being overlarge by uniformly and reasonably arranging the horizontal routing lines 132 and the vertical routing lines 133, so that the display uniformity is ensured.
The technical solution of the present application can be widely applied to various display panels, such as TN (Twisted Nematic) display panel, IPS (In-Plane Switching) display panel, VA (Vertical Alignment) display panel, MVA (Multi-Domain Vertical Alignment) display panel, and of course, other types of display panels, such as OLED (Organic Light-Emitting Diode) display panel, and the above solution can be applied thereto.
The foregoing is a more detailed description of the present application in connection with specific alternative embodiments, and the specific implementations of the present application are not to be considered limited to these descriptions. For those skilled in the art to which the present application pertains, several simple deductions or substitutions may be made without departing from the concept of the present application, and all should be considered as belonging to the protection scope of the present application.
Claims (10)
1. A display panel, comprising:
a plurality of data lines;
a plurality of scan lines; and
a common line including a plurality of sub-common lines; the data lines and the scanning lines are crisscrossed to form a plurality of pixel regions, and each pixel region is correspondingly provided with one sub-common line; the number of the data lines is m, the number of the scanning lines is n, and m and n are natural numbers which are more than or equal to 1;
the common line further includes:
each horizontal routing line is correspondingly crossed with the data line and connects two adjacent sub-common lines along the scanning line direction;
each vertical routing line is correspondingly crossed with the scanning line and is used for communicating two adjacent sub-common lines along the direction of the data line;
the sub common lines are communicated by a plurality of horizontal lines and vertical lines to form the common lines, and the common lines receive common voltage signals;
the number of the horizontal routing lines in the scanning line direction is m/2, and the number of the vertical routing lines in the data line direction is n/2;
the horizontal wiring is arranged one at every interval of one data line, and the vertical wiring is arranged one at every interval of one scanning line.
2. A display panel according to claim 1, wherein m of said pixel regions are provided along one of said scanning line directions, and n of said pixel regions are provided along one of said data line directions, forming a matrix of n rows and m columns of pixel regions;
in the pixel regions of the odd rows, m/2 horizontal routing lines are respectively arranged corresponding to the data lines of the odd columns; in the pixel areas of the even rows, m/2 horizontal routing lines are respectively arranged corresponding to the data lines of the even columns;
in the pixel regions of odd columns, n/2 vertical wires are respectively arranged corresponding to the scanning lines of odd rows; in the pixel areas of the even columns, n/2 vertical routing lines are respectively arranged corresponding to the scanning lines of the even rows.
3. The display panel according to claim 1, wherein each of the sub-common lines includes a first sub-common line segment and a third sub-common line segment parallel to the data line, a second sub-common line segment and a fourth sub-common line segment parallel to the scan line, and the first sub-common line segment, the second sub-common line segment, the third sub-common line segment and the fourth sub-common line segment are sequentially arranged end to end around the pixel region.
4. The display panel according to claim 1, wherein each of the sub common lines is connected to an adjacent other one of the sub common lines only by one of the vertical wirings; each of the sub-common lines is connected to an adjacent one of the sub-common lines only by one of the horizontal routing lines.
5. The display panel of claim 1, wherein one of the pixel regions corresponds to one of a red sub-pixel, a green sub-pixel, and a blue sub-pixel; the red sub-pixel, the green sub-pixel and the blue sub-pixel which are vertically arranged form a pixel.
6. The display panel according to claim 3, wherein the horizontal trace connects a third sub common line segment of one of the sub common lines with a first sub common line segment of another adjacent sub common line segment; the vertical routing connects a second sub-common line segment of one sub-common line with a fourth sub-common line segment of another adjacent sub-common line segment.
7. The display panel according to claim 6, wherein one end of the horizontal trace connects to a middle position of a third sub-common line segment of one of the sub-common lines, and the other end connects to a middle position of a first sub-common line segment of another adjacent sub-common line segment;
one end of the vertical routing is connected with one end of a second sub-common line segment of one sub-common line, and the other end of the vertical routing is connected with one end of a fourth sub-common line segment of another adjacent sub-common line segment.
8. The display panel according to claim 7, wherein the vertical trace is disposed at an end of the fourth sub-common line segment away from the corresponding active switch in the pixel region.
9. The display panel is characterized by comprising a display area and a non-display area, wherein the display area is internally provided with:
m data lines;
the n scanning lines, the m data lines and the n scanning lines are criss-cross to form a plurality of pixel regions; and
a common line receiving a common voltage signal;
the common line includes:
a plurality of sub common lines, one sub common line being disposed corresponding to each of the pixel regions;
each horizontal routing line is correspondingly crossed with the data line and connects two adjacent sub-common lines along the scanning line direction;
each vertical routing wire is correspondingly crossed with the scanning wire and is used for communicating two adjacent sub-common wires in the data wire direction, and the horizontal routing wires and the vertical routing wires are used for communicating the sub-common wires to form the common wire;
each sub-common line comprises a first sub-common line segment and a third sub-common line segment which are parallel to the data line, a second sub-common line segment and a fourth sub-common line segment which are parallel to the scanning line, and the first sub-common line segment, the second sub-common line segment, the third sub-common line segment and the fourth sub-common line segment are arranged around the pixel area in an end-to-end communication mode; the horizontal routing line is connected with a third sub-common line segment of one sub-common line and a first sub-common line segment of another adjacent sub-common line segment; the vertical routing is connected with a second sub-common line segment of one sub-common line and a fourth sub-common line segment of another adjacent sub-common line segment;
the number of the horizontal routing lines in the scanning line direction is m/2, and the number of the vertical routing lines in the data line direction is n/2; one horizontal routing line is arranged at every other data line, and one vertical routing line is arranged at every other scanning line;
the number of the horizontal routing lines in the direction of one data line is n/2, and the number of the vertical routing lines in the direction of one scanning line is m/2; the horizontal routing lines are arranged one by one at intervals of the scanning lines, and the vertical routing lines are arranged one by one at intervals of the data lines;
the display panel comprises a first metal layer, a second metal layer and a transparent electrode layer which are sequentially arranged from bottom to top; the scan line and the common line are formed at the first metal layer; the data line is formed on the second metal layer; the pixel electrode is formed on the transparent electrode layer;
the pixel electrode and the common line form a storage capacitor; the horizontal routing is formed on the first metal layer; the vertical routing lines are formed on the transparent electrode layer; the vertical routing line is connected with two adjacent sub-common lines through a via hole.
10. A display device comprising the display panel according to any one of claims 1 to 9 and a driving circuit for driving the display panel.
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| CN202110863839.8A CN113867060B (en) | 2020-11-24 | 2020-11-24 | Display panel and display device |
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| KR100989165B1 (en) * | 2003-06-02 | 2010-10-20 | 엘지디스플레이 주식회사 | In-Plane Switching Mode Liquid Crystal Display device and method for fabricating the same |
| US7800704B2 (en) * | 2006-11-13 | 2010-09-21 | Hannstar Display Corp. | Liquid crystal display comprising intersecting common lines |
| CN101825816A (en) * | 2009-03-06 | 2010-09-08 | 北京京东方光电科技有限公司 | TFT (Thin Film Transistor)-LCD (Liquid Crystal Display) array baseplate and manufacturing method thereof |
| CN102236222B (en) * | 2010-04-23 | 2013-07-10 | 北京京东方光电科技有限公司 | Array substrate and manufacturing method thereof and liquid crystal display |
| CN102135691B (en) * | 2010-09-17 | 2012-05-23 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and liquid crystal display |
| CN202159214U (en) * | 2010-10-14 | 2012-03-07 | 京东方科技集团股份有限公司 | Array substrate and liquid crystal display |
| KR101953141B1 (en) * | 2011-12-14 | 2019-03-04 | 엘지디스플레이 주식회사 | Array substrate for fringe field switching mode liquid crystal display device and method for fabricating the same |
| CN103176320B (en) * | 2011-12-22 | 2015-12-09 | 上海中航光电子有限公司 | Transversely arranged dot structure, liquid crystal indicator and preparation method thereof |
| JP2015090435A (en) * | 2013-11-06 | 2015-05-11 | 株式会社ジャパンディスプレイ | Liquid crystal display device |
| CN204028524U (en) * | 2014-06-23 | 2014-12-17 | 京东方科技集团股份有限公司 | Display base plate and display device |
| CN204065627U (en) * | 2014-08-05 | 2014-12-31 | 京东方科技集团股份有限公司 | A kind of substrate and display device |
| KR102371385B1 (en) * | 2015-11-26 | 2022-03-08 | 엘지디스플레이 주식회사 | Horizontal electric field type liquid crystal display device and method of fabricating the same |
| CN205645811U (en) * | 2016-05-31 | 2016-10-12 | 京东方科技集团股份有限公司 | Array baseplate and display device |
| CN105892175B (en) * | 2016-07-01 | 2019-11-19 | 上海中航光电子有限公司 | Display panel and display device |
| CN208795983U (en) * | 2018-10-31 | 2019-04-26 | 京东方科技集团股份有限公司 | Display base plate and display device |
| CN110085190B (en) * | 2019-06-10 | 2021-08-24 | 北海惠科光电技术有限公司 | Array substrate and display panel |
| CN113985666A (en) * | 2020-11-24 | 2022-01-28 | 惠科股份有限公司 | Display panel and display device |
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| CN113867060A (en) | 2021-12-31 |
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