CN113851559A - Preparation method of TOPCon battery - Google Patents
Preparation method of TOPCon battery Download PDFInfo
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- CN113851559A CN113851559A CN202111263015.3A CN202111263015A CN113851559A CN 113851559 A CN113851559 A CN 113851559A CN 202111263015 A CN202111263015 A CN 202111263015A CN 113851559 A CN113851559 A CN 113851559A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 43
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 43
- 239000010703 silicon Substances 0.000 claims abstract description 43
- 238000000034 method Methods 0.000 claims abstract description 38
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 31
- 238000000137 annealing Methods 0.000 claims abstract description 27
- 238000009792 diffusion process Methods 0.000 claims abstract description 26
- 230000008569 process Effects 0.000 claims abstract description 26
- 239000002019 doping agent Substances 0.000 claims abstract description 19
- 239000011248 coating agent Substances 0.000 claims abstract description 18
- 238000000576 coating method Methods 0.000 claims abstract description 18
- 238000000151 deposition Methods 0.000 claims abstract description 17
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims abstract description 15
- 239000007788 liquid Substances 0.000 claims abstract description 14
- 230000005641 tunneling Effects 0.000 claims abstract description 14
- 238000007747 plating Methods 0.000 claims abstract description 13
- 239000012535 impurity Substances 0.000 claims abstract description 8
- 238000001035 drying Methods 0.000 claims abstract description 7
- 239000003513 alkali Substances 0.000 claims description 13
- 238000010438 heat treatment Methods 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 238000005498 polishing Methods 0.000 claims description 7
- 238000005245 sintering Methods 0.000 claims description 6
- 238000001179 sorption measurement Methods 0.000 claims description 6
- 238000004804 winding Methods 0.000 claims description 6
- 238000007639 printing Methods 0.000 claims description 5
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 4
- 238000004528 spin coating Methods 0.000 claims description 4
- 238000004140 cleaning Methods 0.000 claims description 3
- 229910021478 group 5 element Inorganic materials 0.000 claims description 3
- 238000005507 spraying Methods 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 3
- 230000003213 activating effect Effects 0.000 abstract description 2
- 230000008021 deposition Effects 0.000 description 9
- 238000002425 crystallisation Methods 0.000 description 6
- 230000008025 crystallization Effects 0.000 description 6
- 229910052698 phosphorus Inorganic materials 0.000 description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000011065 in-situ storage Methods 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910052787 antimony Inorganic materials 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 3
- 229910052797 bismuth Inorganic materials 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 125000004437 phosphorous atom Chemical group 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 101001073212 Arabidopsis thaliana Peroxidase 33 Proteins 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 101001123325 Homo sapiens Peroxisome proliferator-activated receptor gamma coactivator 1-beta Proteins 0.000 description 2
- 102100028961 Peroxisome proliferator-activated receptor gamma coactivator 1-beta Human genes 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000005034 decoration Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000005406 washing Methods 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000010248 power generation Methods 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000002310 reflectometry Methods 0.000 description 1
- 238000005096 rolling process Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- -1 silver aluminum Chemical compound 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
- H01L31/1864—Annealing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
- H01L31/1872—Recrystallisation
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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Abstract
The invention discloses a preparation method of a TOPCon battery, which comprises the steps of preparing a tunneling oxide layer on the back surface of a silicon wafer by LPCVD (low pressure chemical vapor deposition), depositing intrinsic amorphous silicon, removing amorphous silicon on the front surface of the silicon wafer for plating, coating a liquid dopant on the back surface of the silicon wafer, drying, annealing the silicon wafer, crystallizing the amorphous silicon by annealing and activating impurities. The method can realize single-side diffusion without diffusion, is a process scheme for preparing an n + POLO structure, meets the high-yield requirement, optimizes a process window, avoids the risk of diffusion, can realize the removal of amorphous silicon before annealing for plating, simplifies the process steps, protects the front structure of the silicon wafer, improves the process controllability, and can solve the contradiction between the diffusion concentration and the tunneling layer effect.
Description
Technical Field
The invention relates to the field of photovoltaics, in particular to a preparation method of a TOPCon battery.
Background
In order to improve the proportion of photovoltaic power generation, cost reduction and efficiency improvement are two major lines of photovoltaic manufacturing, the current mainstream photovoltaic cell is a crystalline silicon solar cell, the TOPCon technology becomes one of the most potential novel high-efficiency cell technologies due to the extremely high compatibility of the process route and the traditional PERC cell production line and the obvious efficiency gain, and the related research is increased day by day.
With the development and introduction of TOPCon battery technology, the conversion efficiency of industrialized n-type TOPCon batteries exceeds 24%. The preparation of an n + POLO structure is the core technology of the battery, and the conventional preparation schemes in the industry at present have two types: firstly, thermal oxidation, LPCVD in-situ doping and high-temperature annealing; ② thermal oxygen + LPCVD intrinsic deposition + diffusion doping. The intrinsic poly Si deposition rate adopted in the scheme II is far higher than that of in-situ deposition, the LPCVD process time can be effectively reduced, the in-situ deposition can provide a more excellent doping curve and a larger tunneling oxygen layer process window, and compared with the traditional PERC cell, the complexity and the process time of the whole process are increased by the two schemes, so that the corresponding manufacturing cost is increased. How to continue to improve the conversion efficiency of the photovoltaic cell and reduce the process flow time so as to reduce the manufacturing cost is a common goal and direction in the photovoltaic industry.
The current technological process of the TOPCon battery mainly comprises the following steps:
the scheme is as follows: alkali texturing → boron diffusion → BSG removal on the back, alkali polishing on the back → tunneling oxygen + N + amorphous silicon deposition → front surface unwinding and plating → annealing → front and back surface plating → printed electrode sintering;
scheme II: alkali texturing → boron diffusion → back surface BSG removal, back surface alkali polishing → tunneling oxygen + intrinsic amorphous silicon deposition → phosphorus diffusion → front surface PSG removal → front surface wraparound plating → front and back surface plating → printed electrode, and sintering.
In the preparation aspect of the POLO structure, because the intrinsic deposition rate is far higher than that of in-situ deposition, the yield advantage is obvious by the same Poly Si thickness scheme, the first scheme adopts annealing for crystallization, the crystallization process is simple and controllable, the winding plating removal treatment can be carried out before crystallization without considering the winding expansion risk, the process steps are reduced, the front structure is free of etching risk (BSG protection) in the alkali polishing process, and the two schemes have defects in yield and process controllability respectively.
Disclosure of Invention
The invention aims to provide a preparation method of a TOPCon battery, which comprises the steps of preparing a tunneling oxide layer on the back surface of a silicon wafer by LPCVD (low pressure chemical vapor deposition), depositing intrinsic amorphous silicon, removing amorphous silicon on the front surface of the silicon wafer for coil plating, coating a liquid dopant on the back surface of the silicon wafer, drying, annealing the silicon wafer, crystallizing the amorphous silicon by annealing and activating impurities.
Preferably, the preparation method of the TOPCon battery comprises the following specific steps:
1) cleaning a silicon wafer and texturing;
2) b diffusion;
3) removing the BSG on the back;
4) carrying out alkali polishing on the back surface;
5) preparing a tunneling oxide layer and depositing intrinsic amorphous silicon by back LPCVD;
6) removing the amorphous silicon plating on the front surface;
7) coating liquid dopant on the back and drying;
8) annealing to crystallize the amorphous silicon and activate the impurities;
9) coating the film on the front surface and the back surface;
10) printing an electrode;
11) and (5) sintering.
Preferably, in the step 6), the front amorphous silicon spin coating is removed by chain type alkali polishing.
Preferably, in step 7), the front side of the silicon wafer is placed on the support plate, and then the back side of the silicon wafer is coated with the liquid dopant.
Preferably, the support plate has an adsorption function, and the silicon wafer is fixed on the support plate through negative pressure adsorption.
Preferably, the coating is spin coating, roll coating or spray coating.
Preferably, the liquid dopant contains a group v element.
Preferably, the group V element is selected from one or more of N, P, As, Sb and Bi.
Preferably, the carrier plate has a heating function, and the dopant is dried by heating the carrier plate.
Preferably, in step 8), the annealing is carried out in a tube furnace or a chain furnace.
Preferably, in the step 8), the annealing process conditions are as follows: high temperature of 700-900 ℃ for 3-20 min, normal pressure and nitrogen atmosphere.
The invention has the advantages and beneficial effects that: after depositing intrinsic amorphous silicon by LPCVD, adopting a scheme of single-side dopant coating and annealing to realize crystallization and single-side diffusion of a-Si, completing preparation of n + Poly Si and forming an n + POLO structure; the method can realize single-side diffusion without diffusion, is a process scheme for preparing an n + POLO structure, meets the high-yield requirement, optimizes a process window, avoids the risk of diffusion, can realize the removal of amorphous silicon before annealing for plating, simplifies the process steps, protects the front structure of the silicon wafer, improves the process controllability, and can solve the contradiction between the diffusion concentration and the tunneling layer effect.
The invention has the following characteristics:
1. in the prior art, after a-Si is deposited by LPCVD, an n + POLO structure is prepared by high-temperature phosphorus diffusion (gas phase diffusion), the thickness of a tunneling oxide layer is only 1-2 nm, the diffusion process needs to simultaneously meet the concentration requirement and the tunneling effect of the oxide layer, the process window is small, and the fault tolerance rate is poor. The invention can freely control the doping concentration by preparing the solution of the liquid dopant and control the degree of the inner diffusion of the crystallization and oxidation layer by the annealing process, thereby realizing the enhancement of the process controllability.
2. In the prior art, gas phase diffusion is adopted for phosphorus diffusion, the risk of diffusion cannot be avoided, only the front HF-removing PSG is carried out after diffusion, then the front-side plating-removing process is completed, the process complexity is increased, HF possibly causes etching of the BSG in a non-plating-removing area, and then the risk of damaging the front-side suede exists in the alkali-washing plating-removing process. According to the invention, the introduction of doping elements on the back side of the silicon wafer is carried out by coating a liquid dopant on a single side, the front side of the silicon wafer is adsorbed and shielded by the carrier plate, the risk of the dopant being coated on the front side of the silicon wafer in a winding manner is avoided, the carrier plate has a heating function, the coating and drying can be completed and the curing is completed in one step, then the crystallization and the doping of phosphorus atoms (the impurity propulsion and the activation) are carried out by adopting an annealing manner, the front side is protected by the barrier layer BSG with the thickness of 50-120 nm, and the diffusion speed of the phosphorus atoms in the barrier layer BSG is very low, so that the phosphorus atoms cannot penetrate through the barrier layer BSG to be wound and expanded to the front side within the annealing time of 3-20 min, the risk of the winding and expansion is avoided, the winding and the plating can be directly removed before the annealing, the process flow is greatly simplified, and the texture structure of the front side is protected.
Detailed Description
The following further describes embodiments of the present invention with reference to examples. The following examples are only for illustrating the technical solutions of the present invention more clearly, and the protection scope of the present invention is not limited thereby.
The invention provides a preparation method of a TOPCon battery, which comprises the following specific steps:
1) cleaning a silicon wafer and texturing;
2) b diffusion;
3) removing the BSG on the back;
4) carrying out alkali polishing on the back surface;
5) preparing a tunneling oxide layer and depositing intrinsic amorphous silicon by back LPCVD;
6) removing amorphous silicon on the front surface by chain type alkali throwing;
7) coating liquid dopant on the back and drying: the front surface of the silicon wafer can be flatly placed on a support plate with a negative pressure adsorption function and a heating function, the silicon wafer is fixed on the support plate through negative pressure adsorption, then a liquid dopant containing a V-group element (the V-group element is selected from one or more of N, P, As, Sb and Bi) is coated on the back surface of the silicon wafer, and then the dopant is dried through heating the support plate; the coating can adopt a spin coating, roll coating or spray coating mode;
8) annealing: annealing the silicon wafer in a tube furnace or a chain furnace to crystallize amorphous silicon and promote and activate impurities (one or more of N, P, As, Sb and Bi); the annealing process conditions are as follows: high temperature of 700-900 ℃ for 3-20 min, normal pressure and nitrogen atmosphere;
9) coating the film on the front surface and the back surface;
10) printing an electrode;
11) and (5) sintering.
The specific implementation case of the invention on the n-type TOPCon battery is as follows:
selecting an n-type monocrystalline silicon wafer with the resistivity range of 0.8-1.5 ohm.cm and the minority carrier lifetime of more than 2.5 ms, wherein the thickness is 170 mu m, and the size is 166 mm;
in KOH and H2O2Removing a damaged layer on the surface of the silicon wafer in the mixed solution, and then performing texturing in a KOH solution to form a pyramid textured surface on the surface of the silicon wafer, wherein the size of the pyramid textured surface is controlled to be 1-5 mu m;
after the texture surface is finished, preparing an emitter on the front side of the silicon wafer by adopting B diffusion, wherein the sheet resistance is 110-150 ohm.cm, the BSG thickness on the front side is 50-120 nm, and alkali polishing is carried out after BSG on the back side of the silicon wafer is removed, so that the reflectivity of the back side of the silicon wafer is more than 40%;
preparing a tunneling layer (1-2 nm) + a-Si (100-150 nm) on one side of an alkali polished surface (the back surface of a silicon wafer) in LPCVD (low pressure chemical vapor deposition), and removing amorphous silicon spiral coating (BSG as a barrier layer) on the front side by alkali washing after amorphous silicon deposition is completed;
then flatly placing the front side of the silicon wafer on a carrier plate, rolling and coating a liquid dopant containing P on the back side of the silicon wafer, and drying at 100-200 ℃ for 10-120 s;
then annealing in a tube furnace to crystallize the amorphous silicon and drive in and activate the impurity (P), wherein the annealing process conditions are as follows: high temperature of 700-900 ℃ for 3-20 min, normal pressure and nitrogen atmosphere;
depositing aluminum oxide with the thickness of 3-10 nm on the front side of the silicon wafer by using ALD, and preparing silicon nitride with the thickness of 75-80 nm by using PECVD; depositing silicon nitride with the thickness of 70-100 nm on the back of the silicon wafer to finish the preparation of a battery precursor;
and after the surface passivation is finished, metallizing the front side and the back side of the silicon chip, printing a silver paste electrode on the back side of the silicon chip and printing a silver aluminum paste electrode on the front side of the silicon chip in sequence in a screen printing mode, and sintering to finish the preparation of the battery.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the technical principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (10)
1. A preparation method of a TOPCon battery is characterized in that after a tunneling oxide layer is prepared on the back surface of a silicon wafer through LPCVD and intrinsic amorphous silicon is deposited, amorphous silicon on the front surface of the silicon wafer is removed, winding plating is conducted, then liquid dopant is coated on the back surface of the silicon wafer and dried, then annealing is conducted on the silicon wafer, and the amorphous silicon is crystallized through annealing and impurities are activated.
2. The method of claim 1, wherein the method comprises the steps of:
1) cleaning a silicon wafer and texturing;
2) b diffusion;
3) removing the BSG on the back;
4) carrying out alkali polishing on the back surface;
5) preparing a tunneling oxide layer and depositing intrinsic amorphous silicon by back LPCVD;
6) removing the amorphous silicon plating on the front surface;
7) coating liquid dopant on the back and drying;
8) annealing to crystallize the amorphous silicon and activate the impurities;
9) coating the film on the front surface and the back surface;
10) printing an electrode;
11) and (5) sintering.
3. A method of fabricating a TOPCon cell as recited in claim 2 wherein in step 6) the front side amorphous silicon spin coating is removed using a chain type alkaline polish.
4. A topocon cell manufacturing method as claimed in claim 3, wherein in step 7), the front side of the silicon wafer is first laid flat on the carrier plate, and then the back side of the silicon wafer is coated with the liquid dopant.
5. The method of claim 4, wherein the carrier plate has an adsorption function, and the silicon wafer is fixed on the carrier plate by negative pressure adsorption.
6. The method of claim 4, wherein the coating is spin, roll or spray coating.
7. The method of claim 4, wherein the liquid dopant comprises a group V element.
8. The method of claim 4, wherein the carrier plate has a heating function, and the dopant is dried by heating the carrier plate.
9. A method of manufacturing a TOPCon cell according to claim 2, characterized in that in step 8) the annealing is performed in a tube furnace or a chain furnace.
10. The method for preparing a TOPCon battery as claimed in claim 2, wherein the annealing in step 8) is performed under the following process conditions: high temperature of 700-900 ℃ for 3-20 min, normal pressure and nitrogen atmosphere.
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Cited By (5)
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| CN115020534A (en) * | 2022-04-30 | 2022-09-06 | 常州时创能源股份有限公司 | Preparation method of back-side graphical N region of IBC battery |
| CN115020535A (en) * | 2022-04-30 | 2022-09-06 | 常州时创能源股份有限公司 | Preparation method of back double-POLO structure of IBC battery |
| CN115101627A (en) * | 2022-07-08 | 2022-09-23 | 三一集团有限公司 | Double-sided passivation contact solar cell and preparation method thereof |
| CN116613245A (en) * | 2023-06-09 | 2023-08-18 | 无锡松煜科技有限公司 | Method for improving LPCVD (low pressure chemical vapor deposition) through rate of TOPCon battery |
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