CN113851534A

CN113851534A - Semiconductor device with a plurality of semiconductor chips

Info

Publication number: CN113851534A
Application number: CN202010596578.3A
Authority: CN
Inventors: 钟怡青; 张睿钧; 曾富群; 何玉萍
Original assignee: Vanguard International Semiconductor Corp
Current assignee: Vanguard International Semiconductor Corp; Vanguard International Semiconductor America
Priority date: 2020-06-28
Filing date: 2020-06-28
Publication date: 2021-12-28

Abstract

An embodiment of the present invention provides a semiconductor device, including: a substrate; the first trap and the second trap are arranged in the substrate and are adjacent to each other; the isolation structure is arranged on the first trap; the first field plate is arranged on the isolation structure; the grid structure crosses the first trap and the second trap, an opening is formed between the first field plate and the grid structure, and the opening exposes one edge of the isolation structure close to the grid structure; a drain structure disposed in the first well; and the source electrode structure is arranged in the second trap and reduces or prevents hot carrier effect.

Description

Semiconductor device with a plurality of semiconductor chips

Technical Field

Embodiments of the present invention relate to semiconductor devices, and more particularly, to a semiconductor device including a field plate.

Background

Semiconductor devices can be applied in various fields, for example: display driver ICs, power management ICs (or high power management ICs), discrete power devices, sensing devices, fingerprint recognition ICs, and memory, among others. Semiconductor devices are generally manufactured in the following manner: layers of insulating or dielectric, conductive, and semiconductor materials are sequentially deposited on a semiconductor substrate, and the various material layers are patterned using photolithographic techniques to form circuit elements and components thereon.

In order to improve the breakdown voltage of a semiconductor device, in addition to optimizing the well and drift region between the source and drain, the gate is typically extended (e.g., over the drift region or isolation structure) to act as a field plate (field plate). While conventional gate field plates have been generally desirable, they have not been satisfactory in every respect.

Disclosure of Invention

An embodiment of the present invention provides a semiconductor device, including: a substrate; the first trap and the second trap are arranged in the substrate and are adjacent to each other; the isolation structure is arranged on the first trap; the first field plate is arranged on the isolation structure; the grid structure crosses the first trap and the second trap, an opening is formed between the first field plate and the grid structure, and the opening exposes one edge of the isolation structure close to the grid structure; a drain structure disposed in the first well; and a source structure disposed in the second well.

Drawings

Fig. 1-8 are cross-sectional views illustrating a semiconductor device according to some embodiments of the present invention.

Reference numerals:

100,200,300,400,500,600,700,800 semiconductor device

110 substrate

112 first well

114 second well

116 isolation structure

116E edge

118,126,128,130,132 field plate

118a first part

118b second part

118c third part

120: gate structure

120a gate dielectric layer

120b gate electrode

122 drain structure

122a,122b,124a,124b,134,136,138 doped regions

124 source structure

140 interlayer dielectric layer

142,142a,142b drain contact

144,144a,144b,144c field plate contacts

146 source contact

D is distance

L is length

OP is an opening

Detailed Description

The following disclosure provides many embodiments, or examples, for implementing different elements of the provided subject matter. Specific examples of components and arrangements thereof are described below to simplify the description of the embodiments of the invention. These are, of course, merely examples and are not intended to limit the embodiments of the invention. For example, references in the description to a first element being formed on a second element may include embodiments in which the first and second elements are in direct contact, and may also include embodiments in which additional elements are formed between the first and second elements such that they are not in direct contact. In addition, embodiments of the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, in some embodiments of the present invention, terms concerning bonding, connecting, such as "connecting," "interconnecting," and the like, may refer to two structures being in direct contact or, alternatively, may refer to two structures not being in direct contact, unless otherwise specified, with other structures disposed between the two structures. And the terms coupled and connected should also be construed to include both structures being movable or both structures being fixed.

Also, spatially relative terms, such as "below" … …, "below," "lower," "above," "higher," and the like, may be used herein to facilitate describing the relationship of one component(s) or feature(s) to another component(s) or feature(s) in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. When the device is turned to a different orientation (rotated 90 degrees or otherwise), the spatially relative adjectives used herein will also be interpreted in terms of the turned orientation.

As used herein, the terms "about", "approximately" and "substantially" generally mean within 20%, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value. In the case where a given value is approximate, that is, in the case where "about", "about" and "substantial" are not specifically stated, the given value may still imply the meaning of "about", "about" and "substantial".

Some embodiments of the invention are described below in which additional steps may be provided before, during, and/or after various stages described in the embodiments. Some of the stages may be replaced or eliminated in different embodiments. Additional components may be added to the semiconductor device structure. Some of the described components may be replaced or eliminated in different embodiments. Although some embodiments discussed are performed in a particular order of steps, these steps may be performed in another logical order.

The following detailed description of the embodiments of the invention can be best understood when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily expanded or reduced to clearly illustrate the features of the embodiments of the present invention.

Impact ionization point (ii point) of a semiconductor device generally occurs in an isolation structure (such as an STI (shallow trench isolation) structure or a local oxidation of silicon (LOCOS) structure) beside a source structure, and an electric field in the semiconductor device causes electron-hole pairs (HCI) generated by the impact ionization point to be injected into an adjacent component, thereby generating Hot Carrier Injection (HCI) to affect the reliability of the semiconductor device.

Embodiments of the present invention provide a semiconductor device, in which a field plate on an isolation structure does not extend to an edge of an isolation region, and a gate structure does not extend to the isolation region. In other words, an opening exposing the edge of the isolation structure is formed between the field plate on the isolation structure and the gate structure to reduce the electric field strength impacting the free point near the isolation structure, thereby further reducing or preventing the hot carrier effect.

For convenience of illustration, embodiments of the present invention will be described below in terms of devices having a Laterally Diffused Metal Oxide Semiconductor (LDMOS) with an insulator-on-insulator Semiconductor, and examples of applying embodiments of the present invention to other devices, such as a Lateral Insulated Gate Bipolar Transistor (LIGBT), will be described, but embodiments of the present invention are not limited thereto. Some embodiments of the invention may also be applied to other types of Metal Oxide Semiconductor devices, such as Vertical Diffused Metal Oxide Semiconductor (VDMOS) devices, enhanced-Diffused Metal Oxide Semiconductor (EDMOS) devices, or the like. In addition, the present invention is also applicable to other types of semiconductor devices, such as diodes (diode), Insulated Gate Bipolar Transistors (IGBT), Bipolar Junction Transistors (BJT), or the like.

Fig. 1 is a schematic cross-sectional view of a semiconductor device 100 according to some embodiments of the present invention. The semiconductor structure 100 includes: substrate 110, first well 112, second well 114, isolation structure 116, field plate 118, gate structure 120, opening OP, drain structure 122, source structure 124, field plate 126, interlayer dielectric 140, drain contact 142, field plate contact 144, source contact 146. The substrate 110 may be a doped (e.g., doped with p-type or n-type dopants) or undoped semiconductor substrate. For example, the substrate 110 may include: elemental semiconductors including silicon or germanium; compound semiconductors including gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and/or indium antimonide (InSb); the alloy semiconductor comprises silicon-germanium alloy, phosphorus-arsenic-gallium alloy, arsenic-aluminum-indium alloy, arsenic-aluminum-gallium alloy, arsenic-indium-gallium alloy, phosphorus-indium-gallium alloy and/or phosphorus-arsenic-indium-gallium alloy, or a combination of the materials.

In some embodiments, the substrate 110 may also be a semiconductor on insulator (soi) substrate, such as: silicon on insulator (soi) or Silicon Germanium On Insulator (SGOI). In other embodiments, substrate 110 may be a ceramic substrate, such as an aluminum nitride (AlN) substrate, a silicon carbide (SiC) substrate, an aluminum oxide (Al)₂O₃) A substrate (otherwise known as a sapphire substrate), or other similar substrate. In other embodiments, the substrate 110 may comprise a ceramic substrate and a pair of barrier layers respectively disposed on the upper and lower surfaces of the ceramic substrate, wherein the ceramic substrate may comprise a ceramic material, and the ceramic material comprises a metal inorganic material. For example, the ceramic substrate may comprise: silicon carbide, aluminum nitride, sapphire substrates, or other suitable materials. The sapphire substrate may be alumina.

The first well 112 is disposed in the substrate 110. The formation method of the first well 112 includes, but is not limited to: a patterned mask layer (not shown) is formed on the substrate 110 using a photolithography process and an etching process, the patterned mask layer exposing a region of the substrate 110 where the first well 112 is to be formed and covering other regions of the substrate 110, dopants are then injected into the region where the first well 112 is to be formed, and the patterned mask layer is removed. The patterned mask layer may be a hard mask or a photoresist. In an embodiment intended to form the N-type first well 112, the dopants may be N-type dopants, such as: phosphorus, arsenic, or antimony ions. In embodiments where it is desired to form the P-type first well 112, the dopant may be a P-type dopant, such as boron, indium, or BF₂ ⁺Ions.

A second well 114 is disposed in the substrate 110 and abuts the first well 112. The second well 114 is formed in a similar manner to the first well 112 described above. In an embodiment of the present invention, the second well 114 and the first well 112 have opposite conductivity types. For example, in embodiments where the first well 112 is N-type, the dopant used to implant the second well 114 is a P-type dopant (e.g., boron, indium, or BF)₂ ⁺Ions) to form P-typeA second well 114; in embodiments where the first well 112 is P-type, the dopants used to implant the second well 114 are N-type dopants (e.g., phosphorus, arsenic, or antimony ions) to form the N-type second well 114.

In some embodiments, the first well 112 has a first conductivity type and the second well 114 has a second conductivity type opposite the first conductivity type. Alternatively, the first well 106 has the second conductivity type and the second well 108 has the first conductivity type. Specifically, in some embodiments, the first well 106 may be a p-type well and the second well 108 may be an n-type well as an n-type metal-oxide-semiconductor field effect transistor (NMOS). In some embodiments, the first well 112 may be an n-type well and the second well 114 may be a p-type well to function as a p-type metal-oxide-semiconductor field effect transistor (PMOS). In some embodiments, the doping concentration of the first well 112 is between about 1 × 10¹⁰cm^-3To 1X 10²⁰cm^-3. The doping concentration of the second well 114 is between about 1 × 10¹⁰cm^-3To 1X 10²⁰cm^-3。

An isolation structure 116 is disposed on the first well 112. The isolation structure 116 may include: shallow Trench Isolation (STI), local oxidation of silicon (LOCOS), or a combination of the foregoing. In some embodiments, the process of forming the shallow trench isolation may include: forming and patterning a mask layer (not shown) on the first well 112, etching a trench in the first well 112 using the patterned mask layer as an etching mask, performing a deposition process to fill the trench with an isolation material, performing a planarization process, such as a Chemical Mechanical Polishing (CMP) process or a mechanical polishing (mechanical grinding process), to remove an excess portion of the isolation material, and removing the patterned mask layer. The aforementioned isolation material may include an oxide, nitride, or oxynitride, such as: silicon oxide, carbon-doped silicon oxide (SiO)_xC) Silicon oxynitride (SiON), silicon carbon oxynitride (SiOCN), silicon carbide (SiC), silicon carbon nitride (SiCN), silicon nitride (Si)_xN_yOr SiN), silicon-oxycarbide (SiCO) silicon oxide, silicon-oxycarbide (silicon oxycarbide), silicon-oxynitride (silicon oxynitride), silicon-carbide-nitride (silicon carbide), silicon-oxynitride (silicon-oxide-carbide), silicon-carbide-nitride (silicon-carbide-nitride)) Any other suitable material, or combination of the foregoing. In some embodiments, the local oxidation process of silicon to form the isolation structure 116 may include: depositing a mask layer (e.g., a silicon nitride layer) on the first well 112, patterning the mask layer using a photolithography process and an etching process to expose a portion of the first well 112, thermally oxidizing the exposed portion of the first well 112 to form a silicon oxide layer, and removing the patterned mask layer.

A field plate 118 is disposed on the isolation structure 116. In some embodiments, the Field plate 118 has the effect of reducing the surface Field (RESURF) and can reduce the impact ionization point of the isolation structure 116 and the electric Field strength in the vicinity thereof. The material of the field plate 118 may include conductive materials such as: metals, metal nitrides or doped semiconductors, for example, the metals may be: au, Ni, Pt, Pd, Ir, Ti, Cr, W, Al, Cu, similar materials, combinations of the foregoing, or multilayer structures of the foregoing; the metal nitride may be: MoN, WN, TiN, TaN, or similar material; the doped semiconductor is: doped polysilicon (polycrystalline silicon) or doped poly-germanium. The aforementioned conductive materials may be formed by a deposition process, such as: chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or Physical Vapor Deposition (PVD), such as sputtering or evaporation, and then patterning the conductive material to form the field plate 118.

Referring to fig. 1, a gate structure 120 crosses over the first well 112 and the second well 114, and an opening OP is formed between the field plate 118 and the gate structure 120, and exposes an edge 116E of the isolation structure 116 near the gate structure 120. In some embodiments, the gate structure 120 may include a gate dielectric layer 120a on the first well 112 and/or the second well 114 and a gate electrode 120b on the gate dielectric layer 120 a. The vertical electric field in known semiconductor devices causes electron-hole pairs (electron-hole pairs) generated by impact ionization points present at the edges of the isolation structures to gain enough kinetic energy to be injected into overlying features (e.g., gate structures) against potential barriers (potential barriers), resulting in severe hot carrier injection, resulting in reduced reliability or lifetime of the device. In the embodiment of the invention, the edge 116E of the isolation structure 116 close to the gate structure 120 is exposed through the opening OP between the field plate 118 and the gate structure 120, so that damage to the semiconductor structure caused by hot carrier injection (hot carrier injection) can be effectively reduced, and the reliability of the semiconductor structure can be improved.

In some embodiments, the method of forming the gate structure 120 includes: a dielectric material layer (for forming the gate dielectric layer 120a) and a conductive material layer (for forming the gate electrode 120b) thereon are blanket deposited sequentially, and then the dielectric material layer and the conductive material layer are patterned by photolithography and etching processes, respectively, to form the gate dielectric layer 120a and the gate electrode 120b crossing the first well 112 and the second well 114. In some embodiments, as shown in fig. 1, the length L of the gate structure 120 is greater than the distance D between the source structure 124 and the first well 112 in the direction from the source structure 124 to the isolation structure 116, so as to ensure that the device can operate normally, and if the length L is less than the distance D, the channel may not open. The gate dielectric layer 120a may comprise one or more single or multiple layers of dielectric materials, such as: silicon oxide, silicon nitride, silicon oxynitride, or combinations of the foregoing. In other embodiments, the gate dielectric layer 120a may include: metal oxides, metal nitrides, metal silicides, metal aluminates, zirconium silicates, zirconium aluminates, or combinations of the foregoing, but are not limited thereto. For example, the gate dielectric layer 120a may be formed by spin coating (spin coating), chemical vapor deposition (cvd), atomic layer deposition (ald), high density plasma cvd (hdp cvd), other suitable methods, or a combination thereof. The gate electrode 120b is formed of the same or similar materials and methods as the field plate 118, and may be formed by the same deposition and photolithography processes, or by different processes.

In an embodiment where the gate electrode 120b and the field plate 118 are formed by the same process, a conductive material may be formed by a deposition process, such as chemical vapor deposition, atomic layer deposition, or physical vapor deposition (e.g., sputtering or evaporation), and then patterned to form the field plate 118 on the isolation structure 116, the gate electrode 120b crossing the first well 112 and the second well 114, and an opening OP exposing an edge 116E of the isolation structure 116 near the gate electrode 120b, as shown in fig. 1. In some embodiments, the opening OP exposes both the edge 116E of the isolation structure 116 and a portion of the first well 112, further reducing the possibility of electron-hole injection into the overlying gate structure 120 or the field plate 118 under the influence of the electric field, so as to ensure improved hot carrier effect.

A drain structure 122 is disposed in the first well 112 and a source structure 124 is disposed in the second well 114. The drain structure 122 includes a doped region having the same conductivity type as the first well 112. The source structure 124 includes a doped region 124a and a doped region 124b that are adjacent to each other and have opposite conductivity types. The doped regions of the drain structure 122 and the source structure 124 are formed in a manner similar to the doping of the first well 112 described above. In some embodiments, the semiconductor device 100 further includes a doped region 134 disposed below the source structure 124, wherein the doping concentration of the doped region 124b is greater than the doping concentration of the doped region 134. In one embodiment, the doping concentration of the source structure 124 and the doped

regions

124a,124b is between about 10¹³cm^-3To 10²¹cm^-3The doping concentration of the doped region 134 is between 10¹²cm^-3To 10¹³cm^-3The doped region 134 can reduce the on-resistance (R)_on)。

With continued reference to fig. 1, an interlayer dielectric layer 140 is located on the substrate 110. The interlevel dielectric layer 140 may comprise one or more single or multiple layers of dielectric materials, such as: silicon oxide, silicon nitride, silicon oxynitride, Tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric material, and/or other suitable dielectric materials. The low-k dielectric material may include (but is not limited to): fluorinated Silica Glass (FSG), Hydrogen Silsesquioxane (HSQ), carbon doped silicon oxide, amorphous carbon fluoride (fluorinated carbon), parylene, benzocyclobutene (BCB), or polyimide (polyimide). For example, the interlayer dielectric layer 140 may be formed using spin-on coating, chemical vapor deposition, atomic layer deposition, high density plasma chemical vapor deposition, other suitable methods, or a combination thereof.

As shown in fig. 1, the drain contact 142, the field plate contact 144, and the source contact 146 pass through the interlayer dielectric layer 140 and are electrically connected to the drain structure 122, the field plate 118, and the source structure 124, respectively. The contact can be formed in the same process, and the forming method comprises the following steps: a patterning process is performed on the ild 140 to form an opening in the ild 140, and then a planarization process (e.g., chemical mechanical polishing) or an etch back process is performed to fill the opening with a conductive material to remove excess material outside the opening. The conductive material and method of formation of the contacts may be the same as or similar to the conductive material of the field plate 118 described above. In some embodiments, the material of the drain contact 142, the field plate contact 144, and the source contact 146 can be formed of polysilicon, metal, or other suitable conductive material. In some embodiments, the material of the drain contact 142, the field plate contact 144, and the source contact 146 may include copper (Cu), aluminum (Al), molybdenum (Mo), tungsten (W), gold (Au), chromium (Cr), nickel (Ni), platinum (Pt), titanium (Ti), iridium (Ir), rhodium (Rh), copper alloys, aluminum alloys, molybdenum alloys, tungsten alloys, gold alloys, chromium alloys, nickel alloys, platinum alloys, titanium alloys, iridium alloys, rhodium alloys, other suitable materials having conductivity, or combinations of the foregoing.

Referring to fig. 1, a field plate 126 is disposed over the field plate 118 and is electrically connected to the field plate 118 and the source structure 124 by a field plate contact 144 and a source contact 146, respectively. The field plate 126 crosses the isolation structure 116 and the gate structure 120 exposed by the opening OP, so that the surface electric field is reduced, the electric field intensity below the opening OP (for example, the impact ionization point of the isolation structure 116 below the opening OP and the electric field intensity near the impact ionization point) and the electric field intensity below the gate structure 120 are reduced, and the electron-hole pairs generated by the impact ionization point of the isolation structure 116 due to the electric field can be slowed down or prevented from being injected into the gate structure 120 or the field plate 118, so as to improve hot carrier injection, and the reliability or the service life of the device can be improved without affecting the breakdown voltage of the device. In some embodiments of the present invention, source structure 124 may be connected to ground.

One of the objectives of the present invention is to solve the problem of the reliability or lifetime degradation of the device caused by the vertical electric field and the lateral electric field. For example, in addition to hot carrier injection, the vertical electric field causes electron-hole pairs generated by impact ionization at the edge 116E of the isolation structure near the gate structure 120 to generate sufficient kinetic energy to overcome potential energy barrier and inject into adjacent components (e.g., the source structure), which results in severe hot carrier injection, which may damage or degrade the source structure or the drain structure, resulting in reduced reliability or lifetime of the device. In the embodiment of the invention, the field plate 126 above the field plate 118 crosses over the isolation structure 116 and the gate structure 120 exposed by the opening OP, and the field plate 118 and the source structure 124 are electrically connected, so that the field plate 118, the field plate 126 and the source structure 124 have the same potential, and besides the effect of reducing the surface electric field, the impact ionization point of the isolation structure 116 below the opening OP and the lateral electric field intensity nearby the impact ionization point can be reduced, and the lateral electric field intensity below the gate structure 120 can be reduced or prevented, so that the electron-hole pairs generated by the impact ionization point of the isolation structure 116 due to the lateral electric field can be injected into the source structure 124, thereby improving the hot carrier injection, and improving the reliability or the service life of the device without affecting the breakdown voltage of the device.

Fig. 2 is a cross-sectional schematic view of a semiconductor device 200 according to some embodiments of the present invention, the semiconductor device 200 being similar to the semiconductor device 100 of fig. 1 except that the field plate 118 of the semiconductor device 200 has a first portion 118a and a second portion 118b that are separated from each other. The first portion 118a and the second portion 118b of the field plate 118 are electrically connected to the field plate 126 through

field plate contacts

144a and 144b, respectively, and a portion of the isolation structure 116 is exposed between the first portion 118a and the second portion 118 b. In some embodiments, the field plate 118 having the first portion 118a and the second portion 118b separated from each other may be formed by a patterning process. For the sake of simplicity, the same reference numerals are used for the same components in fig. 2 as those in fig. 1 and the description thereof is omitted. The material and formation method of the

field plate contacts

144a and 144b are the same as or similar to those of the field plate contact 144 described above, and a description thereof will not be repeated.

The semiconductor structure 200 and the semiconductor structure 100 also include an opening OP between the field plate 118 and the gate structure 120, so that neither the field plate 118 nor the gate structure 120 is located directly above the edge 116E of the isolation structure 116, thereby alleviating or preventing the vertical electric field from injecting electron-hole pairs generated by the impact of the stray point into the upper component, thereby improving hot carrier injection. The semiconductor structure 200 also includes a field plate 126 disposed above the field plate 118, and in addition to reducing the surface electric field, the field plate 126 can further reduce the electric field intensity between the isolation structure 116 and the source structure 124 (e.g., the electric field intensity under the opening OP and under the gate structure 120), and slow or prevent the injection of the electron-hole pairs generated by the impact on the free spot into the gate structure 120, the field plate 118, or the source structure 124, so as to improve the hot carrier injection, and improve the reliability or lifetime of the device.

In some embodiments, the separated first portion 118a and second portion 118b of the field plate 118 of the semiconductor device 200 can improve the electrical uniformity of the element. For example, depending on the device design or requirement, the first portion 118a and the second portion 118b of the field plate 118 may be separated from each other on the isolation structure 116 to improve the higher local electric field and thus the electrical uniformity of the device. If the electric field distribution below the isolation structure 116 is not uniform, the first portion 118a and the second portion 118b of the field plate 118, which are separated from each other, can be disposed on the corresponding isolation structure 116 directly above, which can also improve the higher local electric field and further improve the electrical uniformity of the device. The embodiments of the present invention do not limit the number of the plurality of portions of the field plate 118 separated from each other, and the first portion 118a and the second portion 118b in fig. 2 are only examples, and those skilled in the art can adjust the number or the pitch of the separated portions according to actual situations. If the single field plate still has too high electric field, the separated field plate can be used to improve the local electric field, thereby improving the electrical uniformity of the device and improving the reliability of the device.

Fig. 3 is a cross-sectional schematic view of a semiconductor device 300, the semiconductor device 300 being similar to the semiconductor device 100 of fig. 1 except that a field plate 128 disposed over the field plate 118 is electrically connected to the field plate 118 and the drain structure 122 via a field plate contact 144 and a drain contact 142, respectively, in accordance with some embodiments of the present invention. For the sake of simplicity, the same reference numerals are used for the same components in fig. 3 as those in fig. 1 and the description thereof is omitted.

Fig. 4 is a cross-sectional schematic view of a semiconductor device 400 according to some embodiments of the present invention, the semiconductor device 400 being similar to the semiconductor device 300 of fig. 3 except that the field plate 118 of the semiconductor device 400 has a first portion 118a and a second portion 118b that are separated from each other. The first portion 118a and the second portion 118b of the field plate 118 are electrically connected to the field plate 128 through

field plate contacts

144a and 144b, respectively, and a portion of the isolation structure 116 is exposed between the first portion 118a and the second portion 118 b. In some embodiments, the field plate 118 having the first portion 118a and the second portion 118b separated from each other may be formed by a patterning process. For the sake of simplicity, the same reference numerals are used for the same components in fig. 4 as those in fig. 3 and the description thereof is omitted. The number of the plurality of separated portions of the field plate 118 is not limited by the embodiments of the present invention, and can be adjusted by those skilled in the art according to the actual situation.

Fig. 5 is a schematic cross-sectional view of a semiconductor device 500 according to some embodiments of the present invention. The field plate 118 of the semiconductor device 500 has a first portion 118a and a second portion 118b that are separated from each other, and a portion of the isolation structure 116 is exposed between the first portion 118a and the second portion 118 b. For the sake of simplicity, the same or similar components in fig. 5 as those in the previous drawings are given the same reference numerals and their descriptions are omitted. As shown in fig. 5, the field plate 130 is disposed over the field plate 118 and is electrically connected to the first portion 118a of the field plate 118 and the drain structure 122, respectively, by a field plate contact 144a and a drain contact 142. The field plate 132 is disposed over the field plate 118 and is electrically connected to the second portion 118b of the field plate 118 and the source structure 124, respectively, by a field plate contact 144b and a source contact 146. In some embodiments, as shown in fig. 5, the length L of the gate structure 120 is greater than the distance D between the source structure 124 and the first well 112 in the direction from the source structure 124 to the isolation structure 116, so as to ensure that the device can operate normally, and if the length L is less than the distance D, the channel may not be opened, so that the device cannot operate.

In some embodiments as shown in fig. 5, the field plate 130 spans the region between the drain structure 122 and the isolation structure 116, so as to reduce the electric field between the drain structure 122 and the isolation structure 116, and slow or prevent the electric field from causing the electron-hole pairs generated by the impact of the isolation structure 116 on the free spot to be injected into the drain structure 122, thereby improving hot carrier injection; the field plate 132, which spans the isolation structure 116 and the gate structure 120 exposed by the opening OP, can reduce the electric field intensity below the opening OP (e.g., reduce the electric field intensity at and near the impact ionization point of the isolation structure 116 below the opening OP) and the electric field intensity below the gate structure 120, and can reduce or prevent the electron-hole pairs generated by the impact ionization point of the isolation structure 116 from being injected into the gate structure 120, the field plate 118, or the source structure 124 by the electric field, so as to improve hot carrier injection. In addition, as mentioned above, the first portion 118a and the second portion 118b of the field plate 118, which are separated from each other, can improve the electrical uniformity of the device. Such embodiments can improve the impact of hot carrier injection on the drain structure 122, the gate structure 120, the field plate 118, and the source structure 124, and improve the reliability, lifetime, and overall performance of the device. In some embodiments, the drain structure 122 or the source structure 124 may be electrically connected to ground.

Those skilled in the art can adjust the configuration of the field plate 118 according to the actual requirement, such as the embodiment shown in fig. 6, which illustrates a cross-sectional view of a semiconductor device 600, the semiconductor device 600 is similar to the semiconductor device 500 of fig. 5, except that the field plate 118 of the semiconductor device 600 is composed of three parts separated from each other, which includes: a first portion 118a, a second portion 118b, and a third portion 118c, and a portion of the isolation structure 116 is exposed between the three separate portions. For the sake of simplicity, the same or similar components in fig. 5 as those in the previous drawings are given the same reference numerals and their descriptions are omitted. The field plate 130 of the semiconductor device 600 is electrically connected to the first portion 118a and the drain structure 122 of the field plate 118 by the field plate contact 144a and the drain contact 142, respectively, and the field plate 132 is electrically connected to the second portion 118b, the third portion 118c, and the source structure 124 by the field plate contact 144b, the field plate contact 144c, and the source contact 146, respectively. In some embodiments, the field plate 118 may be formed to have a first portion 118a, a second portion 118b, and a third portion 118c that are separated from each other by a patterning process. As described above, this embodiment can simultaneously improve the impact of hot carrier injection on the drain structure 122, the gate structure 120, the field plate 118, and the source structure 124, prevent component damage or degradation, and improve the overall performance of the device, and can adjust the pitch or number of the separated portions of the field plate 118 by the patterning process according to the design and functional requirements of the device, thereby providing process flexibility.

Fig. 7 is a cross-sectional view of a semiconductor device 700 according to some embodiments of the present invention, the semiconductor device 700 being similar to the semiconductor device 400 of fig. 4 except that the drain structure 122 of the semiconductor device 700 includes doped

regions

122a and 122b of opposite conductivity types, and the semiconductor device 700 further includes doped

regions

136 and 138. For the sake of simplicity, the same reference numerals are used for the same components in fig. 7 as those in fig. 4 and the description thereof is omitted. The doped region 136 of the semiconductor device 700 is located under the isolation region 116, the doped region 138 is located under the doped region 136 and forms a junction therewith, and the doped region 136 and the doped region 138 have opposite conductivity types. In some embodiments,

doped regions

136 and 138 are formed using ion implantation. In such embodiments, the doped region 136 or the doped region 138 includes at least two sub-implanted regions (sub-implanted regions) with different implantation concentrations. In some embodiments, the sub-implant region having a higher implant concentration is adjacent to the junction and the sub-implant region having a lower implant concentration is remote from the junction. In this embodiment, in addition to improving hot carrier injection, the doped

regions

136 and 138 of the semiconductor device 700 can also be used to reduce the surface electric field of the isolation region 116 and to equalize the surface electric field of the isolation region 116. The widths of the doped

regions

136 and 138 in fig. 7 are only examples, for example, the widths of the doped

regions

136 and 138 may be different from the width of the bottom of the isolation region 112, or in another example, the width of the doped region 136 may be different from the width of the doped region 138.

Fig. 8 is a cross-sectional schematic view of a semiconductor device 800, the semiconductor device 800 being similar to the semiconductor device 300 of fig. 3, except that the drain structure 122 of the semiconductor device 800 includes a doped region 122a and a doped region 122b that are separated from each other and have opposite conductivity types, the doped

regions

122a and 122b being electrically connected to the field plate 128 through

drain contacts

142a and 142b, respectively, according to some embodiments of the present invention. The material and formation method of the

drain contacts

142a and 142b are the same as or similar to those of the drain contact 142 described above, and a description thereof will not be repeated. For the sake of simplicity, the same reference numerals are used for the same components in fig. 8 as those in fig. 3 and the description thereof is omitted. In addition to improving hot carrier injection, the doped region 122a and the doped region 122b of the semiconductor device 800 are separated from each other, so that the doped region 122b can enter the drain contact 142b to be enlarged, thereby increasing the voltage difference between the doped region 122b and the first well 112, and enabling the semiconductor device 800 to be triggered quickly. In addition, by changing the distance between the

doped regions

122a and 122b, the trigger voltage of the semiconductor device 800 can be adjusted. In other embodiments, the semiconductor device 800 may further include an optional doped region between the isolation region 116 and the doped region 122b and not connected to the

drain contact

142a or 142b, which may improve the breakdown voltage of the semiconductor device 800.

The semiconductor device provided by the embodiment of the invention has the opening exposing part of the isolation structure between the field plate on the isolation structure and the gate structure, and can slow down or prevent an electric field from leading electron-hole pairs generated by impact free points of the isolation structure to be injected into the upper gate structure or the field plate so as to improve hot carrier injection, and can improve the reliability or the service life of an element under the condition of not influencing the breakdown voltage of the element. In some embodiments, the field plate on the isolation structure comprises a plurality of portions separated from each other, which can improve the electrical uniformity of the device. In addition, the embodiment of the invention further reduces the electric field below the opening, below the gate structure, between the isolation structure and the source structure, or between the isolation structure and the drain structure by arranging the additional field plate to be electrically connected with at least one of the source electrode structure or the drain electrode structure and the field plate on the isolation structure, and further slows down or prevents the electric field from injecting electron-hole pairs generated by impact free points of the isolation structure into adjacent components, so as to improve hot carrier injection and avoid component damage or deterioration.

The foregoing outlines features of various embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art to which the invention pertains will also appreciate that such equivalent constructions do not depart from the spirit and scope of the invention, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the invention.

Claims

1. A semiconductor device, comprising:

a substrate;

a first well and a second well disposed in the substrate and adjacent to each other;

an isolation structure disposed on the first well;

a first field plate disposed on the isolation structure;

a gate structure crossing the first well and the second well, and having an opening between the first field plate and the gate structure, the opening exposing an edge of the isolation structure near the gate structure;

a drain structure disposed in the first well; and

a source structure disposed in the second well.

2. The semiconductor device of claim 1, wherein the first field plate has a first portion and a second portion separated from each other, and a portion of the isolation structure is exposed between the first portion and the second portion.

3. The semiconductor device of claim 1 or 2, further comprising a second field plate disposed over the first field plate and electrically connecting the first field plate and one of the source/drain structures.

4. The semiconductor device of claim 3, wherein the second field plate spans at least a portion of the isolation structure and the gate structure exposed by the opening.

5. The semiconductor device of claim 3, wherein the source structure or the drain structure is electrically connected to a ground terminal.

6. The semiconductor device of claim 2, further comprising a second field plate disposed over the first field plate and electrically connecting the drain structure and the first portion of the first field plate, and a third field plate electrically connecting the source structure and the second portion of the first field plate.

7. The semiconductor device of claim 6, wherein the third field plate spans at least a portion of the isolation structure and the gate structure exposed by the opening.

8. The semiconductor device of claim 6, wherein the drain structure is electrically connected to a ground terminal and the source structure is electrically connected to another ground terminal.

9. The semiconductor device of claim 1, wherein the opening exposes a portion of the first well.

10. The semiconductor device of claim 1 or 2, wherein the source structure comprises a first doped region and a second doped region adjacent to each other and having opposite conductivity types.

11. The semiconductor device of claim 10, further comprising a third doped region disposed below the source structure, wherein a doping concentration of the second doped region is greater than a doping concentration of the third doped region.

12. The semiconductor device of claim 1 or 2, wherein the drain structure comprises a first doped region and a second doped region adjacent to each other and having opposite conductivity types.

13. The semiconductor device of claim 12, further comprising a third doped region disposed below the isolation region and a fourth doped region disposed below the third doped region and forming a junction with the third doped region, wherein the third doped region and the fourth doped region have opposite conductivity types.

14. The semiconductor device of claim 12, wherein the first doped region and the second doped region are separated by the first well.

15. The semiconductor device according to claim 1 or 2, further comprising:

an interlayer dielectric layer disposed on the substrate;

a drain contact passing through the interlayer dielectric layer and electrically connected with the drain structure; and

a source contact passing through the interlayer dielectric layer and electrically connected with the source structure.

16. The semiconductor device according to claim 1 or 2, wherein a length of the gate structure in a direction from the source structure toward the isolation structure is greater than a distance between the source structure and the first well.