TWI747328B - Semiconductor device - Google Patents

Abstract

The present disclosure provides a semiconductor device, including: a substrate; a first well and a second well adjoining the first well disposed in the substrate; an isolation structure disposed on the first well; a first field plate disposed on the isolation structure; a gate structure spanning over the first well and the second well, wherein an opening is provided between the first field plate and the gate structure and exposes an edge of the isolation structure adjacent to the gate structure; a drain structure disposed in the first well; and a source structure disposed in the second well.

Description

Semiconductor device

The embodiment of the present invention relates to a semiconductor device, in particular to a semiconductor device including a field plate.

Semiconductor devices can be applied to various fields, such as display driver ICs, power management ICs (or high-power power management ICs), discrete power devices, sensing devices, fingerprint recognition ICs, and memory, etc. Semiconductor devices are usually manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate, and patterning various material layers using lithography technology to form circuit components and components thereon.

In order to improve the breakdown voltage of the semiconductor device, in addition to optimizing the well region and the drift region between the source and drain, generally speaking, the gate is also extended (for example, extended to the drift region or isolation The upper part of the structure is used as a field plate. Although the existing gate field plates generally meet the requirements, they are not satisfactory in all respects.

An embodiment of the present invention provides a semiconductor device, including: a substrate; a first well region and a second well region, which are arranged in the substrate and adjacent to each other; an isolation structure, which is arranged on the first well region; and a first field plate is arranged on the On the isolation structure; the gate structure spans the first well region and the second well region, and there is an opening between the first field plate and the gate structure, and this opening exposes an edge of the isolation structure close to the gate structure; the drain structure , Set in the first well region; and source structure, set in the second well region.

The following disclosure provides many embodiments or examples for implementing different elements of the provided subject matter. Specific examples of each element and its configuration are described below to simplify the description of the embodiments of the present invention. Of course, these are only examples and are not intended to limit the embodiments of the present invention. For example, if the description mentions that the first element is formed on the second element, it may include an embodiment in which the first and second elements are in direct contact, or may include additional elements formed between the first and second elements. , So that they do not directly touch the embodiment. In addition, the embodiment of the present invention may repeat reference numerals and/or letters in various examples. Such repetition is for the purpose of conciseness and clarity, and is not used to indicate the relationship between the different embodiments and/or configurations discussed.

In addition, in some embodiments of the present invention, terms such as "connected", "interconnected", etc. regarding joining and connecting, unless specifically defined, can mean that two structures are in direct contact, or that two structures are not Direct contact, where there are other structures located between the two structures. Moreover, the terms of joining and connecting can also include the case where both structures are movable or both structures are fixed.

Furthermore, words that are relative to space may be used, such as "below", "below", "lower", "above", "higher" and other similar words for ease of description The relationship between one part(s) or feature and another part(s) or feature in the diagram. Spatial relative terms are used to include the different orientations of the device in use or operation, as well as the orientation described in the diagram. When the device is turned to different directions (rotated by 90 degrees or other directions), the spatially relative adjectives used therein will also be interpreted according to the turned position.

The terms "about", "approximately" and "approximately" used here usually mean within ±20% of a given value, preferably within ±10%, and more preferably within ±5%, Or within ±3%, or within ±2%, or within ±1%, or within 0.5%. The value given here is an approximate value, that is, if there is no specific description of "about", "approximately", and "approximately", the given value can still imply "about", "approximately", and "approximately". The meaning of "probably".

Some embodiments of the present invention are described below, and additional steps may be provided before, during, and/or after the multiple stages described in these embodiments. Some of these stages can be replaced or omitted in different embodiments. The semiconductor device structure can add additional components. Some of the described components may be replaced or deleted in different embodiments. Although some of the discussed embodiments are performed in a specific order of steps, these steps may be performed in another logical order.

The following detailed description cooperates with the accompanying drawings to best understand the embodiments of the present invention. It should be noted that according to standard practices in the industry, the various features are not drawn to scale. In fact, the size of various components can be arbitrarily enlarged or reduced to clearly show the characteristics of the embodiments of the present invention.

The impact ionization point (ii point) of a semiconductor device usually appears in the isolation structure next to the source structure (such as STI (shallow trench isolation) structure or local oxidation of silicon (LOCOS) structure). The electric field in the semiconductor device causes Electron-hole pairs generated by impacting free points are injected into adjacent components, resulting in hot carrier injection (HCI), which affects the reliability of the semiconductor device.

The embodiment of the present invention provides a semiconductor device in which the field plate on the isolation structure does not extend to the edge of the isolation region, and the gate structure does not extend to the isolation region. In other words, there is an opening that exposes the edge of the isolation structure between the field plate on the isolation structure and the gate structure, so as to reduce the electric field intensity that strikes the free point near the isolation structure, and further reduce or prevent the hot carrier effect.

For the convenience of description, the following will describe the embodiment of the present invention with a Laterally Diffused Metal Oxide Semiconductor (LDMOS) device with a semiconductor-on-insulator, and describe the application of the embodiment of the present invention to other devices (such as laterally insulated gates). An example of a LIGBT (Lateral Insulated Gate Bipolar Transistor), but the embodiment of the present invention is not limited thereto. Some embodiments of the present invention can also be applied to other types of metal oxide semiconductor devices, such as vertical diffused metal oxide semiconductor (VDMOS) devices, and enhanced diffused metal oxide semiconductor (Extended-Drain Metal Oxide Semiconductor) devices. Semiconductor, EDMOS) device or similar metal oxide semiconductor device. In addition, the present invention can also be applied to other types of semiconductor devices, such as diodes, insulated gate bipolar transistors (IGBT), bipolar junction transistors (Bipolar Junction Transistor, BJT), or the like Of semiconductor devices.

FIG. 1 is a schematic cross-sectional view of a semiconductor device 100 according to some embodiments of the present invention. The semiconductor structure 100 includes: a substrate 110, a first well region 112, a second well region 114, an isolation structure 116, a field plate 118, a gate structure 120, an opening OP, a drain structure 122, a source structure 124, a field plate 126, The interlayer dielectric layer 140, the drain contact 142, the field plate contact 144, and the source contact 146. The substrate 110 may be a doped (for example, doped with p-type or n-type dopants) or an undoped semiconductor substrate. For example, the substrate 110 may include: elemental semiconductors, including silicon or germanium; compound semiconductors, including gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs) and/ Or indium antimonide (InSb); alloy semiconductors, including silicon germanium alloy, phosphorous gallium arsenide alloy, aluminum indium arsenic alloy, aluminum gallium arsenic alloy, indium gallium arsenide alloy, indium gallium phosphate alloy and/or phosphorous indium gallium arsenide alloy, or A combination of the aforementioned materials.

In some embodiments, the substrate 110 may also be a semiconductor on insulator (semiconductor on insulator) substrate, such as silicon on insulator or silicon germanium on insulator (SGOI). In other embodiments, the substrate 110 may be a ceramic substrate, such as an aluminum nitride (AlN) substrate, a silicon carbide (SiC) substrate, an aluminum oxide (Al ₂ O ₃ ) substrate (or called a sapphire substrate), or others Similar base. In other embodiments, the substrate 110 may include a ceramic substrate and a pair of barrier layers respectively provided on the upper and lower surfaces of the ceramic substrate, wherein the ceramic substrate may include a ceramic material, and the ceramic material may include a metal inorganic material. For example, the ceramic substrate may include: silicon carbide, aluminum nitride, sapphire substrate, or other suitable materials. The aforementioned sapphire substrate may be alumina.

The first well area 112 is disposed in the base 110. The method for forming the first well region 112 includes, but is not limited to: using a photolithography process and an etching process to form a patterned mask layer (not shown) on the substrate 110. The patterned mask layer exposes the substrate 110 and is intended to form a first The region of the well region 112 covers other regions of the substrate 110, and then the dopant is implanted in the region where the first well region 112 is scheduled to be formed, and then the patterned mask layer is removed. The aforementioned patterned mask layer can be a hard mask or a photoresist. In the embodiment where the N-type first well region 112 is scheduled to be formed, the aforementioned dopant may be an N-type dopant, such as phosphorus, arsenic, or antimony ions. In the embodiment where the P-type first well region 112 is scheduled to be formed, the aforementioned dopants may be P-type dopants, such as boron, indium, or BF ₂ ⁺ ions.

The second well area 114 is disposed in the base 110 and adjacent to the first well area 112. The method for forming the second well region 114 is similar to the method for forming the first well region 112 described above. In the embodiment of the present invention, the second well region 114 and the first well region 112 have opposite conductivity types. For example, in an embodiment where the first well region 112 is N-type, the dopant used to implant the second well region 114 is a P-type dopant (such as boron, indium, or BF ₂ ⁺ ions) to form P-type second well region 114; in the embodiment where the first well region 112 is P-type, the dopant used to plant the second well region 114 is N-type dopant (such as phosphorus, arsenic, or antimony ions), To form an N-type second well region 114.

In some embodiments, the first well region 112 has a first conductivity type, and the second well region 114 has a second conductivity type opposite to the first conductivity type. Alternatively, the first well region 106 has the second conductivity type and the second well region 108 has the first conductivity type. Specifically, in some embodiments, the first well region 106 may be a p-type well, and the second well region 108 may be an n-type well to serve as an n-type metal-oxide-semiconductor field-effect transistor (NMOS ). In some embodiments, the first well region 112 may be an n-type well, and the second well region 114 may be a p-type well to serve as a p-type metal-oxide-semiconductor field-effect transistor (PMOS). In some embodiments, the doping concentration of the first well region 112 is about 1×10 ¹⁰ cm ⁻³ to 1×10 ²⁰ cm ⁻³ . The doping concentration of the second well region 114 is about 1×10 ¹⁰ cm ^-3 to 1×10 ²⁰ cm ^-3 .

The isolation structure 116 is disposed on the first well region 112. The isolation structure 116 may include shallow trench isolation (STI), local oxidation of silicon (LOCOS), or a combination of the foregoing. In some embodiments, the process of forming shallow trench isolation may include: forming a mask layer (not shown) on the first well region 112 and patterning it, and using the patterned mask layer as an etching mask to A trench is etched in the first well region 112, a deposition process is performed to fill the trench with isolation material, and a planarization process is performed, such as a chemical mechanical polishing (CMP) process or a mechanical grinding process (mechanical grinding process), to remove the isolation The excess part of the material, remove the patterned mask layer. The aforementioned isolation materials may include oxides, nitrides, or oxynitrides, such as silicon oxide, carbon-doped silicon oxide (SiO _x C), silicon oxynitride (SiON), silicon carbon oxynitride (SiOCN), silicon carbide (SiC) ), silicon carbon nitride (SiCN), silicon nitride (Si _x N _y or SiN), silicon-oxycarbide (SiCO) silicon oxide, silicon oxycarbide, silicon oxynitride (silicon oxynitride) , Silicon carbonitride, silicon oxy-carbonitride, any other suitable materials or a combination of the foregoing. In some embodiments, the silicon partial oxidation process for forming the isolation structure 116 may include depositing a mask layer (such as a silicon nitride layer) on the first well region 112, and patterning the mask layer using a lithography process and an etching process. A portion of the first well region 112 is exposed, and a portion of the first well region 112 exposed by thermal oxidation is used to form a silicon oxide layer, and the patterned mask layer is removed.

The field plate 118 is disposed on the isolation structure 116. In some embodiments, the field plate 118 has the effect of reducing the REduced SURface Field (RESURF) and can reduce the electric field intensity at the free point of the isolation structure 116 and its vicinity. The material of the field plate 118 may include conductive materials, such as metals, metal nitrides or doped semiconductors. For example, the metals may be: Au, Ni, Pt, Pd, Ir, Ti, Cr, W, Al, Cu, Similar materials, the aforementioned combination, or the aforementioned multilayer structure; the metal nitride can be: MoN, WN, TiN, TaN, or similar materials; the doped semiconductor is: doped polycrystalline silicon (polycrystalline silicon) or doped polycrystalline germanium. The aforementioned conductive material can be formed through a deposition process, such as: chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) (such as sputtering or evaporation), and then patterning the conductive material , To form a field plate 118.

1, the gate structure 120 spans the first well region 112 and the second well region 114, and there is an opening OP between the field plate 118 and the gate structure 120, and the opening OP exposes the isolation structure 116 close to the gate structure 120 Edge 116E. In some embodiments, the gate structure 120 may include a gate dielectric layer 120 a on the first well region 112 and/or the second well region 114 and a gate electrode 120 b on the gate dielectric layer 120 a. The vertical electric field in the conventional semiconductor device will make the electron-hole pair (electron-hole pair) generated at the edge of the isolation structure generate enough kinetic energy to overcome the potential energy barrier ( potential barrier) and injected into the upper component (such as the gate structure), resulting in severe hot carrier injection, resulting in a reduction in the reliability or life of the device. In the embodiment of the present invention, the opening OP between the field plate 118 and the gate structure 120 exposes the edge 116E of the isolation structure 116 close to the gate structure 120, which can effectively reduce the hot carrier injection (hot carrier injection). Damage to the semiconductor structure, and improve the reliability of the semiconductor structure.

In some embodiments, the method for forming the gate structure 120 includes: sequentially blanket depositing a dielectric material layer (used to form the gate dielectric layer 120a) and a conductive material layer located thereon (used to form the gate electrode) 120b), the dielectric material layer and the conductive material layer are respectively patterned by lithography and etching processes to form the gate dielectric layer 120a and the gate electrode 120b across the first well region 112 and the second well region 114 . In some embodiments, as shown in FIG. 1, in the direction from the source structure 124 to the isolation structure 116, the length L of the gate structure 120 is greater than the distance D between the source structure 124 and the first well region 112 , To ensure that the device can operate normally, if the length L is less than the distance D, the channel may not be opened. The gate dielectric layer 120a may include one or more single-layer or multi-layer dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination of the foregoing. In other embodiments, the gate dielectric layer 120a may include: metal oxide, metal nitride, metal silicide, metal aluminate, zirconium silicate, zirconium aluminate, or a combination of the foregoing, but is not limited thereto . For example, spin coating, chemical vapor deposition, atomic layer deposition, high density plasma chemical vapor deposition, other suitable methods, or a combination of the foregoing can be used to form the gate dielectric layer 120a. The material and forming method of the gate electrode 120b are the same as or similar to the above-mentioned field plate 118, and can be formed by the same deposition and lithography process, or by different processes.

In the embodiment where the gate electrode 120b and the field plate 118 are formed by the same process, the conductive material can be formed through a deposition process, such as chemical vapor deposition, atomic layer deposition, or physical vapor deposition (such as sputtering or evaporation). ), and then pattern the conductive material to form the field plate 118 on the isolation structure 116, the gate electrode 120b across the first well region 112 and the second well region 114, and expose the isolation structure 116 near the gate electrode 120b The opening OP of the edge 116E is as shown in FIG. 1. In some embodiments, the opening OP simultaneously exposes the edge 116E of the isolation structure 116 and a part of the first well region 112, which further reduces the possibility of electron-holes being injected into the upper gate structure 120 or the field plate 118 under the influence of the electric field. Ensure that the hot carrier effect is improved.

The drain structure 122 is disposed in the first well region 112 and the source structure 124 is disposed in the second well region 114. The drain structure 122 includes a doped region having the same conductivity type as the first well region 112. The source structure 124 includes a doped region 124a and a doped region 124b that are adjacent to each other and have opposite conductivity types. The formation method of the doped regions of the drain structure 122 and the source structure 124 is similar to the doping method of the first well region 112 described above. In some embodiments, the semiconductor device 100 further includes a doped region 134 disposed under the source structure 124, wherein the doping concentration of the doped region 124 b is greater than the doping concentration of the doped region 134. In one embodiment, the source electrode 124 and the doping concentration of doped regions 124a, 124b is between about 10 ¹³ cm ^-3 to 10 ²¹ cm ^-3, the doping concentration of doped regions 134 between 10 ¹² cm ^{- From 3} to 10 ¹³ cm ^-3 , the doped region 134 can reduce the on-resistance (R _on ).

Continuing to refer to FIG. 1, the interlayer dielectric layer 140 is located on the substrate 110. The interlayer dielectric layer 140 may include one or more single-layer or multi-layer dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS), and phosphosilicate glass (PSG). ), borophosphosilicate glass (BPSG), low-k dielectric materials, and/or other suitable dielectric materials. Low-k dielectric materials may include (but are not limited to): fluorinated silica glass (FSG), hydrogen silsesquioxane (HSQ), carbon-doped silicon oxide, amorphous Fluorinated carbon, parylene, bis-benzocyclobutenes (BCB), or polyimide. For example, spin coating, chemical vapor deposition, atomic layer deposition, high-density plasma chemical vapor deposition, other suitable methods, or a combination of the foregoing may be used to form the interlayer dielectric layer 140.

As shown in Figure 1, the drain contact 142, the field plate contact 144, and the source contact 146 pass through the interlayer dielectric layer 140 and are electrically connected to the drain structure 122, the field plate 118, and the source structure 124, respectively. Sexual connection. The aforementioned contacts can be formed in the same process. The forming method includes: performing a patterning process on the interlayer dielectric layer 140 to form an opening in the interlayer dielectric layer 140, and then filling the opening with a conductive material and performing a planarization process (Such as chemical mechanical polishing) or etch back process to remove excess material outside the opening. The conductive material and forming method of the contact can be the same as or similar to the conductive material of the field plate 118 described above. In some embodiments, the materials of the drain contact 142, the field plate contact 144, and the source contact 146 may be formed of polysilicon, metal, or other suitable conductive materials. In some embodiments, the materials of the drain contact 142, the field plate contact 144, and the source contact 146 may include copper (Cu), aluminum (Al), molybdenum (Mo), tungsten (W), gold ( Au), chromium (Cr), nickel (Ni), platinum (Pt), titanium (Ti), iridium (Ir), rhodium (Rh), copper alloy, aluminum alloy, molybdenum alloy, tungsten alloy, gold alloy, chromium alloy , Nickel alloy, platinum alloy, titanium alloy, iridium alloy, rhodium alloy, other suitable materials with conductivity or a combination of the foregoing.

Referring to FIG. 1, the field plate 126 is disposed above the field plate 118 and is electrically connected to the field plate 118 and the source structure 124 through the field plate contact 144 and the source contact 146, respectively. The field plate 126 exposes the isolation structure 116 and the gate structure 120 across the opening OP. In addition to reducing the surface electric field, it can also reduce the electric field strength under the opening OP (for example, reducing the impact free point of the isolation structure 116 under the opening OP and its vicinity The electric field strength) and the electric field strength under the gate structure 120 can slow down or prevent the electric field from injecting the electron-hole pairs generated by the free point of the isolation structure 116 into the gate structure 120 or the field plate 118 to improve the heat load Sub-injection can improve the reliability or life of the device without affecting the breakdown voltage of the device. In some embodiments of the present invention, the source structure 124 may be connected to the ground terminal.

One of the objectives of the present invention is to solve the reduction in reliability or lifetime of components caused by the vertical electric field and the lateral electric field. For example, the vertical electric field will cause the injection of hot carriers, and the lateral electric field will cause the electron-hole pairs generated by the isolation structure near the edge 116E of the gate structure 120 to generate enough kinetic energy to overcome the potential energy barrier. Injecting into adjacent components (such as the source structure) causes severe hot carrier injection, resulting in damage or deterioration of the source structure or the drain structure, and reducing the reliability or lifetime of the device. In the embodiment of the present invention, the field plate 126 above the field plate 118 exposes the isolation structure 116 and the gate structure 120 across the opening OP, and electrically connects the field plate 118 and the source structure 124, so that the field plate 118 and the field plate 126 The source structure 124 has the same potential. In addition to the effect of reducing the surface electric field, it can also reduce the transverse electric field intensity at and near the impact free point of the isolation structure 116 under the opening OP, as well as the transverse electric field intensity under the gate structure 120. Slow down or prevent the lateral electric field from injecting the electron-hole pairs generated by the free point of the isolation structure 116 to the source structure 124 to improve the injection of hot carriers, which can improve the reliability of the device without affecting the breakdown voltage of the device Degree or life span.

Figure 2 is a schematic cross-sectional view of a semiconductor device 200 according to some embodiments of the present invention. The semiconductor device 200 is similar to the semiconductor device 100 of Figure 1, except that the field plates 118 of the semiconductor device 200 have separate first A part 118a and a second part 118b. The first part 118a and the second part 118b of the field plate 118 are electrically connected to the field plate 126 through the field plate contacts 144a and 144b, respectively, and a part of the isolation structure 116 is exposed between the first part 118a and the second part 118b. In some embodiments, the field plate 118 having the first portion 118a and the second portion 118b separated from each other can be formed through a patterning process. For the sake of simplicity, in Figure 2 the same components as those in Figure 1 are given the same reference numerals and their descriptions are omitted. The materials and forming methods of the field plate contacts 144a and 144b are the same as or similar to those of the field plate contact 144, and the description will not be repeated here.

The semiconductor structure 200 and the semiconductor structure 100 also include an opening OP between the field plate 118 and the gate structure 120, so that neither the field plate 118 nor the gate structure 120 is located directly above the edge 116E of the isolation structure 116, thereby reducing or preventing vertical The electric field causes the electron-hole pairs generated by hitting the dissociation point to be injected into the upper part to improve the injection of hot carriers. The semiconductor structure 200 also includes a field plate 126 disposed above the field plate 118. In addition to reducing the surface electric field, the field plate 126 can further reduce the electric field strength between the isolation structure 116 and the source structure 124 (for example, under the opening OP and the gate The electric field intensity under the pole structure 120), which slows down or prevents electron-hole pairs generated by hitting free points from being injected into the gate structure 120, the field plate 118, or the source structure 124 to improve the hot carrier injection and improve the device’s performance Reliability or longevity.

In some embodiments, the separated first portion 118a and second portion 118b of the field plate 118 of the semiconductor device 200 can improve the electrical uniformity of the device. For example, according to the design or requirements of the device, the first portion 118a and the second portion 118b of the field plate 118 that are separated from each other can be provided on the isolation structure 116 to improve the higher local electric field, thereby improving the electrical uniformity of the device. . If the electric field distribution under the isolation structure 116 is uneven, the first part 118a and the second part 118b of the field plate 118 that are separated from each other can be provided on the corresponding isolation structure 116 directly above, which can also improve the higher local electric field and thereby improve the device. The electrical uniformity. The embodiment of the present invention does not limit the number of the multiple parts of the field plate 118 separated from each other. The first part 118a and the second part 118b in Figure 2 are only examples. Those with ordinary knowledge in the technical field of the present invention can follow the actual situation. To adjust the number or spacing of the separated parts. If a single field plate still has an excessively high electric field, a separate field plate can be used to help improve the local electric field, thereby improving the electrical uniformity of the device and enhancing the reliability of the device.

Figure 3 is a schematic cross-sectional view of a semiconductor device 300 according to some embodiments of the present invention. The semiconductor device 300 is similar to the semiconductor device 100 of Figure 1, except that the field plate 128 disposed above the field plate 118 is transparent The field plate contact 144 and the drain contact 142 are electrically connected to the field plate 118 and the drain structure 122 respectively. For the sake of simplification, in Figure 3, the same components as those in Figure 1 are given the same reference numerals and their descriptions are omitted.

FIG. 4 is a schematic cross-sectional view of a semiconductor device 400 according to some embodiments of the present invention. The semiconductor device 400 is similar to the semiconductor device 300 of FIG. 3, except that the field plates 118 of the semiconductor device 400 have separate first A part 118a and a second part 118b. The first part 118a and the second part 118b of the field plate 118 are electrically connected to the field plate 128 through the field plate contacts 144a and 144b, respectively, and a part of the isolation structure 116 is exposed between the first part 118a and the second part 118b. In some embodiments, the field plate 118 having the first portion 118a and the second portion 118b separated from each other can be formed through a patterning process. For the sake of simplification, in Figure 4, the same components as those in Figure 3 are given the same reference numerals and their descriptions are omitted. The embodiment of the present invention does not limit the number of the multiple separated parts of the field plate 118, and those with ordinary knowledge in the technical field to which the present invention belongs can make adjustments according to actual conditions.

FIG. 5 is a schematic cross-sectional view of a semiconductor device 500 according to some embodiments of the present invention. The field plate 118 of the semiconductor device 500 has a first portion 118a and a second portion 118b separated from each other, and a part of the isolation structure 116 is exposed between the first portion 118a and the second portion 118b. For the sake of simplification, the same or similar parts in Figure 5 as those in the previous figures are given the same reference numerals and their descriptions are omitted. As shown in FIG. 5, the field plate 130 is disposed above the field plate 118 and is electrically connected to the first portion 118a of the field plate 118 and the drain structure 122 through the field plate contact 144a and the drain contact 142, respectively. The field plate 132 is disposed above the field plate 118 and is electrically connected to the second portion 118 b of the field plate 118 and the source structure 124 through the field plate contact 144 b and the source contact 146, respectively. In some embodiments, as shown in FIG. 5, in the direction from the source structure 124 to the isolation structure 116, the length L of the gate structure 120 is greater than the distance D between the source structure 124 and the first well region 112 , To ensure that the device can operate normally, if the length L is less than the distance D, the channel may not be opened and the device cannot be operated.

In some embodiments as shown in FIG. 5, the field plate 130 spans the area between the drain structure 122 and the isolation structure 116, which can reduce the electric field between the drain structure 122 and the isolation structure 116, and slow down or prevent the electric field. The electron-hole pairs generated by the collision free point of the isolation structure 116 are injected into the drain structure 122 to improve hot carrier injection; the isolation structure 116 and the gate structure 120 exposed by the field plate 132 across the opening OP can reduce The electric field strength under the opening OP (for example, to reduce the electric field strength of the isolation structure 116 under the opening OP and the electric field strength near it) and the electric field strength below the gate structure 120 can slow down or prevent the electric field from causing the isolation structure 116 to hit the free point The generated electron-hole pairs are injected into the gate structure 120, the field plate 118, or the source structure 124 to improve hot carrier injection. In addition, as mentioned above, the first part 118a and the second part 118b of the field plate 118 separated from each other can improve the electrical uniformity of the device. These embodiments can simultaneously improve the effect of hot carrier injection on the drain structure 122, the gate structure 120, the field plate 118, and the source structure 124, and improve the reliability, lifetime, and overall performance of the device. In some embodiments, the drain structure 122 or the source structure 124 may be electrically connected to the ground terminal.

Those skilled in the art to which the present invention pertains can adjust the configuration of the field plate 118 according to actual needs. As shown in the embodiment shown in FIG. 6, a schematic cross-sectional view of the semiconductor device 600 is drawn. The semiconductor device 600 and the fifth The semiconductor device 500 in the figure is similar, the difference is that the field plate 118 of the semiconductor device 600 is composed of three parts separated from each other, including: a first part 118a, a second part 118b, and a third part 118c, and a part of the isolation structure 116 is exposed Between the three separate parts. For the sake of simplification, the same or similar parts in Figure 5 as those in the previous figures are given the same reference numerals and their descriptions are omitted. The field plate 130 of the semiconductor device 600 is electrically connected to the first portion 118a of the field plate 118 and the drain structure 122 through the field plate contact 144a and the drain contact 142, respectively, and the field plate 132 is electrically connected to the first portion 118a of the field plate 118 and the drain structure 122 through the field plate contact 144b and the field plate. The contact 144c, and the source contact 146 are electrically connected to the second portion 118b, the third portion 118c, and the source structure 124, respectively. In some embodiments, the field plate 118 can be formed by a patterning process to have a first portion 118a, a second portion 118b, and a third portion 118c that are separated from each other. As described above, this embodiment can simultaneously improve the effects of hot carrier injection on the drain structure 122, the gate structure 120, the field plate 118, and the source structure 124, avoid component damage or deterioration, and improve the overall performance of the device. Moreover, the distance or the number of the separated parts of the field plate 118 can be adjusted through the patterning process according to the design and functional requirements of the device, which has flexibility in the process.

FIG. 7 is a schematic cross-sectional view of a semiconductor device 700 according to some embodiments of the present invention. The semiconductor device 700 is similar to the semiconductor device 400 of FIG. 4, except that the drain structure 122 of the semiconductor device 700 includes opposite conductivity types. The doped region 122a and the doped region 122b are formed, and the semiconductor device 700 further includes a doped region 136 and a doped region 138. For the sake of simplification, the same components in FIG. 7 as those in FIG. 4 are given the same reference numerals and their description is omitted. The doped region 136 of the semiconductor device 700 is located below the isolation region 116, the doped region 138 is located below and forms a junction with the doped region 136, and the doped region 136 and the doped region 138 have opposite conductivity types. In some embodiments, the doped region 136 and the doped region 138 are formed by ion implantation. In these embodiments, the doped region 136 or the doped region 138 includes at least two sub-implant regions, and the sub-implant regions have different implant concentrations. In some embodiments, the secondary planting area with a higher planting density is adjacent to the aforementioned junction, and the secondary planting area with a lower planting density is far from the aforementioned junction. In this embodiment, in addition to improving the hot carrier injection, the doped region 136 and the doped region 138 of the semiconductor device 700 can also be used to reduce the surface electric field of the isolation region 116 and homogenize the surface electric field of the isolation region 116. The widths of the doped regions 136 and the doped regions 138 in Figure 7 are just examples. For example, the widths of the doped regions 136 and the doped regions 138 may be different from the bottom width of the isolation region 112, or in another In an example, the width of the doped region 136 may also be different from the width of the doped region 138.

FIG. 8 is a schematic cross-sectional view of a semiconductor device 800 according to some embodiments of the present invention. The semiconductor device 800 is similar to the semiconductor device 300 of FIG. 3, except that the drain structure 122 of the semiconductor device 800 includes separate and separate The doped regions 122a and 122b have opposite conductivity types, and the doped regions 122a and 122b are electrically connected to the field plate 128 through the drain contacts 142a and 142b, respectively. The materials and forming methods of the drain contacts 142a and 142b are the same as or similar to those of the above-mentioned drain contact 142, and the description will not be repeated here. For the sake of simplification, the same components in Figure 8 as those in Figure 3 are given the same reference numerals and their descriptions are omitted. In these embodiments, in addition to improving the hot carrier injection, since the doped region 122a and the doped region 122b of the semiconductor device 800 are separated from each other, the access to the drain contact 142b through the doped region 122b can be enlarged, thus increasing the doping. The voltage difference between the impurity region 122b and the first well region 112 enables the semiconductor device 800 to be triggered quickly. In addition, by changing the distance between the doped regions 122a and 122b, the trigger voltage of the semiconductor device 800 can be adjusted. In other embodiments, the semiconductor device 800 may further include an optional doped region located between the isolation region 116 and the doped region 122b and is not connected to the drain contact 142a or 142b. This optional doped region The breakdown voltage of the semiconductor device 800 can be improved.

The semiconductor device provided by the embodiment of the present invention has an opening exposing a part of the isolation structure between the field plate on the isolation structure and the gate structure, which can slow down or prevent the injection of electron-hole pairs generated by the impact of the isolation structure by the electric field. To the upper gate structure or field plate to improve the injection of hot carriers, it can improve the reliability or life of the device without affecting the breakdown voltage of the device. In some embodiments, the field plate on the isolation structure includes multiple parts separated from each other, which can improve the electrical uniformity of the device. In addition, in the embodiment of the present invention, an additional field plate is provided to electrically connect with at least one of the source structure or the drain structure and the field plate on the isolation structure to further reduce the opening below the gate structure, the isolation structure and the isolation structure. The electric field between the source structure or between the isolation structure and the drain structure further slows down or prevents the electron-hole pairs generated by the electric field from impacting the free point of the isolation structure into the adjacent components to improve the hot carrier Inject to avoid component damage or deterioration.

The above summarizes the characteristics of several embodiments so that those with ordinary knowledge in the technical field of the present invention can better understand the various aspects of the present invention. Those with ordinary knowledge in the technical field of the present invention should understand that they can easily use the present invention as a basis to design or modify other processes and structures to achieve the same objectives and/or advantages of the embodiments described herein. . Those having ordinary knowledge in the technical field of the present invention should also understand that such equivalent structures do not depart from the spirit and scope of the present invention, and various changes, substitutions, and substitutions can be made here without departing from the present invention Spirit and scope.

100, 200, 300, 400, 500, 600, 700, 800: semiconductor device 110: Base 112: The first well area 114: The second well area 116: Isolation structure 116E: Edge 118, 126, 128, 130, 132: field board 118a: Part One 118b: Part Two 118c: Part Three 120: Gate structure 120a: gate dielectric layer 120b: gate electrode 122: Drain structure 122a, 122b, 124a, 124b, 134, 136, 138: doped area 124: Source structure 140: Interlayer dielectric layer 142, 142a, 142b: Drain contact 144, 144a, 144b, 144c: field plate contact 146: source contact D: distance L: length OP: opening

Figures 1-8 show cross-sections of semiconductor devices according to some embodiments of the present invention Schematic.

100: Semiconductor device

110: Base

112: The first well area

114: The second well area

116: Isolation structure

116E: Edge

118,126: field board

120: Gate structure

120a: gate dielectric layer

120b: gate electrode

122: Drain structure

124: Source structure

124a, 124b, 134: doped area

140: Interlayer dielectric layer

142: Drain contact

144: Field plate contact

146: source contact

OP: opening

D: distance

L: length

Claims (15)

A semiconductor device includes: a substrate; a first well region and a second well region, which are arranged in the substrate and adjacent to each other; an isolation structure is arranged on the first well region; and a first field plate is arranged On the isolation structure; a gate structure spans the first well region and the second well region, and there is an opening between the first field plate and the gate structure, the opening exposing the isolation structure close to the An edge of the gate structure; a drain structure disposed in the first well region; and a source structure disposed in the second well region, wherein in the direction from the source structure to the isolation structure , The length of the gate structure is greater than the distance between the source structure and the first well region. The semiconductor device of claim 1, wherein the first field plate has a first part and a second part separated from each other, and a part of the isolation structure is exposed between the first part and the second part. For example, the semiconductor device of claim 1 or 2, further includes a second field plate disposed above the first field plate and electrically connected to one of the source/drain structures and the first field plate. The semiconductor device of claim 3, wherein the second field plate straddles at least a part of the isolation structure and the gate structure exposed by the opening. The semiconductor device of claim 3, wherein the source structure or the drain structure is electrically connected to a ground terminal. For example, the semiconductor device of claim 2, further comprising a second field plate and a third field plate, which are arranged above the first field plate and the second field plate is electrically connected to the drain structure and the first field plate In the first part, the third field plate is electrically connected to the source structure and the second part of the first field plate. The semiconductor device of claim 6, wherein the third field plate straddles at least a part of the isolation structure and the gate structure exposed by the opening. The semiconductor device of claim 6, wherein the drain structure is electrically connected to a ground terminal and the source structure is electrically connected to the other ground terminal. The semiconductor device of claim 1, wherein the opening exposes a part of the first well region. The semiconductor device of claim 1 or 2, wherein the source structure includes a first doped region and a second doped region that are adjacent to each other and have opposite conductivity types. For example, the semiconductor device of claim 10 further includes a third doped region disposed under the source structure, wherein the doped concentration of the second doped region is greater than the doped concentration of the third doped region. The semiconductor device of claim 1 or 2, wherein the drain structure includes a first doped region and a second doped region that are adjacent to each other and have opposite conductivity types. For example, the semiconductor device of claim 12, further comprising a third doped region disposed below the isolation region, and a fourth doped region disposed below the third doped region and formed with the third doped region A junction, and the third doped region and the fourth doped region have opposite conductivity types. The semiconductor device of claim 12, wherein the first doped region and the second doped region are separated by the first well region. Such as the semiconductor device of claim 1 or 2, further including: An interlayer dielectric layer is disposed on the substrate; a drain contact that passes through the interlayer dielectric layer and is electrically connected to the drain structure; and a source contact that passes through the interlayer dielectric layer and is connected to the drain structure It is electrically connected to the source structure.

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