CN113838752A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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CN113838752A
CN113838752A CN202010585384.3A CN202010585384A CN113838752A CN 113838752 A CN113838752 A CN 113838752A CN 202010585384 A CN202010585384 A CN 202010585384A CN 113838752 A CN113838752 A CN 113838752A
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layer
sacrificial
forming
isolation
material layer
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CN113838752B (en
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H01L29/7828—Vertical transistors without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure

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Abstract

A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a base, wherein the base comprises a substrate and a first doping layer positioned on the substrate; the process window for forming the sacrificial material layer on the first doping layer is large, the thickness of the sacrificial material layer is easy to control accurately, the thickness uniformity of the sacrificial material layer is high, the sacrificial material layer is etched to form the sacrificial layer, the thickness of the sacrificial layer is accurate, the thickness uniformity of the sacrificial layer is high, after the sacrificial layer is removed, an isolation groove is formed between the work function layer and the substrate, in the normal direction of the surface of the substrate, the size of the isolation groove meets the process requirement, the size uniformity of all positions of the isolation groove is high, the thickness of the isolation layer formed in the isolation groove meets the process requirement, the thickness uniformity of the isolation layer is high, the uniformity of the electrical isolation capability of the isolation layer is high, and the electrical performance and performance uniformity of the semiconductor structure are improved.

Description

Semiconductor structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are moving toward higher element density and higher integration, and the trend of semiconductor process nodes following moore's law is decreasing. Transistors are currently being widely used as the most basic semiconductor devices, and therefore, as the element density and integration of semiconductor devices increase, the channel length of transistors has to be shortened in order to accommodate the reduction of process nodes.
The shortening of the channel length of the transistor has the advantages of increasing the die density of the chip, increasing the switching speed, and the like. However, as the channel length is shortened, the distance between the source and the drain of the transistor is also shortened, and the controllability of the gate to the channel is deteriorated, so that a sub-threshold leakage (SCE) phenomenon, which is a so-called short-channel effect (short-channel leakage) is more likely to occur, and the channel leakage current of the transistor is increased.
Therefore, in order to better accommodate the scaling requirements of device dimensions, semiconductor processes are gradually starting to transition from planar transistors to more power efficient three-dimensional transistors, such as Gate-all-around (GAA) transistors. In the all-around gate transistor, the gate surrounds the region where the channel is located from the periphery, and compared with a planar transistor, the all-around gate transistor has stronger control capability on the channel, and can better inhibit a short-channel effect.
The fully-wrapped Gate transistor includes a transverse Gate-all-around (LGAA) transistor and a Vertical Gate-all-around (VGAA) transistor, in which a channel of the VGAA extends in a direction perpendicular to a surface of a substrate, which is advantageous for improving an area utilization efficiency of a semiconductor structure, and thus is advantageous for realizing a further reduction in feature size.
Disclosure of Invention
Embodiments of the present invention provide a semiconductor structure and a method for forming the same, which optimize the performance of the semiconductor structure.
To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a base, wherein the base comprises a substrate and a first doping layer positioned on the substrate; forming a sacrificial material layer on the first doping layer; forming a dielectric material layer on the sacrificial material layer; forming a semiconductor channel column penetrating through the dielectric material layer and the sacrificial material layer and connected with the first doping layer; after the semiconductor channel column is formed, removing the dielectric material layer; after removing the dielectric material layer, forming a work function layer on the side wall of the semiconductor channel column and the sacrificial material layer; after the work function layer is formed, etching the sacrificial material layer far away from the semiconductor channel column, and taking the remaining sacrificial material layer close to the semiconductor channel column as a sacrificial layer; removing the sacrificial layer, and forming an isolation groove between the work function layer and the substrate; and forming an isolation layer in the isolation groove.
Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: a substrate; the first doping layer is positioned on the substrate; the semiconductor channel column is separated on the first doping layer; the sacrificial layer is positioned on the side part of the semiconductor channel column, covers part of the side wall of the semiconductor channel column, and is exposed out of the first doping layer far away from the semiconductor channel column; and the work function layer is positioned on the sacrificial layer and on the side wall of the semiconductor channel column higher than the sacrificial layer.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the method for forming a semiconductor structure provided by the embodiment of the invention, a sacrificial material layer is formed to occupy a spatial position for forming an isolation layer subsequently, the sacrificial material layer is formed on the first doping layer, the top surface of the first doping layer is a plane, a corresponding process window for forming the sacrificial material layer is large, the thickness of the sacrificial material layer is easy to control accurately, the uniformity of the thickness of the sacrificial material layer is high, the sacrificial material layer is etched to form the sacrificial layer, the thickness of the sacrificial layer is accurate, the uniformity of the thickness of the sacrificial layer is high, after the sacrificial layer is removed, an isolation groove is formed between the work function layer and the substrate, the size of the isolation groove meets process requirements in the normal direction of the surface of the substrate, and the size uniformity of each part of the isolation groove is high, so that the thickness of the isolation layer formed in the isolation groove meets process requirements, and the thickness uniformity of the isolation layer is higher, and the uniformity of the electrical isolation capability of the isolation layer is high, so that the electrical property and the performance uniformity of the semiconductor structure can be improved. Generally, the number of the semiconductor channel columns is multiple, because the thickness uniformity of the sacrificial material layer is higher, correspondingly, the semiconductor channel columns covered by the sacrificial material layer are the same in size in the normal direction of the surface of the substrate, correspondingly, the semiconductor channel columns covered by the subsequently formed isolation layer are the same in size, the semiconductor channel columns are higher in size uniformity when used as channel regions, and when the semiconductor structure works, the uniformity of conduction current in the channels is higher, so that the electrical performance of the semiconductor structure is improved.
Drawings
FIGS. 1-3 are schematic structural diagrams of a semiconductor structure;
fig. 4 to 16 are schematic structural views corresponding to steps in a first embodiment of a method for forming a semiconductor structure according to an embodiment of the present invention;
fig. 17 and 18 are schematic structural views corresponding to respective steps in a second embodiment of a method of forming a semiconductor structure according to an embodiment of the present invention;
FIG. 19 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention.
Detailed Description
The semiconductor structure formed at present still has a problem of poor performance. The reason for the poor performance of a semiconductor structure is now analyzed in conjunction with a semiconductor structure.
Fig. 1 to 3 are schematic structural diagrams of a semiconductor structure.
As shown in fig. 1, the semiconductor structure includes: a substrate 1; a source doping layer 2 located on the substrate 1; the semiconductor channel column 3 is separated on the source doping layer 2; and the isolation material layer 4 is positioned on the source doping layer 2 at the side part of the semiconductor channel column 3.
As shown in fig. 2, said layer of isolating material 4 is etched back partially thick, forming an isolating layer 5.
As shown in fig. 3, a gate structure 6 is formed on the sidewall of the semiconductor channel pillar 3; a drain doping layer 7 is formed on top of the semiconductor channel pillar 3.
After the isolation material layer 4 is formed on the source doping layer 2 on the side portion of the semiconductor channel column 3, the isolation material layer 4 with partial thickness is etched back, the rest isolation material layer 4 is used as the isolation layer 5, the process operation controllability of the isolation material layer 4 with partial thickness etched back is poor, the thickness of the isolation layer 5 cannot be well controlled, and therefore the isolation layer 5 cannot well play a role in electrical isolation. In addition, in the process of etching the isolation material layer 4 to form the isolation layer 5, the isolation material layer 4 close to the semiconductor channel column 3 is not easy to remove, the thickness of the isolation layer 5 close to the semiconductor channel column 3 is higher than that of the isolation layer 5 far away from the semiconductor channel column 3, the electrical isolation capability of the isolation layer 5 close to the semiconductor channel column 3 is different from that of the isolation layer far away from the semiconductor channel column 3, and therefore poor electrical performance and poor electrical performance uniformity of the semiconductor structure are caused.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: by forming a sacrificial material layer to occupy a spatial position for subsequently forming an isolation layer, the sacrificial material layer is formed on the first doping layer, the top surface of the first doping layer is a plane, a corresponding process window for forming the sacrificial material layer is large, the thickness of the sacrificial material layer is easy to accurately control, the thickness uniformity of the sacrificial material layer is high, the sacrificial material layer is etched to form the sacrificial layer, the thickness of the sacrificial layer is accurate, the thickness uniformity of the sacrificial layer is high, after the sacrificial layer is removed, an isolation groove is formed between the work function layer and the substrate, the size of the isolation groove meets process requirements in the normal direction of the surface of the substrate, the size uniformity of each isolation groove is high, so that the thickness of the isolation layer formed in the isolation groove meets process requirements, and the thickness uniformity of the isolation layer is high, the isolation layer has high uniformity of electrical isolation capability, and is beneficial to improving the electrical performance and the performance uniformity of the semiconductor structure. Generally, the number of the semiconductor channel columns is multiple, because the thickness uniformity of the sacrificial material layer is higher, correspondingly, the semiconductor channel columns covered by the sacrificial material layer are the same in size in the normal direction of the surface of the substrate, correspondingly, the semiconductor channel columns covered by the subsequently formed isolation layer are the same in size, the semiconductor channel columns are higher in size uniformity when used as channel regions, and when the semiconductor structure works, the uniformity of conduction current in the channels is higher, so that the electrical performance of the semiconductor structure is improved.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.
Fig. 4 to 16 are schematic structural diagrams corresponding to steps in the first embodiment of the method for forming a semiconductor structure according to the embodiment of the present invention.
Referring to fig. 4, a base is provided, the base including a substrate 100 and a first doping layer 101 on the substrate 100.
In this embodiment, the method for forming a semiconductor structure is used to form a gate all around structure (GAA). In this embodiment, the substrate includes a device sparse region and a device dense region, and the device density of the device sparse region is lower than the device density of the device dense region.
The substrate 100 provides a process platform for subsequently forming semiconductor structures.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate material can also be germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
The first doped layer 101 and the second doped layer formed later together serve as a source of the semiconductor structure, and when the semiconductor structure operates, the source provides stress for the channel to increase the migration rate of carriers in the channel.
In this embodiment, the material of the first doping layer 101 is silicon germanium with doping ions. In other embodiments, the material of the first doped layer may also be silicon with doping ions.
In this embodiment, the method for forming the semiconductor structure is used to form a pmos (positive Channel Metal Oxide semiconductor) transistor, the doped ions in the corresponding first doped layer 101 are P-type ions, the P-type ions replace the positions of silicon atoms in the crystal lattice, and the more P-type ions are doped, the higher the concentration of majority ions is, and the higher the conductivity is. Specifically, the P-type ions include B, Ga or In.
In other embodiments, the method for forming a semiconductor structure is used to form an nmos (negative channel Metal Oxide semiconductor) transistor, the doped ions in the first doped layer are N-type ions, the N-type ions replace silicon atoms in the lattice, and the more N-type ions are doped, the higher the concentration of majority ions is, and the higher the conductivity is. Specifically, the N-type ions include P, As or Sb.
Specifically, the step of forming the first doping layer 101 includes: a Selective epitaxial growth process (SEG) is used to form a stress layer, and in the process of forming the stress layer, an in-situ self-doping process is used to dope ions into the stress layer to form the first doping layer 101.
The stress layer obtained through the selective epitaxial growth process is high in purity and few in defects, and the formation quality of the doping layer 101 is improved, so that the migration rate of carriers in a channel is improved when the semiconductor structure works. In other embodiments, the stress layer may be formed by a process such as molecular beam epitaxy.
Referring to fig. 5, a sacrificial material layer 102 is formed on the first doping layer 101.
In the method for forming a semiconductor structure provided by the embodiment of the invention, the sacrificial material layer 102 is formed to occupy a spatial position for forming an isolation layer subsequently, the sacrificial material layer 102 is formed on the first doping layer 101, the top surface of the first doping layer 101 is a plane, a corresponding process window for forming the sacrificial material layer 102 is large, the thickness of the sacrificial material layer 102 is easily and accurately controlled, the uniformity of the thickness of the sacrificial material layer 102 is high, the sacrificial material layer 102 is etched to form the sacrificial layer, the thickness of the sacrificial layer is accurate, the uniformity of the thickness of the sacrificial layer is high, the isolation groove is formed after the sacrificial layer is removed, the size of the isolation groove meets process requirements in the normal direction of the surface of the substrate 100, the uniformity of the size of each isolation groove is high, the thickness of the isolation layer formed in the isolation groove meets process requirements, and the uniformity of the thickness of the isolation layer is high, the isolation layer has high uniformity of electrical isolation capability, and is beneficial to improving the electrical performance and the performance uniformity of the semiconductor structure.
The sacrificial material layer 102 is also used to provide a formation process foundation for the semiconductor channel pillar in cooperation with a subsequently formed dielectric material layer.
In this embodiment, the sacrificial material layer 102 is formed by a selective epitaxial growth process. The selective epitaxial growth process can precisely control the thickness of the sacrificial material layer 102, and further control the thickness of the sacrificial layer formed by the subsequent etching of the sacrificial material layer 102. The sacrificial material layer 102 obtained by the selective epitaxial growth process has high purity and few defects, and is beneficial to improving the forming quality of the sacrificial material layer 102, the corresponding sacrificial layer has high purity and few defects, the forming quality of the sacrificial layer is high, and the sacrificial layer is not easy to have residues in the corresponding subsequent step of removing the sacrificial layer. In addition, the selective epitaxial growth process has the advantages of simple process, fast growth, low cost, no need of ultrahigh vacuum, convenience for industrial mass production and the like. In other embodiments, other processes capable of precisely controlling the film formation thickness may be used to form the sacrificial material layer.
In the subsequent step of removing the sacrificial layer, the etching selectivity of the sacrificial layer and the first doped layer 101 is not too small. If the etching selection ratio is too small, the first doping layer 101 is easily damaged in the step of removing the sacrificial layer, and when the semiconductor structure works, the first doping layer 101 is not easy to provide sufficient stress for a subsequently formed semiconductor channel column, so that the migration rate of carriers in the semiconductor channel column is poor. In this embodiment, in the subsequent step of removing the sacrificial layer, the etching selectivity ratio between the sacrificial layer and the first doped layer 101 is greater than 10.
Specifically, the material of the sacrificial material layer 102 includes silicon germanium. In this embodiment, the material of the sacrificial material layer 102 includes silicon germanium.
It should be noted that in the step of forming the sacrificial material layer 102, the sacrificial material layer 102 is not too thick nor too thin. If the sacrificial material layer 102 is too thick, correspondingly, the sacrificial material layer 102 is etched subsequently, the formed sacrificial layer is too thick, the sacrificial layer is removed subsequently, an isolation groove is formed, the size of the isolation groove on the normal line of the surface of the substrate 100 is too large, the size of the semiconductor structure in the normal line direction of the surface of the substrate 100 is too large due to the fact that the isolation layer formed in the isolation groove subsequently is too thick, the integration degree of the semiconductor structure in the normal line direction of the surface of the substrate 100 is poor, and the power consumption of the semiconductor structure is high. If the sacrificial material layer 102 is too thin, the dimension of the subsequently formed isolation trench on the normal line of the substrate 100 is too small, and in the subsequent step of forming the isolation layer in the isolation trench, the isolation trench is not easily filled with the isolation layer, a void (void) is easily present in the isolation layer, the formation quality of the corresponding isolation layer is poor, and the isolation layer cannot well electrically isolate the first doping layer 101 and the subsequently formed gate structure. In the present embodiment, the thickness of the sacrificial material layer 102 is 3 nm to 8 nm.
With continued reference to fig. 5, a layer of dielectric material 103 is formed on the layer of sacrificial material 102.
The dielectric material layer 103 and the sacrificial material layer 102 are prepared for the subsequent formation of openings.
In this embodiment, the material of the dielectric material layer 103 includes silicon oxide.
In this embodiment, the dielectric material layer 103 is formed by a Flowable Chemical Vapor Deposition (FCVD) process. The flowable chemical vapor deposition process has good filling capacity, is favorable for reducing the probability of defects such as cavities and the like formed in the dielectric material layer, and is correspondingly favorable for improving the film forming quality of the dielectric material layer.
As shown in fig. 5, a layer of masking material 104 is formed on the layer of dielectric material 103.
The mask material layer 104 is patterned to form a mask layer, which is used as a mask for etching the dielectric material layer 103 and the sacrificial material layer 102 to form an opening.
Specifically, the material of the mask material layer 104 includes one or more of silicon oxynitride, silicon carbonitride, and silicon nitride. In this embodiment, the material of the mask material layer 104 includes silicon nitride.
Referring to fig. 6 and 7, a semiconductor channel pillar 107 (shown in fig. 7) is formed through the dielectric material layer 103 and the sacrificial material layer 102 and connected to the first doped layer 101.
The semiconductor channel pillar 107 serves as a channel when the semiconductor structure is in operation.
In this embodiment, the material of the semiconductor channel pillar 107 is silicon. In other embodiments, the material of the semiconductor channel pillar may also be germanium, silicon carbide, gallium arsenide, or gallium indium arsenide.
It should be noted that, in general, the substrate includes a device sparse region and a device dense region, the density of the semiconductor channel pillars 107 in the device sparse region is lower than the density of the semiconductor channel pillars 107 in the device dense region, the number of the semiconductor channel pillars 107 is multiple, because the thickness uniformity of the sacrificial material layer 102 is higher, correspondingly, in the normal direction of the surface of the substrate 100, the size of the semiconductor channel pillars 107 covered by the sacrificial material layer 102 is the same, correspondingly, the size of the semiconductor channel pillars 107 covered by the subsequently formed isolation layer in the device sparse region and the device dense region is the same, the size uniformity of the semiconductor channel pillars 107 used as the channel region in the device sparse region and the device dense region is higher, when the semiconductor structure operates, the uniformity of the conduction current in the channel in the device sparse region and the device dense region is higher, which is beneficial to improving the electrical performance of the semiconductor structure.
As shown in fig. 6, the method for forming a semiconductor structure includes: before forming the semiconductor channel pillar 107, the dielectric material layer 103 and the sacrificial material layer 102 are etched to form an opening 105 exposing the first doping layer 101.
The opening 105 provides a process space for the subsequent formation of a semiconductor channel pillar.
The step of forming the opening 105 includes: patterning the mask material layer 104 to form a mask layer 106; the dielectric material layer 103 and the sacrificial material layer 102 are etched using the mask layer 106 as a mask to form an opening 105 exposing the first doping layer 101.
In this embodiment, the dielectric material layer 103 and the sacrificial material layer 102 are etched by a dry etching process using the mask layer 106 as a mask. The dry etching process has anisotropic etching characteristics and better etching profile controllability, is favorable for enabling the appearance of the opening 105 to meet the process requirements, and is also favorable for improving the removal efficiency of the dielectric material layer 103 and the sacrificial material layer 102. In the step of forming the opening 105 by using the dry etching process, the top of the first doped layer 101 can be used as an etching stop position, so that damage to other film structures is reduced. In addition, the dielectric material layer 103 and the sacrificial material layer 102 can be etched in the same etching equipment by replacing the etching gas, so that the process steps are simplified.
Accordingly, a semiconductor channel pillar 107 is formed in the opening 105.
The step of forming the semiconductor channel pillar 107 includes: forming a semiconductor channel pillar material layer (not shown) in the opening 105 by using a selective epitaxial growth method, wherein the top of the semiconductor channel pillar material layer is higher than the top of the mask layer 106; the semiconductor channel pillar material layer higher than the mask layer 106 is removed, and the remaining semiconductor channel pillar material layer in the opening 105 serves as a semiconductor channel pillar 107.
In this embodiment, a semiconductor channel pillar material layer is formed by using a selective epitaxial growth process. The semiconductor channel column material layer formed by the selective epitaxial growth process has high epitaxial growth purity and is not easy to have defects, and correspondingly, the semiconductor channel column 107 has high formation quality, and the migration rate of carriers in the semiconductor channel column 107 is favorably improved when the semiconductor structure works.
Referring to fig. 8, after forming the semiconductor channel pillar 107, the dielectric material layer 103 is removed.
The dielectric material layer 103 is removed in preparation for subsequent formation of the gate structure.
In this embodiment, the dielectric material layer 103 is removed by a wet etching process. The wet etching process has the advantages of high etching rate, simple operation and low process cost.
Specifically, the dielectric material layer 103 is silicon oxide, and the corresponding wet etching solution includes a hydrogen fluoride solution.
Before the dielectric material layer 103 is removed, the mask layer 106 is removed.
In this embodiment, the mask layer 106 is removed by using a wet etching solution. The wet etching process has the advantages of high etching rate, simple operation and low process cost.
Specifically, the material of the mask layer 106 includes silicon nitride. The corresponding wet etching solution for removing the mask layer 106 includes a phosphoric acid solution.
Referring to fig. 9, after removing the dielectric material layer 103, a work function layer 108 is formed on the sidewalls of the semiconductor channel pillars 107 and the sacrificial material layer 102.
The work function layer 108 is used to adjust the threshold voltage of the semiconductor structure during operation of the semiconductor structure.
In this embodiment, where the semiconductor structure is used to form a PMOS, the material of the corresponding work function layer 108 includes one or more of titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride, and tantalum carbide. In other embodiments, the semiconductor structure is an NMOS, and accordingly, the material of the work function layer includes one or more of titanium aluminide, tantalum carbide, aluminum, and titanium carbide.
In this embodiment, the work function layer 108 is formed by an Atomic Layer Deposition (ALD) process. The atomic layer deposition process is a Self-limiting (Self-limiting) reaction process based on the atomic layer deposition process, the deposited film can reach the thickness of a single layer of atoms, and because the atomic layer deposition process can accurately deposit one atomic layer in each period, the atomic layer deposition process is selected to be beneficial to accurately controlling the thickness of the work function layer 108, and in addition, the film prepared by the ALD process has the characteristics of good bonding strength, consistent film thickness, good component uniformity, good conformality and the like, and is beneficial to improving the thickness uniformity and the film quality of the work function layer 108. In other embodiments, the work function layer may also be formed using a Metal Organic Chemical Vapor Deposition (MOCVD) process.
Note that the work function layer 108 is also formed on top of the semiconductor channel pillar 107.
The method for forming the semiconductor structure further comprises the following steps: after removing the dielectric material layer 103, a gate dielectric layer 109 is formed on the sidewalls of the semiconductor channel pillar 107 and the sacrificial material layer 102 before forming the work function layer 108.
The gate dielectric layer 109 is used to electrically isolate the semiconductor channel pillar 107 from subsequently formed gate structures.
The gate dielectric layer 109 is made of a high-k dielectric material. Wherein, the high-k dielectric material is a dielectric material with a relative dielectric constant larger than that of silicon oxide.
In this embodiment, the gate dielectric layer 109 is made of HfO2. In other embodiments, the material of the gate dielectric layer may also be selected from ZrO2HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3One or more of them.
With continued reference to fig. 9, the method of forming a semiconductor structure further comprises: after the work function layer 108 is formed, the sacrificial material layer 102 is subsequently etched, and before the sacrificial layer is formed, a protective layer 110 is formed on the sidewall of the semiconductor channel pillar 107.
Subsequently forming a shielding layer covering the protective layer 110 and the semiconductor channel pillar 107; the sacrificial material layer 102 is etched using the masking layer as a mask to form a sacrificial layer.
In the step of forming the sacrificial layer, the protective layer 110 protects the work function layer 108 on the sidewall of the semiconductor channel pillar 107 from being damaged.
And subsequently removing the sacrificial layer to form an isolation groove, wherein the step of forming the isolation layer in the isolation groove comprises the following steps: forming an isolation material layer on the isolation layer and the sidewall of the work function layer 108; and etching back the partial thickness of the isolation material layer, wherein the rest isolation material layer in the isolation groove is used as an isolation layer. The protective layer protects the work function layer 108 on the sidewalls of the semiconductor channel pillar 107 from damage during the step of back etching a portion of the thickness of the spacer material layer.
In this embodiment, the material of the protection layer 110 includes: one or more of SiON, SiBCN, SiCN, carbon doped SiN, and oxygen doped SiN.
The forming step of the protective layer 110 includes: forming a protective material layer (not shown) on the semiconductor channel pillar 107 and the exposed sacrificial material layer 102 of the semiconductor channel pillar 107; the top of the semiconductor channel pillar 107 and the protective material layer on the sacrificial material layer 102 are removed, and the remaining protective material layer on the sidewall of the semiconductor channel pillar 107 serves as the protective layer 110.
In this embodiment, an atomic layer deposition process is used to form the protective material layer. The atomic layer deposition process comprises multiple atomic layer deposition cycles, which is beneficial to improving the thickness uniformity of the protective material layer, so that the protective material layer can conformally cover the side wall of the semiconductor channel column 107, the top of the semiconductor channel column 107 and the sacrificial material layer 102; in addition, the gap filling performance and the step coverage performance of the atomic layer deposition process are good, and the conformal coverage capability of the protective material layer is correspondingly improved. In other embodiments, the protective material layer may also be formed by a Chemical Vapor Deposition (CVD) process.
In the step of forming the protective layer 110 with the direction perpendicular to the sidewall of the semiconductor channel pillar 107 as the lateral direction, the lateral dimension of the protective layer 110 is not preferably too large or too small. If the lateral dimension of the protection layer 110 is too large, it is easy to spend too much process time and material to form the protection layer 110, resulting in a low forming efficiency of the protection layer 110. If the lateral dimension of the protection layer 110 is too small, the protection layer 110 is easily removed by etching in the subsequent step of etching the sacrificial material layer 102 to form a sacrificial layer, and the protection layer 110 cannot well protect the work function layer 108. In the present embodiment, in the step of forming the protective layer 110 on the sidewall of the semiconductor channel pillar 107, the lateral dimension of the protective layer 110 is 2 nm to 8 nm.
Referring to fig. 10 to 12, after forming the work function layer 108, the sacrificial material layer 102 away from the semiconductor channel pillar 107 is etched, and the sacrificial material layer 102 remaining close to the semiconductor channel pillar 107 is used as a sacrificial layer 111 (as shown in fig. 11).
And a sacrificial layer 111 occupying a spatial location for subsequent formation of an isolation layer.
The step of etching the sacrificial material layer 102 to form the sacrificial layer 111 includes: forming a shielding layer 112 covering the protective layer 110 and the semiconductor channel pillar 107; the sacrificial material layer 102 is etched using the masking layer 112 as a mask to form a sacrificial layer 111.
Specifically, the shielding layer 112 exposes the work function layer 108 away from the semiconductor channel pillar 107.
In this embodiment, the sacrificial layer 102 is etched using the shielding layer 112 as a mask to form a sacrificial layer 111. The dry etching process has anisotropic etching characteristics and good etching profile controllability, is favorable for enabling the appearance of the sacrificial layer 111 to meet the process requirements, and is also favorable for improving the removal efficiency of the sacrificial material layer 102. In the dry etching process, the gate dielectric layer 109, the work function layer 108 and the sacrificial material layer 102 can be etched in the same etching device by replacing the etching gas, so that the process steps are simplified.
The blocking layer 112 is a material that can function as a mask and is easy to remove, so that the work function layer 108 is not easily damaged during the subsequent removal of the blocking layer 112.
Specifically, the material of the shielding layer 112 is an organic material, such as: BARC (bottom-antireflective coating) material, ODL (organic dielectric layer) material, photoresist, DARC (dielectric-antireflective coating) material, DUO (Deep UV Light Absorbing Oxide) material, or APF (Advanced Patterning Film) material.
Specifically, the step of forming the shielding layer 112 includes: forming a shielding material layer (not shown) covering the sacrificial material layer 102, the semiconductor channel pillar 107 and the work function layer 108, wherein the top surface of the shielding material layer is higher than the top surface of the work function layer 108; the patterned masking material layer forms a masking layer 112.
In this embodiment, the blocking material layer is formed by a spin coating process. The surface flatness of the shielding material layer is high.
As shown in fig. 12, the method for forming a semiconductor structure further includes: after the sacrificial layer 111 is formed, the shielding layer 112 is removed.
In this embodiment, the material of the shielding layer 112 is an organic material, and the ashing process is correspondingly used to remove the shielding layer 112.
Referring to fig. 13, the sacrificial layer 111 is removed, and an isolation groove 113 is formed between the work function layer 108 and the substrate 100.
A gate structure is subsequently formed on the isolation trench 113. The isolation trenches 113 provide for the subsequent formation of isolation layers, and the dimension of the isolation trenches 113 in the direction of the surface normal of the substrate 100 determines the thickness of the isolation layer and, accordingly, the electrical isolation effect of the isolation layer.
In this embodiment, the sacrificial layer 111 is removed by a wet etching process. The wet etching process has the advantages of high etching rate, simple operation and low process cost.
Since the thickness uniformity of the sacrificial layer 111 is high, accordingly, the uniformity of the formed isolation trenches 113 is high, that is, the uniformity of the size of the semiconductor channel pillars 107 exposed by the isolation trenches 113 in the normal direction of the surface of the substrate 100 is high.
Referring to fig. 14 and 15, an isolation layer 114 is formed in the isolation trench 113.
A gate layer is subsequently formed on the work function layer 108 on the sidewall of the semiconductor channel pillar 107, and the work function layer 108 and the gate layer serve as a gate structure. The isolation layer 114 serves to electrically isolate the gate structure from the first doped layer 101.
In this embodiment, the material of the isolation layer 114 includes silicon oxide.
The step of forming the isolation layer 114 in the isolation trench 113 includes: forming an isolation material layer (not shown) on the substrate 100 exposed by the semiconductor channel pillar 107, wherein the isolation material layer covers the top of the semiconductor channel pillar 107; a portion of the thickness of the spacer material layer is etched back and the remaining spacer material layer serves as the spacer layer 114.
In this embodiment, a Flow Chemical Vapor Deposition (FCVD) process is used to form the isolation material layer. The flowable chemical vapor deposition process has good filling capacity, is favorable for reducing the probability of defects such as cavities and the like in the isolation layer, and is correspondingly favorable for improving the film forming quality of the isolation layer.
It should be noted that, in the step of etching back the isolation material layer with a partial thickness, the work function layer 108 on top of the semiconductor channel pillar 107 plays a role of protecting the top of the semiconductor channel pillar 107.
It should be noted that, in this embodiment, the isolation layer 114 covers the sidewall of the work function layer 108. That is, the thickness of the isolation layer 114 near the semiconductor channel pillar 107 is smaller than the thickness of the isolation layer 114 far from the semiconductor channel pillar 107, so that the gate layer formed directly on the isolation layer 114 can be well electrically isolated, which is beneficial to improving the electrical performance of the semiconductor structure.
In general, the number of the semiconductor channel pillars 107 is large, and the uniformity of the size of the semiconductor channel pillars 107 exposed from the isolation trenches 113 is high. Correspondingly, the semiconductor channel pillars 107 covered by the formed isolation layer 114 have the same size, the uniformity of the size of the semiconductor channel pillars 107 used as a channel region is higher, and the uniformity of the conduction current in the channel is higher when the semiconductor structure works, which is beneficial to improving the electrical performance of the semiconductor structure.
As shown in fig. 15, the method for forming a semiconductor structure further includes: after the isolation layer 114 is formed in the isolation groove 113, the protection layer 110 is removed.
The protective layer 110 is removed in preparation for subsequent formation of a gate layer over the work function layer 108.
In this embodiment, a wet etching process is used to remove the protection layer 110. In the process of removing the protective layer 110, the etching rate of the protective layer 110 is greater than that of the isolation layer 114; the protective layer 110 is etched at a rate greater than the work function layer 108. The wet etching process has the advantages of high etching rate, simple operation and low process cost.
In this embodiment, the material of the protection layer 110 includes silicon nitride, and the corresponding wet etching solution for removing the protection layer 110 includes a phosphoric acid solution.
Referring to fig. 16, the method of forming the semiconductor structure further includes: after forming the isolation layer 114, a gate material layer (not shown) is formed on the work function layer 108; removing a part of the gate material layer to expose the top of the semiconductor channel pillar 107, and using the remaining gate material layer as a gate layer 116; the work function layer 108 exposing the gate layer 116 is removed, and the gate layer 116 and the remaining work function layer 108 serve as the gate structure 115.
The gate structure 115 is used to control the opening and closing of the channel during operation of the semiconductor structure.
The gate material layer is used to prepare the gate layer 116 for subsequent formation.
In this embodiment, the material of the gate material layer includes a magnesium-tungsten alloy. In other embodiments, the material of the gate material layer may also be W, Al, Cu, Ag, Au, Pt, Ni, Ti, or the like.
The step of forming the gate layer 116 includes: forming an interlayer dielectric layer 116 exposing the top of the semiconductor channel column 107 on the side of the semiconductor channel column 107; the gate material layer exposing the interlayer dielectric layer 116 is removed by using the interlayer dielectric layer 116 as a mask, and the remaining gate material layer is used as the gate layer 116.
The material of the interlayer dielectric layer 116 is an insulating material. Specifically, the material of the interlayer dielectric layer 116 includes one or more of silicon oxide, silicon oxynitride, silicon carbonitride and silicon nitride. In this embodiment, the interlayer dielectric layer 116 is made of silicon oxide.
In this embodiment, the work function layer 108 exposing the gate layer 116 is removed by using the interlayer dielectric layer 116 as a mask.
The method for forming the semiconductor structure further comprises the following steps: after removing the work function layer 108 exposing the gate layer 116, a second doping layer 117 is formed on top of the semiconductor channel pillar 107.
The second doping layer 117 and the first doping layer 101 serve as source-drain doping layers of the semiconductor channel pillar 107.
In this embodiment, the second doping layer 117 is formed on the top of the semiconductor channel pillar 107 by an ion implantation process. The ion implantation process has the characteristics of simple operation and low process cost.
Referring to fig. 17 and 18, there are shown schematic structural views corresponding to key steps in a second embodiment of a method of forming a semiconductor structure.
The same parts of this embodiment as those of the first embodiment are not described herein again, and the differences from the first embodiment are as follows:
the forming method of the semiconductor structure comprises the following steps: after forming the work function layer 208 and before forming the sacrificial layer, a gate material film 218 is formed on the semiconductor channel pillar 207 and the sacrificial material layer 202 exposed by the semiconductor channel pillar 207 (as shown in fig. 17); forming a protection layer 210 on sidewalls of the gate material film 218; forming a barrier layer 212 covering the top of the protection layer 210 and the top of the semiconductor channel pillar 207 with a film of gate material; gate material film 218 is etched using the top of sacrificial material layer 202 as an etch stop and masking layer 212 as a mask, forming gate material layer 219 that exposes sacrificial material layer 202.
The step of forming the sacrificial layer 211 includes: sacrificial material layer 202 is etched using masking layer 212 as a mask to form sacrificial layer 211.
In an embodiment of the present invention, the method for forming the semiconductor structure further includes: forming an interlayer dielectric layer exposing the top of the semiconductor channel column 207, removing the work function layer 208 and the gate material layer 219 exposed by the interlayer dielectric layer, and using the remaining work function layer 208 and the gate material layer 219 as a gate structure.
In the embodiment of the invention, the barrier layer 212 is used as a mask to etch the sacrificial material layer 102, and before the sacrificial layer 211 is formed, the barrier layer 212 is also used as a mask to etch the gate material film 218 to form the gate material layer 219, and the sacrificial layer 211 and the gate material layer 219 are formed to share one mask, so that the forming efficiency of the semiconductor structure is improved, and the process cost for forming the semiconductor structure is reduced.
Correspondingly, the embodiment of the invention also provides a semiconductor structure. Referring to fig. 19, a schematic structural diagram of an embodiment of a semiconductor structure of the present invention is shown.
The semiconductor structure includes: a substrate 300; a first doped layer 301 on the substrate 300; a semiconductor channel pillar 307 separated on the first doped layer 301; a work function layer 308 on a portion of the sidewall of the semiconductor channel pillar 307 near the top surface; the sacrificial layer 311 is positioned on the side part of the semiconductor channel column 307, the sacrificial layer 311 covers part of the side wall of the semiconductor channel column 307, and the sacrificial layer 311 exposes the first doping layer 301 far away from the semiconductor channel column 307; and a work function layer 308 on the sacrificial layer 311 and on the sidewall of the semiconductor channel pillar 307 higher than the sacrificial layer 311.
In the semiconductor structure provided by the embodiment of the invention, the sacrificial layer 311 is formed by etching the sacrificial material layer, the sacrificial material layer is formed on the top surface of the first doped layer 301, the top surface of the first doped layer 301 is a plane, the corresponding process window for forming the sacrificial material layer is larger, the thickness of the sacrificial material layer is easy to accurately control, and the uniformity of the thickness of the sacrificial material layer is higher. The sacrificial material layer is etched to form the sacrificial layer 311, the thickness of the corresponding sacrificial layer 311 is relatively accurate, and the thickness uniformity of the sacrificial layer 311 is relatively high. After the sacrificial layer 311 is subsequently removed, an isolation groove is formed between the work function layer 308 and the substrate 300, the size of the isolation groove meets the process requirement in the normal direction of the surface of the substrate 300, and the uniformity of the size of each isolation groove is high, so that the thickness of the isolation layer formed in the isolation groove meets the process requirement, the uniformity of the thickness of the isolation layer is high, the uniformity of the electrical isolation capability of the isolation layer is high, and the improvement of the electrical performance and the performance uniformity of the semiconductor structure is facilitated.
In addition, the substrate generally includes a device sparse region and a device dense region, the density of the semiconductor channel pillars 307 in the device sparse region is lower than the density of the semiconductor channel pillars 307 in the device dense region, the number of the semiconductor channel pillars 307 is multiple, accordingly, in the normal direction of the surface of the substrate 300, the size of the semiconductor channel pillars 307 covered by the sacrificial layer 311 is the same, correspondingly, the size of the semiconductor channel pillars 307 covering the device sparse region and the device dense region by the subsequently formed isolation layer is the same, the size uniformity of the semiconductor channel pillars 307 in the device sparse region and the device dense region serving as the channel region is higher, and when the semiconductor structure works, the uniformity of the conduction current in the channel in the device sparse region and the device dense region is higher, which is beneficial to improving the electrical performance of the semiconductor structure.
In this embodiment, the semiconductor structure is a vertical all-around gate structure (VGAA). The substrate 300 provides a process platform for subsequently forming semiconductor structures.
In this embodiment, the substrate 300 is a silicon substrate. In other embodiments, the substrate material can also be germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
The first doped layer 301 and the second doped layer formed subsequently together serve as a source of the semiconductor structure, and when the semiconductor structure operates, the source provides stress for the channel to increase the mobility rate of carriers in the channel.
In this embodiment, the semiconductor structure is a PMOS transistor. In other embodiments, the semiconductor structure is an NMOS transistor.
The semiconductor channel column 307 functions as a channel when the semiconductor structure is in operation.
In this embodiment, the material of the semiconductor channel pillar 307 is silicon. In other embodiments, the material of the semiconductor channel pillar may also be germanium, silicon carbide, gallium arsenide, or gallium indium arsenide.
The sacrificial layer 311 is formed by etching a sacrificial material layer formed using a selective epitaxial growth process. The selective epitaxial growth process can precisely control the formation thickness of the sacrificial material layer, and thus the thickness of the sacrificial layer 311. The sacrificial material layer obtained by the selective epitaxial growth process has high purity and few defects, the formation quality of the sacrificial material layer is favorably improved, the purity and the defects of the corresponding sacrificial layer are few, the formation quality of the sacrificial layer 311 is high, and the residue of the sacrificial layer 311 is not easy to exist in the corresponding subsequent step of removing the sacrificial layer 311.
In the subsequent step of removing the sacrificial layer 311, the etching selectivity of the sacrificial layer 311 and the first doped layer 301 is not too small. The etching selection ratio is too small, so that the first doping layer 301 is easily damaged in the step of removing the sacrificial layer 311, and when the semiconductor structure works, the first doping layer 301 is not easy to provide sufficient stress for the semiconductor channel column 307, so that the migration rate of carriers in the semiconductor channel column 307 is not good. In this embodiment, in the subsequent step of removing the sacrificial layer 311, the etching selectivity ratio between the sacrificial layer 311 and the first doped layer 301 is greater than 10.
Specifically, the material of the sacrificial layer 311 includes silicon germanium. In this embodiment, the material of the sacrificial layer 311 includes silicon germanium.
Note that the sacrificial layer 311 is not too thick nor too thin. If the sacrificial layer 311 is too thick, the sacrificial layer 311 is subsequently removed to form an isolation trench, the size of the isolation trench on the normal line of the surface of the substrate 300 is too large, and the isolation layer subsequently formed in the isolation trench is too thick, so that the size of the semiconductor structure in the normal line direction of the surface of the substrate 300 is too large, the integration level of the semiconductor structure in the normal line direction of the surface of the substrate 300 is poor, so that the power consumption of the semiconductor structure is high, and if the sacrificial layer 311 is too thick, the thickness of the semiconductor channel column 307 covered by the corresponding subsequently formed isolation layer is large, the length of the channel is small, and the short channel effect is likely to be serious. If the sacrificial layer 311 is too thin, the size of the subsequently formed isolation trench on the normal line of the substrate 300 is too small, and in the subsequent step of forming the isolation layer in the isolation trench, the isolation layer is not easily filled in the isolation trench, a void (void) is easily present in the isolation layer, the formation quality of the corresponding isolation layer is poor, and the isolation layer cannot well electrically isolate the first doping layer 301 and the subsequently formed gate structure. In this embodiment, the thickness of the sacrificial layer 311 is 3 nm to 8 nm.
The work function layer 308 is used to adjust the threshold voltage of the semiconductor structure during operation of the semiconductor structure.
In this embodiment, the semiconductor structure is a PMOS, and correspondingly, the material of the work function layer 308 includes one or more of titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride, and tantalum carbide. In other embodiments, the semiconductor structure is an NMOS, and accordingly, the material of the work function layer includes one or more of titanium aluminide, tantalum carbide, aluminum, and titanium carbide.
Note that the work function layer 308 is also located on top of the semiconductor channel column 307.
The semiconductor structure further includes: and a gate dielectric layer 309 between the sacrificial layer 311 and the work function layer 308, and between the semiconductor channel column 307 and the work function layer 308.
The gate dielectric layer 309 is used to electrically isolate the semiconductor channel pillar 307 from subsequently formed gate structures.
The gate dielectric layer 309 is made of a high-k dielectric material. Wherein, the high-k dielectric material is a dielectric material with a relative dielectric constant larger than that of silicon oxide.
In this embodiment, the gate dielectricThe material of layer 309 is HfO2. In other embodiments, the material of the gate dielectric layer may also be selected from ZrO2HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3One or more of them.
The semiconductor structure further includes: and a protection layer 310 on the sacrificial layer 311 and on the sidewall of the work function layer 308.
Subsequently, the sacrificial layer 311 is removed to form an isolation trench, and an isolation layer is formed in the isolation trench, where the step of forming the isolation layer includes: forming a barrier material layer on the substrate 300 where the protective layer 310 is exposed; and etching back the partial thickness of the isolation material layer, wherein the rest isolation material layer in the isolation groove is used as an isolation layer. The protective layer protects the work function layer 302 on the sidewalls of the semiconductor trench column 307 from damage during the step of back etching a portion of the thickness of the isolation material layer.
In this embodiment, the material of the protection layer 310 includes: one or more of SiON, SiBCN, SiCN, carbon doped SiN, and oxygen doped SiN.
Note that, the lateral dimension of the protection layer 310 is not too large nor too small, taking the direction perpendicular to the sidewall of the semiconductor channel pillar 307 as the lateral direction. If the lateral dimension of the protection layer 310 is too large, it may take too much process time and material to form the protection layer 310. If the lateral dimension of the protection layer 310 is too small, the protection layer 310 is easily removed by etching in the step of etching the sacrificial material layer to form the sacrificial layer 311, and the protection layer 310 cannot well protect the work function layer 308. In the present embodiment, the lateral dimension of the passivation layer 310 is 2 nm to 8 nm.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (20)

1. A method of forming a semiconductor structure, comprising:
providing a base, wherein the base comprises a substrate and a first doping layer positioned on the substrate;
forming a sacrificial material layer on the first doping layer;
forming a dielectric material layer on the sacrificial material layer;
forming a semiconductor channel column penetrating through the dielectric material layer and the sacrificial material layer and connected with the first doping layer;
after the semiconductor channel column is formed, removing the dielectric material layer;
after removing the dielectric material layer, forming a work function layer on the side wall of the semiconductor channel column and the sacrificial material layer;
after the work function layer is formed, etching the sacrificial material layer far away from the semiconductor channel column, and taking the remaining sacrificial material layer close to the semiconductor channel column as a sacrificial layer;
removing the sacrificial layer, and forming an isolation groove between the work function layer and the substrate;
and forming an isolation layer in the isolation groove.
2. The method of claim 1, wherein in the step of forming the sacrificial material layer on the first doped layer, the sacrificial material layer has a thickness of 3 nm to 8 nm.
3. The method of forming a semiconductor structure according to claim 1, wherein in the step of removing the sacrificial layer, an etch selectivity ratio of the sacrificial layer to the first doped layer is greater than 10.
4. The method of claim 1 or 3, wherein the material of the sacrificial material layer comprises silicon germanium.
5. The method of forming a semiconductor structure of claim 1, wherein the sacrificial layer is removed using a wet etch process.
6. The method of claim 1, wherein a selective epitaxial growth process is used to form a layer of sacrificial material on the first doped layer.
7. The method of forming a semiconductor structure of claim 1, further comprising: after the work function layer is formed and before the sacrificial layer is formed, a protective layer is formed on the side wall of the semiconductor channel column;
the method for forming the semiconductor structure further comprises the following steps: and removing the protective layer after forming the isolation layer in the isolation groove.
8. The method of forming a semiconductor structure of claim 7, wherein a material of the protective layer comprises: one or more of SiON, SiBCN, SiCN, carbon doped SiN, and oxygen doped SiN.
9. The method of claim 7, wherein the lateral direction is perpendicular to the sidewall of the semiconductor channel pillar;
in the step of forming the protective layer on the sidewall of the semiconductor channel pillar, a lateral dimension of the protective layer is 2 nm to 8 nm.
10. The method of forming a semiconductor structure of claim 7, wherein etching the layer of sacrificial material to form a sacrificial layer comprises: forming a shielding layer covering the protective layer and the semiconductor channel column; etching the sacrificial material layer by taking the shielding layer as a mask to form the sacrificial layer;
the method for forming the semiconductor structure further comprises the following steps: and after the sacrificial layer is formed, removing the shielding layer.
11. The method of forming a semiconductor structure of claim 1, wherein the step of forming an isolation layer in the isolation trench comprises: forming an isolation material layer on the substrate exposed out of the semiconductor channel column, wherein the isolation material layer covers the top of the semiconductor channel column; and etching back the isolation material layer with partial thickness, wherein the rest isolation material layer is used as an isolation layer.
12. The method of claim 11, wherein the layer of spacer material is formed using a flowable chemical vapor deposition process.
13. The method of forming a semiconductor structure of claim 1, further comprising: forming a gate material layer on the work function layer after forming the isolation layer;
removing part of the thickness of the gate material layer to expose the top of the semiconductor channel column, wherein the rest gate material layer is used as a gate layer;
and removing the work function layer exposing the grid layer, wherein the grid layer and the rest work function layer are used as a grid structure.
14. The method of forming a semiconductor structure of claim 1, comprising: before the semiconductor channel column is formed, etching the dielectric material layer and the sacrificial material layer to form an opening exposing the first doping layer;
the semiconductor channel pillar is formed in the opening.
15. The method of forming a semiconductor structure of claim 1, further comprising:
after the work function layer is formed and before the sacrificial layer is formed, a grid material film is formed on the semiconductor channel column and the sacrificial material layer exposed out of the semiconductor channel column; forming a protective layer on a sidewall of the gate material film; forming a shielding layer covering the top of the protective layer and the gate material film on the top of the semiconductor channel column; etching the gate material film by taking the top of the sacrificial material layer as an etching stop position and the shielding layer as a mask to form a gate material layer exposing the sacrificial material layer;
the step of forming the sacrificial layer includes: and etching the sacrificial material layer by taking the shielding layer as a mask to form the sacrificial layer.
16. A semiconductor structure, comprising:
a substrate;
the first doping layer is positioned on the substrate;
the semiconductor channel column is separated on the first doping layer;
the sacrificial layer is positioned on the side part of the semiconductor channel column, covers part of the side wall of the semiconductor channel column, and is exposed out of the first doping layer far away from the semiconductor channel column;
and the work function layer is positioned on the sacrificial layer and on the side wall of the semiconductor channel column higher than the sacrificial layer.
17. The semiconductor structure of claim 16, wherein the sacrificial layer has a dimension in a direction normal to the surface of the substrate of 3 nm to 8 nm.
18. The semiconductor structure of claim 16, in which a material of the sacrificial layer comprises silicon germanium.
19. The semiconductor structure of claim 16, wherein the semiconductor structure further comprises: and the protective layer is positioned on the sacrificial layer and positioned on the side wall of the semiconductor channel column.
20. The semiconductor structure of claim 19, wherein a lateral dimension of the protective layer is 2 nm to 8 nm, taken in a lateral direction perpendicular to a sidewall of the semiconductor channel pillar.
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