CN113823643B - Array substrate mother board, array substrate, display panel and display device - Google Patents
Array substrate mother board, array substrate, display panel and display device Download PDFInfo
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- CN113823643B CN113823643B CN202111095061.7A CN202111095061A CN113823643B CN 113823643 B CN113823643 B CN 113823643B CN 202111095061 A CN202111095061 A CN 202111095061A CN 113823643 B CN113823643 B CN 113823643B
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- 239000000758 substrate Substances 0.000 title claims abstract description 163
- 238000001514 detection method Methods 0.000 claims abstract description 180
- 238000007689 inspection Methods 0.000 claims description 33
- 230000005611 electricity Effects 0.000 abstract description 26
- 230000003068 static effect Effects 0.000 abstract description 26
- 238000000034 method Methods 0.000 description 12
- 238000002360 preparation method Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 7
- 230000007547 defect Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 230000001627 detrimental effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
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Abstract
The invention relates to an array substrate motherboard, an array substrate, a display panel and a display device. Cutting lines are arranged on the array substrate mother board and divide the array substrate mother board into a plurality of panel areas; the array substrate motherboard is also provided with a plurality of array detection wires, each array wire is arranged at a main line part in each panel area and a cross line connecting part for connecting the main line parts of adjacent panel areas together; the main line part is connected with an electrical terminal used for array detection in the panel area; the overline connecting part spans the cutting line between the adjacent panel areas; the width of the cross wire connecting part of each array detection wire is smaller than that of the main wire part of the array detection wire; and/or the interval of the cross wire connecting parts of any two adjacent array detection wires is larger than the interval of the main wire parts of the two adjacent array detection wires. The array substrate motherboard can enable the fracture of the array detection wiring at the edge of each array substrate to be difficult to generate static electricity.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate mother board, an array substrate obtained by cutting an array substrate, a display panel comprising the array substrate and a display device comprising the display panel.
Background
The preparation of an Array (Array) substrate is an important step in the preparation process of a display panel. After the Array process is completed, a structure such as a thin film transistor formed on a motherboard of the Array substrate needs to be inspected and tested, which is generally called Array Test (Array Test). By array detection, bad detection can be performed in the early stage, and the problem of continuously preparing products in the subsequent process is avoided.
Array inspection generally forms an array inspection trace (a/T trace) on a motherboard of an array substrate, and the array inspection trace is further connected with an array inspection terminal (AT pad) and is also connected with an electrical terminal (ET pad) in each panel area on the motherboard of the array substrate, and the electrical terminal is connected with a gate line and a data line in the panel area, so as to realize connection of the array inspection terminal and sub-pixels in the panel area, and inspect the structure of the sub-pixels formed in the panel area.
Each panel region on the array substrate motherboard is cut into array substrates along Cutting lines (Cutting lines). According to different cutting modes, the array substrate mother board can be divided into two types, wherein the first type is the array substrate mother board with zero cutting (only one cutting line is arranged between adjacent panel areas, the two cutting lines are connected, and no space exists between the two cutting lines), and the second type is the array substrate mother board with non-zero cutting (two cutting lines are arranged between the adjacent panel areas, and the two cutting lines are separated, and the space exists between the two cutting lines).
For the array substrate motherboard in the zero cutting mode, the array detection wires are arranged along the cutting lines between the adjacent panel areas, the array detection wires can cross the cutting lines between the adjacent panel areas, after the panel areas are cut to form the array substrate, the edges of the array substrate are provided with exposed fractures of the array detection wires, static electricity is easily formed at the fractures, and the static electricity is conducted into the array substrate, so that the array substrate and the display panel are poor or damaged.
For the array substrate motherboard in a non-zero cutting mode, the array detection wires are arranged along the cutting area between two cutting lines of the adjacent panel areas, the array detection wires extend out of connecting wires (generally ITO wires) towards the panel areas, and the connecting wires extend into the panel areas and are connected with the electrical terminals of the panel areas. In the case of each panel region, the number of electrical terminals disposed therein is large, and in the case of the panel region having an insufficient width, the plurality of electrical terminals are generally arranged in a plurality of rows, and are arranged compactly and densely, and the pitch between adjacent electrical terminals is small. In such a case, the width of the ITO trace for connecting the electrical terminal and the array detection trace must be set to be thin to achieve connection with a plurality of electrical terminals, or else, cannot be simultaneously connected with the plurality of electrical terminals. This presents the problem that thinner ITO wiring leads to a greater resistance between the array sense traces and the electrical terminals, which is detrimental to array sensing. Or, in another case, the width of the panel area is set larger, that is, the panel area has a larger frame, so that the distance between adjacent electrical terminals can be increased, the ITO wiring connecting the array detection wiring and the electrical terminals is ensured to have a sufficient width, but the frame width of the array substrate formed by cutting and the further prepared display panel is too large.
Disclosure of Invention
The invention provides an array substrate motherboard, an array substrate, a display panel and a display device, which are used for solving the technical problems that in the prior art, a fracture of an array detection wiring occurs at the edge of the array substrate, the array detection wiring is easy to cause bad and damage due to static electricity, and the width of the array detection wiring needs to be set thinner so as to be unfavorable for array detection or cause a larger frame width.
The invention provides an array substrate motherboard, which is provided with cutting lines, wherein the cutting lines divide the array substrate motherboard into a plurality of panel areas; the array substrate motherboard is also provided with a plurality of array detection wires, each array wire is arranged at a main line part in each panel area and a cross line connecting part for connecting the main line parts of adjacent panel areas together; the main line part is connected with an electrical terminal used for array detection in the panel area; the overline connecting part spans a cutting line between adjacent panel areas; the width of the cross wire connecting part of each array detection wire is smaller than that of the main wire part of the array detection wire; and/or the interval of the cross wire connecting parts of any two adjacent array detection wires is larger than the interval of the main wire parts of the two adjacent array detection wires.
The width of the cross wire connecting part of each array detection wire is 20-40 micrometers, and the width of the main wire part is 30-60 micrometers.
The distance between the cross-line connecting parts of any two adjacent array detection wires is 20-40 micrometers, and the distance between the main line parts is 10-30 micrometers.
The width of the jumper connection part of each array detection wire is smaller than the interval between the jumper connection parts of any two adjacent array detection wires.
The width of the cross wire connecting part of each array detection wire is 30 micrometers, and the width of the main wire part is 50 micrometers; the interval between the cross-line connection parts of any two adjacent array detection wires is 35 micrometers, and the interval between the main line parts is 25 micrometers.
The invention provides another array substrate motherboard, which is provided with a cutting line area, wherein the cutting line area divides the array substrate motherboard into a plurality of panel areas, and the cutting line area is provided with an array detection wiring; each panel region comprises a display region and a wiring region positioned at one side of the display region, wherein the wiring region is provided with a flexible circuit board and a plurality of electrical terminals for array detection; the plurality of electrical terminals for array detection are connected with the array detection wiring; at least part of the plurality of electrical terminals for array detection are first electrical terminals; the first electrical terminal is connected with the flexible circuit board and is connected with the array detection wire through a first connecting wire formed between the flexible circuit board and the array detection wire.
The second electrical terminals are connected through a second connecting wire formed between the electrical terminals and the array detection wires.
The width of the non-overlapping area between the projection of each second electrical terminal on the array detection wire and the projection of other second electrical terminals on the array detection wire is larger than a first set value.
Among the plurality of electrical terminals for array detection, the electrical terminal with the width of the non-overlapping area of the projection of the array detection wire and the projection of each second electrical terminal on the array detection wire being larger than the first set value is the second electrical terminal, and the electrical terminal with the width being smaller than the first set value is the first electrical terminal.
Wherein the plurality of electrical terminals for array detection are arranged in n rows in the wiring area, and n is more than or equal to 1; one of the n rows of electrical terminals is a third electrical terminal, and the third electrical terminal is provided with an outward extension line; a third connecting wire is formed between the extension wire of the third electrical terminal and the array detection wire.
The array substrate provided by the invention is formed by cutting the array substrate mother board.
The display panel provided by the invention comprises the array substrate.
The display device provided by the invention comprises the display panel.
Compared with the prior art, the array substrate motherboard, the array substrate, the display panel and the display device provided by the embodiment of the invention have the following advantages:
according to the array substrate motherboard provided by the embodiment of the invention, each array detection trace comprises the main line part and the cross-line connecting part, the width of the cross-line connecting part of each array detection trace is smaller than that of the main line part, and/or the distance between the cross-line connecting parts of any two adjacent array detection traces is larger than that of the main line part, so that the width of the array detection trace is reduced at the cross-cutting line position of the edge of a panel region, smaller than that of the main line part of the array detection trace in the panel region, and/or the distance between the adjacent array detection traces is increased and larger than that of the main line part of the adjacent array detection trace in the panel region, and after a plurality of panel regions on the array substrate motherboard are cut into a plurality of array substrates along cutting lines, the arrangement can enable the fracture of the array detection trace at the edge of each array substrate to be smaller and/or the distance between the adjacent array detection trace fracture to be larger, static electricity is less likely to be generated, and therefore the probability of poor or damaged of the array substrate caused by static electricity conduction into the array substrate is reduced.
In another array substrate motherboard provided by the embodiment of the invention, at least part of the plurality of electrical terminals for array detection are first electrical terminals; the first electrical terminals are connected to the flexible circuit board, and are connected with the array detection wires through the first connecting wires formed between the flexible circuit board and the array detection wires, so that all the electrical terminals are not required to be directly connected with the array detection wires through the ITO wires, the problem that the width of the ITO wires is required to be thinner due to insufficient wire space, the resistance of the ITO wires is higher, and the array detection is affected is avoided, or the problem that the width of a frame is required to be larger in order to increase the wire space is solved.
According to the array substrate provided by the embodiment of the invention, the array substrate mother board is cut, the fractures of the array detection wires at the edge of the obtained first type of array substrate are smaller and/or the intervals between the adjacent array detection wire fractures are larger, so that static electricity is less likely to be generated, and the probability of poor or damage of the array substrate caused by the fact that the static electricity is conducted into the array substrate is reduced; the obtained second array substrate improves the problem of array detection effect due to higher resistance impression when array detection is performed, and under the condition that the array detection effect is well ensured, a panel area on a motherboard of the array substrate with bad performance can be well identified, so that the yield of the array substrate obtained by cutting is higher, or a larger frame is not required to be arranged when array detection is performed, so that the frame width of the array substrate obtained by cutting is smaller.
The display panel provided by the embodiment of the invention comprises the array substrate, static electricity is not easy to generate at the fracture of the array detection wiring at the edge of the display panel, and the probability of poor or damage caused by the fact that the static electricity is conducted into the display panel is reduced. Or, the defects generated in the preparation process can be identified in the early stage, so that the display panel has higher yield, or a larger frame is not required to be arranged in the preparation process, and the width of the frame of the display panel is smaller.
The display device provided by the embodiment of the invention comprises the display panel, static electricity is not easy to generate at the fracture of the array detection wiring at the edge of the display device, and the probability of poor or damage caused by the conduction of the static electricity into the display device is reduced. Or, the defects generated in the preparation process can be identified in the early stage, so that the display panel has higher yield, or a larger frame is not required to be arranged in the preparation process, and the width of the frame of the display panel is smaller.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, and it will be obvious to a person skilled in the art that other drawings can be obtained from these drawings without inventive effort.
Fig. 1 is a schematic structural diagram of a motherboard of an array substrate according to embodiments 1 to 3 of the present invention;
FIG. 2 is a schematic diagram of a portion of an array inspection trace in the motherboard of the array substrate shown in FIG. 1;
fig. 3 is a schematic structural diagram of a motherboard of an array substrate according to embodiment 4 of the present invention;
FIG. 4 is a schematic view of a structure of a wiring area in a panel area of the motherboard of the array substrate shown in FIG. 3;
FIG. 5 is a schematic view of another structure of a wiring area in a panel area of the motherboard of the array substrate shown in FIG. 3;
FIG. 6 is a schematic diagram illustrating a connection manner between the array inspection trace and the second electrical terminal in the motherboard of the array substrate shown in FIG. 3;
FIG. 7 is a schematic diagram illustrating a connection manner between the array inspection trace and the first electrical terminal in the motherboard of the array substrate shown in FIG. 3;
FIG. 8 is a schematic diagram illustrating a connection manner between the array inspection trace and the electrical terminal in the motherboard of the array substrate shown in FIG. 3;
fig. 9 is a schematic diagram of a connection manner between an array inspection trace and a third electrical terminal in the motherboard of an array substrate according to embodiment 5 of the present invention.
In the figure:
10-panel area; 101-a display area; 102-a wiring region;
11-electrical terminals; 11 a-a first electrical terminal; 11 b-a second electrical terminal; 11 c-a third electrical terminal; 110-extension wire 12-flexible circuit board;
13-a driving circuit;
20-array detection wiring; 201-a main line portion; 202-an overline connection;
21-a first connection line;
22-a second connecting line;
23-a third connecting line;
CL-cutting lines; CA-cut line region.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Embodiments of an array substrate motherboard, an array substrate, a display panel and a display device provided by the invention are described below with reference to the accompanying drawings.
(1) Example 1 of array substrate motherboard
Referring to fig. 1, the array substrate motherboard provided in this embodiment is provided with a cutting line CL dividing the array substrate motherboard into a plurality of panel areas 10. Adjacent panel sections 10 meet at cut line CL with no gap therebetween. After cutting along the cutting line CL, each panel region 10 becomes a single array substrate. Each panel region 10 includes a display region 101 (Active area, abbreviated as AA region) and a wiring region 102, a plurality of pixel units each including a plurality of sub-pixels are disposed in the display region 101; the wiring region 102 is provided with a driving circuit, a flexible circuit board, and the like, and is also provided with a plurality of electrical terminals.
Referring to fig. 1 and 2, a plurality of array detecting wires 20 are further formed on the motherboard of the array substrate, each array detecting wire 20 has a plurality of intersections with the cutting line CL, each panel region 10 has at least one corresponding intersection, and the array detecting wires 20 extend from the corresponding intersection of each panel region 10 into the panel region 10 and are connected with the electrical terminals for array detection in the panel region 10. In other words, each array detection trace 20 is provided in the main line portion 201 in each panel region 10 and the flying lead connection portion 202 that connects the main line portions 201 of adjacent panel regions 10 together; the main line portion 201 is connected to an electrical terminal for performing array detection in the panel region 10; the overline connection 202 spans the cut line CL between adjacent panel areas 10. It should be noted that the number of the electrical terminals in the panel area 10 is greater, and the greater number of the electrical terminals may have different applications, and the electrical terminals in the embodiment are all electrical terminals for array detection, and do not include electrical terminals for other applications and not connected to the array detection trace 20.
With continued reference to fig. 2, the number of array sense traces 20 is a plurality. Specifically, the plurality of array detection traces 20 are disposed at intervals along the same direction, for example, in fig. 2, the plurality of array detection traces 20 are substantially parallel to each other.
In the present embodiment, the width of the flying lead connection portion 202 of each array detection trace 20 is smaller than the width of the main line portion 201 thereof. In the conventional array substrate motherboard, the width of the array detection trace 20 at the edge of the panel region 10 crossing the cutting line CL is consistent with the width in the panel region 10, and the width of the array detection trace 20 is not intentionally reduced at the edge of the panel region 10 crossing the cutting line CL; compared with the prior array substrate motherboard, in this embodiment, the width of the array detection trace 20 is reduced, particularly at the cross-cutting line CL of the edge of the panel area 10, smaller than the width of the main line portion 201 of the array detection trace 20 in the panel area 10, so that after the plurality of panel areas 10 on the array substrate motherboard are cut into a plurality of array substrates along the cutting line CL, the fracture of the array detection trace 20 at the edge of each array substrate is smaller, static electricity is less likely to be generated, and the probability of poor or damaged array substrates caused by static electricity conduction into the array substrates is reduced.
Specifically, in the present embodiment, the width of the jumper connection portion 202 of each array detection trace 20 is 20 to 40 micrometers, and the width of the main line portion 201 is 30 to 60 micrometers. Further, the width of the jumper connection 202 of each array detection trace 20 is 30 micrometers, and the width of the main line 201 is 50 micrometers.
In this embodiment, the width of the jumper connection 202 of each array detection trace 20 is smaller than the pitch of the jumper connection 202 of any two adjacent array detection traces 20. After each panel area 10 is cut into the array substrate, the probability of static electricity generated between the fractures at the edge of the array substrate due to too short distance between the fractures and too dense fractures of different array detection wires 20 is reduced, so that the array substrate is better ensured not to be bad or damaged due to static electricity.
(2) Example 2 of array substrate motherboard
As in embodiment 1, the array substrate motherboard in this embodiment is also provided with a cutting line CL, which divides the array substrate motherboard into a plurality of panel areas 10, and the array substrate motherboard is also provided with an array detection trace 20, and the cutting line CL, the panel areas 10, the array detection trace 20, and the like are the same as in embodiment 1, and are not described here again. Only the differences between the array substrate mother board in this embodiment and embodiment 1 described above will be described in detail.
In this embodiment, as shown in fig. 2, the pitch of the jumper connection portions 202 of any two adjacent array detection wires 20 is larger than the pitch of the main wire portions 201 of the two adjacent array detection wires 20.
In the existing array substrate motherboard, the distance between adjacent array detection wires 20 at the edge of the panel region 10 and the distance between adjacent array detection wires 20 in the panel region 10 are consistent, and the distance between adjacent array detection wires 20 at the edge of the panel region 10 and the distance between adjacent array detection wires in the panel region is not intentionally increased; compared with the prior array substrate motherboard, in this embodiment, particularly, the spacing between adjacent array detection wires 20 at the cross-cut line CL of the edge of the panel area 10 is increased to be larger than the spacing between the main line portions 201 of the adjacent array detection wires 20 in the panel area 10, so that after the plurality of panel areas 10 on the array substrate motherboard are cut into a plurality of array substrates along the cut line CL, the spacing between the fractures of the adjacent array detection wires 20 at the edge of each array substrate is made larger, static electricity is less likely to be generated, and the probability of poor or damaged array substrates caused by static electricity conduction into the array substrates is reduced.
Specifically, the pitch of the jumper connection portions 202 of any two adjacent array detection traces 20 is 20 to 40 micrometers, and the pitch of the main line portions 201 is 10 to 30 micrometers. Further, the pitch of the jumper connection portions 202 of any two adjacent array detection traces 20 is 35 micrometers, and the pitch of the main line portions 201 is 25 micrometers.
Other parts not mentioned in this embodiment are the same as those in embodiment 1 described above, and are not described here again.
(3) Example 3 of array substrate motherboard
As in the foregoing embodiment 1 and embodiment 2, the array substrate motherboard in this embodiment is also provided with a cutting line CL, which divides the array substrate motherboard into a plurality of panel areas 10, and the array substrate motherboard is also provided with an array detection trace 20, and the cutting line CL, the panel areas 10, the array detection trace 20, and the like are the same as in the foregoing embodiment 1, and are not described again here. Only the differences between the array substrate mother board in this embodiment and embodiment 1 described above will be described in detail.
In the present embodiment, as shown in fig. 2, the width of the flying lead connection portion 202 of each array detection trace 20 is smaller than the width of the main line portion 201; and, the interval between the cross wire connection portions 202 of any two adjacent array detection wires 20 is larger than the interval between the main wire portions 201 of the two adjacent array detection wires 20.
In the conventional array substrate motherboard, the width of the array detection trace 20 at the edge of the panel region 10 crossing the cutting line CL is consistent with the width in the panel region 10, the spacing between adjacent array detection traces 20 at the edge of the panel region 10 crossing the cutting line CL is also consistent with the spacing in the panel region 10, and the width of the array detection trace 20 is not intentionally reduced at the edge of the panel region 10 crossing the cutting line CL, so that the spacing between adjacent array detection traces 20 is enlarged; compared with the conventional array substrate motherboard, in this embodiment, the width of the array detecting trace 20 is reduced, particularly at the cross-cut line CL of the edge of the panel area 10, smaller than the width of the main line portion 201 of the array detecting trace 20 in the panel area 10, and the pitch of the adjacent array detecting trace 20 is increased, larger than the pitch of the main line portion 201 of the adjacent array detecting trace 20 in the panel area 10, so that after the plurality of panel areas 10 on the array substrate motherboard are cut into a plurality of array substrates along the cut line CL, the fracture of the array detecting trace 20 at the edge of each array substrate is made smaller, and the pitch between the fracture of the adjacent array detecting trace 20 is made larger, so that static electricity is less likely to be generated, thereby reducing the probability of failure or damage of the array substrate caused by static electricity conduction into the array substrate.
Specifically, the width of the jumper connection portion 202 of each array detection trace 20 is 20-40 micrometers, and the width of the main line portion 201 is 30-60 micrometers; the pitch of the cross-line connection parts 202 of any two adjacent array detection wires 20 is 20-40 micrometers, and the pitch of the main line parts 201 is 10-30 micrometers. Further, the width of the jumper connection portion 202 of each array detection trace 20 is 30 micrometers, and the width of the main line portion 201 is 50 micrometers; the pitch of the cross-line connection portions 202 of any two adjacent array detection wires 20 is 35 micrometers, and the pitch of the main line portions 201 is 25 micrometers.
In summary, in the array substrate motherboard according to the embodiments 1 to 3, each of the array detecting traces 20 includes the main line portion 201 and the cross-line connection portion 202, the width of the cross-line connection portion 202 of each of the array detecting traces 20 is smaller than the width of the main line portion 201, and/or the distance between the cross-line connection portions 202 of any two adjacent array detecting traces 20 is larger than the distance between the main line portions 201 of the adjacent array detecting traces 20, so that the width of the array detecting trace 20 is reduced, particularly at the cross-cut line CL at the edge of the panel region 10, smaller than the width of the main line portion 201 of the array detecting trace 20 in the panel region 10, and/or the distance between the adjacent array detecting traces 20 is increased, larger than the distance between the main line portions 201 of the adjacent array detecting trace 20 in the panel region 10, so that after the plurality of panel regions 10 on the array substrate motherboard are cut into a plurality of array substrates along the cut line CL, the edge of each array detecting trace 20 is smaller and/or the distance between the adjacent array detecting traces 20 is smaller, and the electrostatic conduction probability of the array substrate is reduced, which is not likely to be caused by the electrostatic conduction of the array substrate.
(4) Example 4 of array substrate motherboard
As shown in fig. 3, the array substrate motherboard provided in this embodiment is provided with a scribe line area CA, which is an area between two scribe lines CL on the array substrate motherboard. The scribe line area CA divides the array substrate motherboard into a plurality of panel areas 10, and a gap, i.e., the scribe line area CA, is provided between adjacent panel areas 10. After cutting along the two cut lines CL at the edge of the cut line area CA, each panel area 10 becomes a single array substrate. The scribe line area CA is provided with array detection traces 20.
Each panel region 10 includes a display region 101 (Active area, referred to as AA region for short) and a wiring region 102 located on one side of the display region 101. A plurality of pixel units are disposed in the display area 101, each pixel unit including a plurality of sub-pixels. The wiring region 102 is provided with an electrical terminal 11 for array detection, a flexible circuit board 12, a driving circuit 13, and the like. Specific arrangement of the wiring area 102 as shown in fig. 4 and 5, fig. 4 and 5 show two arrangements of the wiring area 102, respectively, in the structure shown in fig. 4, the number of the flexible circuit boards 12 is two, the number of the driving circuits 13 is 2, and the driving circuits 13 and the flexible circuit boards 12 are arranged opposite to each other; in the structure shown in fig. 5, the number of flexible circuit boards 12 is 2, the number of driving circuits 13 is 4, and each flexible circuit board 12 is located between two driving circuits 13.
In the wiring area 102, the number of the electrical terminals 11 for array inspection is plural, and the plural electrical terminals 11 for array inspection are connected to the array inspection trace 20. It should be noted that, the number of the electrical terminals in the wiring area 102 of the panel area 10 is greater, and the electrical terminals may have different applications, and the electrical terminals 11 in this embodiment are all electrical terminals for array detection, and do not include electrical terminals for other applications and are not connected to the array detection trace 20.
As described in the background art section, in the wiring area of each panel area 10, the plurality of electrical terminals 11 are generally arranged in two rows due to the insufficient width, as shown in fig. 6, and in order to save the space of the wiring area 102, the plurality of electrical terminals 11 are arranged more compactly, and the space between the adjacent electrical terminals 11 is smaller. For example, in fig. 6, the width of each electrical terminal 11 is 700 micrometers, and the interval between adjacent electrical terminals 11 is 400 micrometers, it is conceivable that even in the case of the staggered arrangement of two rows of electrical terminals 11 in fig. 6, it is impossible to arrange ITO traces on all electrical terminals 11 of two rows, and all electrical terminals 11 are directly connected with the array detection trace 20.
In the present embodiment, referring to fig. 6, 7 and 8, at least some of the plurality of electrical terminals 11 for array detection are first electrical terminals 11a; the first electrical terminal 11a is connected to the flexible circuit board 12, and is connected to the array detection trace 20 through a first connection line 21 formed between the flexible circuit board 12 and the array detection trace 20. The electrical terminals 11 are connected to the flexible circuit board 12, and the connection between the electrical terminals 11 and the array detection wires 20 is realized through the first connecting wires 21, so that all the electrical terminals 11 are not required to be directly connected with the array detection wires 20 through the ITO wires, the problem that the array detection is affected due to the fact that the width of the ITO wires is required to be thinner due to insufficient wire space, or the problem that the width of the frame is required to be larger in order to increase the wire space is avoided.
Specifically, the plurality of electrical terminals 11 for array inspection may be all the first electrical terminals 11a, that is, all the electrical terminals 11 for array inspection are connected to the flexible circuit board 12 and connected to the array inspection trace 20 through the first connection line 21. Or, the plurality of electrical terminals 11 for array inspection, wherein a portion of the plurality of electrical terminals is a first electrical terminal 11a, and the portion of the first electrical terminal 11a is connected to the flexible circuit board 12 and is connected to the array inspection trace 20 through the first connection line 21. The other part is the second electrical terminal 11b, and the second electrical terminal 11b is connected through a second connection line 22 formed between the second electrical terminal 11b and the array detection trace 20, as shown in fig. 6 and 7, the second connection line 22 may be specifically an ITO trace, and the ITO trace may be formed synchronously in a process of preparing an ITO electrode in the display region 101 on the motherboard of the array substrate, without adding a process. It will be appreciated that, since part of the electrical terminals 11 are the first electrical terminals 11a, the connection with the array detection trace 20 does not occupy the space around the electrical terminals 11, and the space for disposing the second connection lines 22 is increased for the second electrical terminals 11b, the width of the second connection lines 22 connecting each of the second electrical terminals 11b and the array detection trace 20 can be set to a desired suitable width.
Referring to fig. 6, in the present embodiment, the width of the non-overlapping area between the projection of each second electrical terminal 11b on the array detection trace 20 and the projection of the other second electrical terminals 11b on the array detection trace 20 is larger than the first set value. The first setting value may be set according to the need, specifically, if the width of the non-overlapping area is greater than the first setting value, then there is enough space and width (the width of the second connection line may be combined with the interval between the electrical terminals 11, for example, the width of the second connection line is 750 micrometers, the width of the non-overlapping area is 700 micrometers, and the interval between the electrical terminals 11 is 400 micrometers), and then the first setting value may be determined to be 700 micrometers, that is, the first setting value may be smaller than the width of the second connection line, specifically, the value smaller than the width of the second connection line does not exceed the interval between the electrical terminals 11). The purpose of the above arrangement is to ensure that there is a sufficient line width at each second electrical terminal 11b for the arrangement of the second connection lines 22. For the electrical terminal 11 overlapping with other second electrical terminals 11b and having a width of the non-overlapping area smaller than the first set value, it is indicated that there is not enough line width at the electrical terminal 11 for arranging the second connection line 22, so that the electrical terminal 11 cannot be used as the second electrical terminal 11b but can only be used as the first electrical terminal 11a, and is connected with the array detection trace 20 through the flexible circuit board 12 and the first connection line 21, so that the phenomenon that the second connection line 22 of the electrical terminal 11 overlaps with the second connection line 22 of other second electrical terminals 11b due to insufficient space for arranging the second connection line 22 is avoided when such electrical terminal 11 is used as the second electrical terminal 11 b.
Further, among the plurality of electrical terminals 11 for array inspection, the electrical terminal 11 with a width of a non-overlapping area between the projection of the array inspection trace 20 and the projection of each second electrical terminal 11b on the array inspection trace 20 being greater than the first set value is the second electrical terminal 11b, and the electrical terminal 11 with a width being smaller than the first set value is the first electrical terminal 11a. In this way, as long as the non-overlapping area of each electrical terminal 11 and the other second electrical terminals 11b is larger than the first set value, the electrical terminal 11 is used as the second electrical terminal 11b, so that the electrical terminal 11 and the array detection trace 20 are directly connected by the second connection line 22, and the other electrical terminals 11 which cannot meet the condition that the non-overlapping area is larger than the first set value are used as the first electrical terminals 11a, so that the electrical terminal 11 is connected with the array detection trace 20 through the flexible circuit board 12 and the first connection line 21. By the arrangement, the plurality of electrical terminals 11 for array detection are made to be the second electrical terminals 11b according with the width and space conditions of the second connecting wires 22, and the number and the duty ratio of the second electrical terminals 11b are increased as much as possible; the connection of the excessive electrical terminals 11 to the flexible circuit board 12 is avoided, so that more pins (Pin) are required to be added to the flexible circuit board 12, and the connection of the first connecting wires 21 remained on the array substrate after the panel area 10 is cut into the array substrate to the flexible circuit board 12 can be avoided. In particular, regarding the plurality of electrical terminals 11 for array inspection shown in fig. 6 and 7, which are arranged in two rows, the two rows of electrical terminals 11 are staggered, one electrical terminal 11 of any one row is located between two electrical terminals 11 of the other row, the two rows of electrical terminals 11 are in a staggered relationship, for the electrical terminals 11 of this case, the gap between adjacent electrical terminals 11 is insufficient to provide the second connection line 22, therefore, when one electrical terminal 11 of one row is connected with the array inspection trace 20 through the second connection line 22, there is a partial region overlapping electrical terminal 11 of the other row with the electrical terminal 11, because the width and the space of the non-overlapping region are insufficient, the electrical terminals 11 of the other row can only be connected to the flexible circuit board 12, and are connected with the array inspection trace 20 through the first connection line 21, and so on, in the case that the first electrical terminal 11a and the second electrical terminal 11b are formed at intervals as a whole, and in the case that all the other rows are the first electrical terminals 11a and the other electrical terminals 11b are the second electrical terminals 11b are arranged (the electrical terminals 11 of fig. 6 and the electrical terminals 11 of fig. 7 are used for the array inspection 11 are the actual electrical terminals 11 and the other electrical terminals 11b are arranged according to the above-mentioned electrical terminal 11 and the electrical terminal 11 detection principle, and the electrical terminals 11b are the electrical terminals 11 of the case shown in the electrical array 11 and the electrical terminals 11 are more preferred electrical terminals 11b are the electrical terminals 11 and the electrical array 11 and the electrical terminals 11 are used for the electrical device 11 and the electrical device 11).
(5) Example 5 of array substrate motherboard
In this embodiment, the array substrate motherboard is also provided with a cutting line area CA, the cutting line area CA divides the array substrate motherboard into a plurality of panel areas 10, the cutting line area CA is also provided with an array detection trace 20, and the structures and the arrangement of the cutting line area CA, the panel areas 10 and the array detection trace 20 are the same as those of the embodiment 4, which will not be described again here. Only the differences between the array substrate mother board in this embodiment and embodiment 4 are described in detail below.
In the present embodiment, as shown in fig. 9, a plurality of electrical terminals 11 for array inspection are arranged in n rows in the wiring area, n being equal to or greater than 1; the electrical terminals 11 located at the edge of one of the n rows of electrical terminals is a third electrical terminal 11c, and the third electrical terminal 11c has an outward extension line 110; a third connection line 23 is formed between the extension line 110 of the third electrical terminal 11c and the array detection trace 20.
In embodiment 4, if the non-overlapping area between the third electrical terminal 11c and the other second electrical terminals 11b is smaller than the first set value, that is, there is insufficient space and width for disposing the second connection line 22 at the third electrical terminal 11c, the third electrical terminal 11c can only serve as the first electrical terminal 11a and be connected to the flexible circuit board 12, and is connected to the array detection trace 20 through the first connection line 21. However, in the present embodiment, when the non-overlapping area between the third electrical terminal 11c and the other second electrical terminals 11b is smaller than the first set value, an extension line 110 is obtained by extending outwards, and the non-overlapping area between the extension line 110 and the other second electrical terminals 11b is larger than the first set value, and a connection line directly connected to the array detection trace 20 is provided with a sufficient width and space, which is called a third connection line 23, so that the direct connection between the third electrical terminal 11c and the array detection trace 20 is achieved through the extension line 110 and the third connection line 23. The third electrical terminal 11c which is originally only connected with the array detection wire 20 through the flexible circuit board 12 and the first connecting wire 21 is arranged in this way, so that the third electrical terminal 11 can be directly connected with the array detection wire 20 through the third connecting wire 23, and the number and the duty ratio of the electrical terminals 11 which are directly connected with the array detection wire 20 in the plurality of electrical terminals 11 for array detection are improved.
Specifically, the third connection line 23 may also be an ITO trace, which may be formed simultaneously in a process of preparing an ITO electrode in the display region 101 on the motherboard of the array substrate, without adding a process.
In summary, in the array substrate mother board provided in the embodiments 4 to 5, at least some of the electrical terminals 11 among the plurality of electrical terminals 11 for array inspection are the first electrical terminals 11a; the first electrical terminal 11a is connected to the flexible circuit board 12, and is connected with the array detection trace 20 through the first connecting wire 21 formed between the flexible circuit board 12 and the array detection trace 20, so that all the electrical terminals 11 are not required to be directly connected with the array detection trace 20 through the ITO traces, the problem that the width of the ITO trace caused by insufficient trace space must be set thinner to enable the resistance of the ITO trace to be higher, thereby influencing array detection is avoided, or the problem that the width of a frame must be set larger in order to increase trace space is avoided.
(6) Embodiments of array substrates
In this embodiment, the array substrate is cut from the array substrate motherboard described in the embodiment of the array substrate motherboard described above.
According to the array substrate obtained by cutting the array substrate mother board in embodiments 1 to 3, the breakage of the array detection wires 20 at the edge is smaller and/or the interval between the breakage of the adjacent array detection wires 20 is larger, so that static electricity is less likely to be generated, and the probability of poor or damaged array substrate caused by static electricity conduction into the array substrate is reduced.
According to the array substrate obtained by cutting according to embodiments 4 to 5 of the array substrate motherboard, the problem of array detection effect due to higher resistance is improved when array detection is performed, and under the condition that the array detection effect is well ensured, the panel area on the array substrate motherboard with bad can be well identified, so that the yield of the array substrate obtained by cutting is higher. Or, when array detection is performed, a large frame is not required to be arranged, so that the frame width of the array substrate obtained by cutting is small.
(7) Embodiments of display Panel
In this embodiment, the display panel includes the array substrate described in the embodiment of the array substrate described above.
The display panel provided by the embodiment comprises the array substrate described in the embodiment of the array substrate, static electricity is less likely to be generated at the fracture of the array detection wire 20 at the edge of the display panel, and the probability of poor or damaged caused by static electricity conduction to the inside of the display panel is reduced. Or, the defects generated in the preparation process can be identified in the early stage, so that the display panel has higher yield, or a larger frame is not required to be arranged in the preparation process, and the width of the frame of the display panel is smaller.
(8) Embodiments of a display device
In this embodiment, the display device includes the display panel described in the embodiment of the display panel described above.
The display device provided in this embodiment includes the display panel described in the embodiment of the display panel, and static electricity is less likely to be generated at the fracture of the array detection trace 20 at the edge of the display device, so that the probability of occurrence of defects or damages due to static electricity conduction into the display device is reduced. Or, the defects generated in the preparation process can be identified in the early stage, so that the display panel has higher yield, or a larger frame is not required to be arranged in the preparation process, and the width of the frame of the display panel is smaller.
It should be noted that in this document, relational terms such as "first" and "second" and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The foregoing is only a specific embodiment of the invention to enable those skilled in the art to understand or practice the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (12)
1. An array substrate mother board is characterized in that cutting lines are arranged on the array substrate mother board and divide the array substrate mother board into a plurality of panel areas;
the array substrate motherboard is also provided with a plurality of array detection wires, each array detection wire is arranged at a main line part in each panel area and a cross line connecting part for connecting the main line parts of adjacent panel areas together; the main line part is connected with an electrical terminal used for array detection in the panel area; the overline connecting part spans a cutting line between adjacent panel areas;
the width of the cross wire connecting part of each array detection wire is smaller than that of the main wire part of the array detection wire; and/or
The distance between the cross-line connecting parts of any two adjacent array detection wires is larger than the distance between the main line parts of the two adjacent array detection wires, and the width of the cross-line connecting part of each array detection wire is smaller than the distance between the cross-line connecting parts of any two adjacent array detection wires.
2. The array substrate motherboard of claim 1, wherein a width of the jumper connection portion of each of the array detection traces is 20 to 40 micrometers and a width of the main line portion is 30 to 60 micrometers.
3. The array substrate motherboard of claim 1, wherein a pitch of the overline connection portions of any two adjacent array detection wires is 20 to 40 micrometers, and a pitch of the main line portions is 10 to 30 micrometers.
4. The array substrate motherboard of any one of claims 1 to 3, wherein a width of a jumper connection portion of each of the array detection wirings is 30 micrometers, and a width of a main line portion is 50 micrometers;
the interval between the cross-line connection parts of any two adjacent array detection wires is 35 micrometers, and the interval between the main line parts is 25 micrometers.
5. The array substrate mother board is characterized in that a cutting line area is arranged on the array substrate mother board, the cutting line area divides the array substrate mother board into a plurality of panel areas, and an array detection wiring is arranged in the cutting line area;
each panel region comprises a display region and a wiring region positioned at one side of the display region, wherein the wiring region is provided with a flexible circuit board and a plurality of electrical terminals for array detection; the plurality of electrical terminals for array detection are connected with the array detection wiring;
at least part of the plurality of electrical terminals for array detection are first electrical terminals; the first electrical terminal is connected with the flexible circuit board and is connected with the array detection wire through a first connecting wire formed between the flexible circuit board and the array detection wire.
6. The array substrate motherboard of claim 5, wherein a portion of the plurality of electrical terminals for array inspection is a second electrical terminal connected by a second connection line formed between the electrical terminal and the array inspection trace.
7. The motherboard of claim 6, wherein a width of a non-overlapping area of a projection of each second electrical terminal on the array detection trace and a projection of other second electrical terminals on the array detection trace is greater than a first set value.
8. The motherboard of claim 7, wherein among the plurality of electrical terminals for array inspection, an electrical terminal having a width of a non-overlapping area of a projection of the array inspection trace and a projection of each second electrical terminal on the array inspection trace that is greater than a first set value is a second electrical terminal, and an electrical terminal having a width that is less than the first set value is a first electrical terminal.
9. The array substrate motherboard according to any one of claims 5 to 8, wherein the plurality of electrical terminals for array inspection are arranged in n rows in the wiring area, n being equal to or greater than 1;
one of the n rows of electrical terminals is a third electrical terminal, and the third electrical terminal is provided with an outward extension line; a third connecting wire is formed between the extension wire of the third electrical terminal and the array detection wire.
10. An array substrate, characterized in that the array substrate is cut from the array substrate mother board according to claims 1 to 4 or claims 5 to 9.
11. A display panel comprising the array substrate of claim 10.
12. A display device comprising the display panel of claim 11.
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| CN202111095061.7A CN113823643B (en) | 2021-09-17 | 2021-09-17 | Array substrate mother board, array substrate, display panel and display device |
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| CN202111095061.7A CN113823643B (en) | 2021-09-17 | 2021-09-17 | Array substrate mother board, array substrate, display panel and display device |
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