CN113823643A - Array substrate mother board, array substrate, display panel and display device - Google Patents
Array substrate mother board, array substrate, display panel and display device Download PDFInfo
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- CN113823643A CN113823643A CN202111095061.7A CN202111095061A CN113823643A CN 113823643 A CN113823643 A CN 113823643A CN 202111095061 A CN202111095061 A CN 202111095061A CN 113823643 A CN113823643 A CN 113823643A
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- 238000007689 inspection Methods 0.000 claims description 19
- 230000005611 electricity Effects 0.000 abstract description 28
- 230000003068 static effect Effects 0.000 abstract description 28
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- 238000002360 preparation method Methods 0.000 description 8
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
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Abstract
The invention relates to an array substrate mother board, an array substrate, a display panel and a display device. Cutting lines are arranged on the array substrate mother board, and divide the array substrate mother board into a plurality of panel areas; a plurality of array detection wires are also formed on the array substrate motherboard, and each array wire is arranged on a main wire part in each panel area and a cross wire connecting part which connects the main wire parts of the adjacent panel areas together; the main line part is connected with an electric terminal used for array detection in the panel area; the overline connecting part spans the cutting line between the adjacent panel areas; the width of the cross-line connecting part of each array detection wire is smaller than the width of the main line part of the array detection wire; and/or the distance between the cross line connecting parts of any two adjacent array detection wires is larger than the distance between the main line parts of the two adjacent array detection wires. The array substrate motherboard can ensure that static electricity is not easily generated at the fracture of the array detection wiring at the edge of each array substrate.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate mother board, an array substrate obtained by cutting the array substrate, a display panel comprising the array substrate and a display device comprising the display panel.
Background
The fabrication of an Array substrate is an important step in the fabrication of display panels. After the Array process is completed, inspection and testing of structures such as thin film transistors formed on a mother substrate of the Array substrate are required, which is generally called Array Test (Array Test). By array detection, the detection is poor in the early stage, and the problem existing in the subsequent process of continuously preparing products is avoided.
The array detection generally forms an array detection line (A/T line) on an array substrate motherboard, the array detection line is also connected with an array detection terminal (AT pad) and is also connected with an electric terminal (ET pad) in each panel area on the array substrate motherboard, and the electric terminal is connected with a grid line and a data line in the panel area, so that the connection between the array detection terminal and a sub-pixel in the panel area is realized, and the structure of the sub-pixel formed in the panel area is detected.
Each panel region on the array substrate motherboard is cut into an array substrate along a Cutting Line. According to different cutting modes, the array substrate mother board can be divided into two types, the first type is the array substrate mother board with zero cutting (only one cutting line is arranged between the adjacent panel areas, the two cutting lines are connected, and no space exists), and the second type is the array substrate mother board with non-zero cutting (two cutting lines are arranged between the adjacent panel areas, the two cutting lines are separated, and a space exists between the two cutting lines).
For the array substrate mother board with the zero-cutting mode, the array detection wires are arranged along cutting lines between adjacent panel areas, the array detection wires can cross the cutting lines between the adjacent panel areas, after the panel areas are cut to form the array substrate, the edge of the array substrate is provided with exposed fractures of the array detection wires, static electricity is easily formed at the fractures, and the static electricity is conducted into the array substrate to cause the defects or damages of the array substrate and the display panel.
For the array substrate mother board with the non-zero cutting mode, the array detection wires are arranged along the cutting area between two cutting lines of adjacent panel areas, the array detection wires extend out of connecting wires (generally ITO wires) towards the panel areas, and the connecting wires extend into the panel areas and are connected with the electric terminals of the panel areas. Each panel region has a large number of electrical terminals disposed therein, and when the width of the panel region is insufficient, the electrical terminals are generally arranged in a plurality of rows, and are arranged compactly and densely, and the pitch between adjacent electrical terminals is small. In such a case, the width of the ITO trace for connecting the electrical terminals and the array detection trace must be set to be thin to achieve the connection with the electrical terminals, otherwise, the ITO trace cannot be connected with the electrical terminals at the same time. The problem that this brings is that the thin ITO link causes the resistance between the array detection trace and the electrical terminal to be large, which is not favorable for array detection. Or, in another case, the width of the panel area is set to be larger, that is, the panel area has a larger frame, so that the distance between adjacent electrical terminals can be increased, and it is ensured that the ITO traces connecting the array detection traces and the electrical terminals have a sufficient width, but the frame width of the array substrate formed by cutting and the display panel further prepared is too large.
Disclosure of Invention
The invention provides an array substrate mother board, an array substrate, a display panel and a display device, and aims to solve the technical problems that fractures of array detection wires are generated at the edge of the array substrate in the prior art, the array detection wires are prone to being bad and damaged due to static electricity, and the width of the array detection wires is required to be set to be thin, so that array detection is not facilitated or the width of a frame is large.
According to the array substrate mother board provided by the invention, the array substrate mother board is provided with cutting lines, and the array substrate mother board is divided into a plurality of panel areas by the cutting lines; a plurality of array detection wires are also formed on the array substrate motherboard, and each array wire is arranged on a main wire part in each panel area and a cross wire connecting part which connects the main wire parts of the adjacent panel areas together; the main line part is connected with an electric terminal used for array detection in the panel area; the overline connecting part spans the cutting line between the adjacent panel areas; the width of the cross-line connecting part of each array detection wire is smaller than the width of the main line part of the array detection wire; and/or the distance between the cross line connecting parts of any two adjacent array detection wires is larger than the distance between the main line parts of the two adjacent array detection wires.
The width of the cross-line connecting part of each array detection line is 20-40 micrometers, and the width of the main line part is 30-60 micrometers.
The distance between the crossing line connecting parts of any two adjacent array detection wires is 20-40 microns, and the distance between the main line parts is 10-30 microns.
The width of the cross-line connecting part of each array detection line is smaller than the distance between the cross-line connecting parts of any two adjacent array detection lines.
The width of the cross-line connecting part of each array detection line is 30 micrometers, and the width of the main line part is 50 micrometers; the distance between the cross-line connecting parts of any two adjacent array detection wires is 35 micrometers, and the distance between the main line parts is 25 micrometers.
According to the other array substrate motherboard provided by the invention, a cutting line area is arranged on the array substrate motherboard, the array substrate motherboard is divided into a plurality of panel areas by the cutting line area, and array detection wiring is arranged in the cutting line area; each panel area comprises a display area and a wiring area positioned on one side of the display area, and the wiring area is provided with a flexible circuit board and a plurality of electric terminals for array detection; the plurality of electrical terminals for array detection are connected with the array detection wires; at least part of the plurality of electrical terminals for array detection is a first electrical terminal; the first electrical terminals are connected with the flexible circuit board and connected with the array detection wires through first connecting wires formed between the flexible circuit board and the array detection wires.
And the second electric terminals are connected through a second connecting wire formed between the electric terminals and the array detection wiring.
The width of a non-overlapping area between the projection of each second electrical terminal on the array detection trace and the projections of other second electrical terminals on the array detection trace is greater than a first set value.
Among the plurality of electrical terminals for array detection, the electrical terminal of which the width of the non-overlapping area between the projection of the array detection trace and the projection of each second electrical terminal on the array detection trace is larger than a first set value is the second electrical terminal, and the electrical terminal of which the width is smaller than the first set value is the first electrical terminal.
The plurality of electric terminals for array detection are arranged in n rows in the wiring area, wherein n is more than or equal to 1; the electric terminal at the edge of one of the n rows of electric terminals is a third electric terminal, and the third electric terminal is provided with an outward extension line; and a third connecting line is formed between the extension line of the third electrical terminal and the array detection line.
The array substrate provided by the invention is formed by cutting the array substrate motherboard.
The display panel provided by the invention comprises the array substrate.
The display device provided by the invention comprises the display panel.
Compared with the prior art, the array substrate motherboard, the array substrate, the display panel and the display device provided by the embodiment of the invention have the following advantages:
in the array substrate motherboard provided by the embodiment of the invention, each array detection trace comprises a main line part and a cross line connecting part, the width of the cross line connecting part of each array detection trace is smaller than the width of the main line part, and/or the distance between the cross line connecting parts of any two adjacent array detection traces is larger than the distance between the main line parts, so that the width of the array detection trace is reduced at the cross cutting line at the edge of a panel area, and is smaller than the width of the main line part of the array detection trace in the panel area, and/or the distance between the adjacent array detection traces is increased and is larger than the distance between the main line parts of the adjacent array detection traces in the panel area, and thus, after a plurality of panel areas on the array substrate motherboard are cut into a plurality of array substrates along the cutting line, the array detection trace at the edge of each array substrate is smaller and/or the distance between the adjacent array detection traces is larger, static electricity is less likely to be generated, thereby reducing the probability of failure or damage of the array substrate due to conduction of static electricity into the array substrate.
In another array substrate motherboard provided by the embodiment of the invention, at least part of the plurality of electrical terminals for array detection is a first electrical terminal; connect first electrical property terminal to flexible circuit board, through forming at flexible circuit board and array detection walk the first connecting wire between the line and the array detection walk the line connection, set up like this and all need not all electrical property terminals and all directly walk the line and detect through ITO and walk the line connection, avoid because walking the width that the ITO that the line space is not enough leads to walks the line must set up thin, make its resistance higher, thereby influence the problem that the array detected, perhaps, in order to increase and walk the line space, lead to the width of frame to have to set up great problem.
The array substrate provided by the embodiment of the invention is formed by cutting according to the array substrate motherboard, and the obtained array detection wires at the edge of the first array substrate have smaller fractures and/or the distance between the adjacent array detection wire fractures is larger, so that static electricity is less likely to be generated, and the probability of bad or damaged array substrates caused by the conduction of the static electricity into the array substrate is reduced; the second array substrate improves the problem of array detection effect due to high impression of resistance when array detection is carried out, and has the advantage that a panel area on a motherboard of a bad array substrate can be well identified under the condition that the array detection effect is well guaranteed, so that the yield of the array substrate obtained by cutting is high, or a large frame does not need to be arranged when the array detection is carried out, and the frame width of the array substrate obtained by cutting is small.
The display panel provided by the embodiment of the invention comprises the array substrate, static electricity is less prone to be generated at the fracture of the array detection wiring at the edge of the display panel, and the probability of poor or damaged due to conduction of the static electricity to the inside of the display panel is reduced. Or, the defects generated in the preparation process can be identified in the early stage, so that the display panel has higher yield, or a larger frame is not required to be arranged in the preparation process, so that the width of the frame of the display panel is smaller.
The display device provided by the embodiment of the invention comprises the display panel, static electricity is less likely to be generated at the fracture of the array detection wiring at the edge of the display device, and the probability of poor or damaged due to conduction of the static electricity to the inside of the display device is reduced. Or, the defects generated in the preparation process can be identified in the early stage, so that the display panel has higher yield, or a larger frame is not required to be arranged in the preparation process, so that the width of the frame of the display panel is smaller.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive exercise.
Fig. 1 is a schematic structural diagram of a motherboard of an array substrate provided in embodiments 1 to 3 of the present invention;
fig. 2 is a partial schematic view of array detection traces in the array substrate motherboard shown in fig. 1;
fig. 3 is a schematic structural diagram of an array substrate motherboard according to embodiment 4 of the present invention;
FIG. 4 is a schematic diagram of a structure of a wiring region in a panel region of the motherboard of the array substrate shown in FIG. 3;
FIG. 5 is a schematic diagram of another structure of a wiring region in a panel region of the motherboard of the array substrate shown in FIG. 3;
fig. 6 is a schematic view illustrating a connection manner between the array detection trace and the second electrical terminal in the array substrate motherboard shown in fig. 3;
fig. 7 is a schematic view illustrating a connection manner between the array detection traces and the first electrical terminals in the array substrate motherboard shown in fig. 3;
fig. 8 is a schematic view illustrating a connection manner between array detection traces and electrical terminals in the array substrate motherboard shown in fig. 3;
fig. 9 is a schematic view of a connection manner between the array detection trace and the third electrical terminal in the array substrate motherboard according to embodiment 5 of the present invention.
In the figure:
10-panel area; 101-a display area; 102-a wiring area;
11-electrical terminals; 11 a-a first electrical terminal; 11 b-a second electrical terminal; 11 c-a third electrical terminal; 110-extension 12-flexible circuit board;
13-a drive circuit;
20-array detection routing; 201-main line portion; 202-a flying lead connection;
21-a first connection line;
22-a second connecting line;
23-a third connecting line;
CL-cut line; CA-cut line region.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
Embodiments of an array substrate motherboard, an array substrate, a display panel and a display device provided by the invention are described below with reference to the drawings.
(1) Embodiment 1 of array substrate mother board
Referring to fig. 1, the array substrate motherboard provided in this embodiment is provided with a cutting line CL, and the cutting line CL divides the array substrate motherboard into a plurality of panel regions 10. Adjacent panel sections 10 meet at a cut line CL with no gaps therebetween. After cutting along the cutting line CL, each panel region 10 becomes an individual array substrate. Each panel area 10 includes a display area 101(Active area, abbreviated as AA area) and a wiring area 102, a plurality of pixel units are disposed in the display area 101, and each pixel unit includes a plurality of sub-pixels; the wiring region 102 is provided with a drive circuit, a flexible circuit board, and the like, and is also provided with a plurality of electrical terminals.
Referring to fig. 1 and 2, a plurality of array detection traces 20 are further formed on the array substrate motherboard, each array detection trace 20 has a plurality of intersections with the cutting line CL, each panel area 10 has at least one corresponding intersection, and the array detection trace 20 extends into the panel area 10 from the corresponding intersection of each panel area 10 and is connected to an electrical terminal for array detection in the panel area 10. In other words, each array detection trace 20 is provided with a main line part 201 in each panel area 10 and a crossover connection part 202 connecting the main line parts 201 of the adjacent panel areas 10 together; the main line part 201 is connected with an electric terminal used for array detection in the panel area 10; the crossover connection 202 crosses the cutting line CL between adjacent panel regions 10. It should be noted that there are more electrical terminals in the panel area 10, and the more electrical terminals may also have different purposes, and all the electrical terminals mentioned in this embodiment are electrical terminals for array detection, and do not include electrical terminals for other purposes that are not connected to the array detection trace 20.
With continued reference to fig. 2, the number of array detection traces 20 is plural. Specifically, the plurality of array detection traces 20 are arranged in parallel along the same direction at intervals, for example, in fig. 2, the plurality of array detection traces 20 are substantially parallel to each other.
In the present embodiment, the width of the crossover connection portion 202 of each array detection trace 20 is smaller than the width of the main line portion 201 thereof. In the existing array substrate motherboard, the width of the array detection trace 20 at the position of the panel area 10 edge across the cutting line CL is the same as the width in the panel area 10, and the width of the array detection trace 20 at the position of the panel area 10 edge across the cutting line CL is not intentionally reduced; compared with the existing array substrate motherboard, in the embodiment, especially, the width of the array detection trace 20 at the cross-cutting line CL at the edge of the panel area 10 is reduced to be smaller than the width of the main line part 201 of the array detection trace 20 in the panel area 10, so that after the plurality of panel areas 10 on the array substrate motherboard are cut into a plurality of array substrates along the cutting line CL, the fracture of the array detection trace 20 at the edge of each array substrate is smaller, static electricity is less likely to be generated, and the probability of failure or damage of the array substrate due to the conduction of the static electricity into the array substrate is reduced.
Specifically, in the present embodiment, the width of the crossover connecting portion 202 of each array detection trace 20 is 20 to 40 micrometers, and the width of the main line portion 201 is 30 to 60 micrometers. Further, the width of the crossover connecting portion 202 of each array detection trace 20 is 30 micrometers, and the width of the main line portion 201 is 50 micrometers.
In this embodiment, the width of the crossing connection portion 202 of each array detection trace 20 is smaller than the pitch of the crossing connection portions 202 of any two adjacent array detection traces 20. After each panel area 10 is cut into the array substrate, the probability of static electricity generated between the fractures of different array detection wires 20 at the edge of the array substrate due to too short distance between the fractures and too dense fractures is reduced, and therefore the array substrate is better prevented from being badly or damaged due to static electricity.
(2) Embodiment 2 of array substrate mother board
As in embodiment 1, the array substrate motherboard in this embodiment is also provided with a cutting line CL, the cutting line CL divides the array substrate motherboard into a plurality of panel regions 10, and the array substrate motherboard is also provided with an array detection trace 20, and the cutting line CL, the panel regions 10, the array detection trace 20, and the like are the same as those in embodiment 1, and are not described again here. Only the differences between the array substrate motherboard in this embodiment and the above embodiment 1 will be described in detail.
In this embodiment, as shown in fig. 2, the pitch of the crossing connection portion 202 of any two adjacent array detection traces 20 is greater than the pitch of the main line portion 201 of the two adjacent array detection traces 20.
In the existing array substrate motherboard, the distance between adjacent array detection traces 20 at the position of the panel area 10 edge across the cutting line CL is consistent with the distance within the panel area 10, and the distance between adjacent array detection traces 20 at the position of the panel area 10 edge across the cutting line CL is not intentionally increased; compared with the existing array substrate motherboard, in the embodiment, especially, the distance between the adjacent array detection wires 20 at the cross-cutting line CL at the edge of the panel area 10 is increased to be larger than the distance between the main line portions 201 of the adjacent array detection wires 20 in the panel area 10, so that after the plurality of panel areas 10 on the array substrate motherboard are cut into a plurality of array substrates along the cutting line CL, the distance between the fractures of the adjacent array detection wires 20 at the edge of each array substrate is larger, static electricity is less likely to be generated, and the probability of failure or damage of the array substrate due to the conduction of the static electricity into the array substrate is reduced.
Specifically, the distance between the crossing wire connection portions 202 of any two adjacent array detection wires 20 is 20 to 40 micrometers, and the distance between the main wire portions 201 is 10 to 30 micrometers. Further, the pitch of the crossover connecting portion 202 of any two adjacent array detection traces 20 is 35 micrometers, and the pitch of the main line portion 201 is 25 micrometers.
The other parts not mentioned in this embodiment are the same as those in embodiment 1, and are not described herein again.
(3) Embodiment 3 of array substrate mother board
As in embodiments 1 and 2, the array substrate motherboard in this embodiment is also provided with a cutting line CL, the cutting line CL divides the array substrate motherboard into a plurality of panel regions 10, and the array substrate motherboard is also provided with an array detection trace 20, and the cutting line CL, the panel regions 10, the array detection trace 20, and the like are the same as those in embodiment 1, and are not described again here. Only the differences between the array substrate motherboard in this embodiment and the above embodiment 1 will be described in detail.
In the present embodiment, as shown in fig. 2, the width of the crossover connection portion 202 of each array detection trace 20 is smaller than the width of the main line portion 201; moreover, the pitch of the crossover connecting portion 202 of any two adjacent array detection traces 20 is greater than the pitch of the main line portion 201 of the two adjacent array detection traces 20.
In the existing array substrate motherboard, the width of the array detection trace 20 at the position of the panel area 10 edge across the cutting line CL is consistent with the width in the panel area 10, the distance between the adjacent array detection traces 20 at the position of the panel area 10 edge across the cutting line CL is also consistent with the distance in the panel area 10, the width of the array detection trace 20 is not intentionally reduced at the position of the panel area 10 edge across the cutting line CL, and the distance between the adjacent array detection traces 20 is expanded; compared with the existing array substrate motherboard, in the embodiment, especially, the width of the array detection trace 20 is reduced at the cross-cutting line CL at the edge of the panel area 10, and is smaller than the width of the main line part 201 of the array detection trace 20 in the panel area 10, and the distance between the adjacent array detection traces 20 is increased and is larger than the distance between the main line parts 201 of the adjacent array detection traces 20 in the panel area 10, so that after the plurality of panel areas 10 on the array substrate motherboard are cut into a plurality of array substrates along the cutting line CL, the fracture of the array detection trace 20 at the edge of each array substrate is smaller, and the distance between the fractures of the adjacent array detection traces 20 is larger, so that static electricity is less likely to be generated, and the probability of failure or damage of the array substrate caused by the conduction of the static electricity into the array substrate is reduced.
Specifically, the width of the crossover connecting part 202 of each array detection trace 20 is 20-40 micrometers, and the width of the main line part 201 is 30-60 micrometers; the distance between the crossing line connecting parts 202 of any two adjacent array detection tracks 20 is 20-40 microns, and the distance between the main line parts 201 is 10-30 microns. Further, the width of the crossover connecting portion 202 of each array detection trace 20 is 30 micrometers, and the width of the main line portion 201 is 50 micrometers; the pitch of the crossover connecting part 202 of any two adjacent array detection tracks 20 is 35 microns, and the pitch of the main line part 201 is 25 microns.
To sum up, in the array substrate motherboard provided in embodiments 1 to 3 of the present invention, each array detection trace 20 includes a main line portion 201 and a crossing line connection portion 202, a width of the crossing line connection portion 202 of each array detection trace 20 is smaller than a width of the main line portion 201, and/or a pitch of the crossing line connection portions 202 of any two adjacent array detection traces 20 is larger than a pitch of the main line portions 201 of the two adjacent array detection traces 20, such that the width of the array detection trace 20 is reduced at a crossing line CL at an edge of the panel region 10, and is smaller than the width of the main line portion 201 of the array detection trace 20 in the panel region 10, and/or the pitch of the adjacent array detection traces 20 is increased and is larger than the pitch of the main line portions 201 of the adjacent array detection traces 20 in the panel region 10, such that after the plurality of panel regions 10 on the array substrate motherboard are cut into a plurality of array substrates along the cutting line CL, the array detection traces 20 at the edge of each array substrate have smaller fractures and/or the distance between the fractures of the adjacent array detection traces 20 is larger, so that static electricity is less likely to be generated, and the probability of bad or damaged array substrates caused by the conduction of the static electricity into the array substrates is reduced.
(4) Embodiment 4 of array substrate mother board
As shown in fig. 3, the array substrate motherboard provided in this embodiment is provided with a cutting line area CA, where the cutting line area CA is an area between two cutting lines CL on the array substrate motherboard. The scribe line area CA divides the array substrate motherboard into a plurality of panel areas 10, and a gap is formed between adjacent panel areas 10, that is, the scribe line area CA. After cutting along the two cutting lines CL at the edge of the cutting line area CA, each panel area 10 becomes an individual array substrate. The scribe line area CA is provided with array detection traces 20.
Each panel area 10 includes a display area 101(Active area, abbreviated as AA area) and a wiring area 102 located on one side of the display area 101. A plurality of pixel units, each including a plurality of sub-pixels, are disposed in the display region 101. The wiring region 102 is provided with the electric terminals 11 for array detection, the flexible circuit board 12, the drive circuit 13, and the like. The specific arrangement of the wiring region 102 is as shown in fig. 4 and 5, and fig. 4 and 5 respectively show two arrangements of the wiring region 102, in the structure shown in fig. 4, the number of the flexible circuit boards 12 is two, the number of the driving circuits 13 is 2, and the driving circuits 13 and the flexible circuit boards 12 are arranged oppositely; in the structure shown in fig. 5, the number of the flexible circuit boards 12 is 2, the number of the drive circuits 13 is 4, and each flexible circuit board 12 is located between two drive circuits 13.
In the wiring region 102, the number of the electrical terminals 11 for array inspection is plural, and the plural electrical terminals 11 for array inspection are connected to the array inspection trace 20. It should be noted that there are a large number of electrical terminals in the wiring area 102 of the panel area 10, and the large number of electrical terminals may have different purposes, and the electrical terminals 11 mentioned in this embodiment are all electrical terminals for array detection, and do not include electrical terminals for other purposes that are not connected to the array detection traces 20.
As described in the background section, in the wiring region of each panel region 10, the plurality of electrical terminals 11 are generally arranged in two rows due to insufficient width, as shown in fig. 6, and in order to save the space of the wiring region 102, the plurality of electrical terminals 11 are arranged compactly, and the pitch between adjacent electrical terminals 11 is small. For example, in fig. 6, the width of each electrical terminal 11 is 700 micrometers, and the pitch between adjacent electrical terminals 11 is 400 micrometers, it is conceivable that even in the case that two rows of electrical terminals 11 are arranged in a staggered manner in fig. 6, ITO traces cannot be arranged on all the electrical terminals 11 in the two rows, and all the electrical terminals 11 are directly connected to the array detection trace 20.
In the present embodiment, referring to fig. 6, 7 and 8, at least a portion of the plurality of electrical terminals 11 for array inspection is a first electrical terminal 11 a; the first electrical terminals 11a are connected to the flexible circuit board 12 and connected to the array detection trace 20 through first connection lines 21 formed between the flexible circuit board 12 and the array detection trace 20. Part of the electrical terminals 11 are firstly connected to the flexible circuit board 12, and the connection between the electrical terminals 11 and the array detection wires 20 is continuously realized through the first connecting lines 21, so that the arrangement is not required that all the electrical terminals 11 are directly connected with the array detection wires 20 through the ITO wires, and the problem that the width of the ITO wires caused by insufficient wire space is required to be thinner, the resistance of the ITO wires is higher, and the array detection is influenced is solved, or the width of the frame is required to be larger in order to increase the wire space.
Specifically, the plurality of electrical terminals 11 for array inspection may be all the first electrical terminals 11a, that is, all the electrical terminals 11 for array inspection are connected to the flexible circuit board 12 and connected to the array inspection trace 20 through the first connection line 21. Or, the plurality of electrical terminals 11 for array detection, wherein a portion of the plurality of electrical terminals 11 is the first electrical terminal 11a, and the portion of the first electrical terminal 11a is connected to the flexible circuit board 12 and connected to the array detection trace 20 through the first connection line 21. And the other part is the second electrical terminal 11b, and the part of the second electrical terminal 11b is connected through the second connection line 22 formed between the second electrical terminal 11b and the array detection trace 20, as shown in fig. 6 and 7, the second connection line 22 may specifically be an ITO trace, and the ITO trace may be formed synchronously in processes of preparing an ITO electrode in the display area 101 on the array substrate motherboard, and the like, without adding a process. It is understood that since the portion of the electrical terminals 11 are the first electrical terminals 11a, the connection with the array detection trace 20 does not occupy the space around the electrical terminals 11, and the space for disposing the second connection line 22 for the second electrical terminals 11b is increased, the width of the second connection line 22 connecting between each second electrical terminal 11b and the array detection trace 20 can be set to a desired suitable width.
Referring to fig. 6, in the present embodiment, the width of the non-overlapping area between the projection of each second electrical terminal 11b on the array detection trace 20 and the projection of the other second electrical terminals 11b on the array detection trace 20 is greater than a first predetermined value. The first set value is set as required, and specifically may be determined according to a standard that if the width of the non-overlapping area is greater than the first set value, there is enough space and width (for example, the width of the second connection line is 750 micrometers, the width of the non-overlapping area is 700 micrometers, and the distance between the electrical terminals 11 is 400 micrometers, the first set value may be determined to be 700 micrometers, that is, the first set value may be smaller than the width of the second connection line, and specifically, a value smaller than the width of the second connection line does not exceed the distance between the electrical terminals 11). The purpose of the above arrangement is to ensure that each second electrical terminal 11b has a sufficient line width for arranging the second connection line 22. For the electrical terminals 11 that are overlapped with other second electrical terminals 11b and the width of the non-overlapped area is smaller than the first set value, it is indicated that there is not enough line width at the electrical terminals 11 for arranging the second connection lines 22, so that the electrical terminals 11 cannot be used as the second electrical terminals 11b but only as the first electrical terminals 11a, and are connected with the array detection traces 20 through the flexible circuit board 12 and the first connection lines 21, so as to avoid the phenomenon that the second connection lines 22 of the electrical terminals 11 and the second connection lines 22 of other second electrical terminals 11b overlap due to the insufficient space for arranging the second connection lines 22 when such electrical terminals 11 are used as the second electrical terminals 11 b.
Further, of the plurality of electrical terminals 11 for array inspection, the electrical terminal 11 having a width of a non-overlapping area between a projection of the array inspection trace 20 and a projection of each second electrical terminal 11b on the array inspection trace 20 is a second electrical terminal 11b, and the electrical terminal 11 having a width smaller than a first predetermined value is a first electrical terminal 11 a. In this way, as for each electrical terminal 11, as long as the non-overlapping area of the electrical terminal 11 and the other second electrical terminal 11b is greater than the first predetermined value, the electrical terminal 11 is used as the second electrical terminal 11b to be directly connected with the array detection trace 20 through the second connection line 22, and the other electrical terminals 11 which cannot satisfy the non-overlapping area greater than the first predetermined value are used as the first electrical terminal 11a to be connected with the array detection trace 20 through the flexible circuit board 12 and the first connection line 21. Through the arrangement, the plurality of electrical terminals 11 for array detection, which meet the width and space conditions for arranging the second connecting wires 22, are used as the second electrical terminals 11b, so that the number and the occupation ratio of the second electrical terminals 11b are increased as much as possible; the excessive connection of the electrical terminals 11 to the flexible circuit board 12 is avoided, so that more Pin holes (Pin) need to be added to the flexible circuit board 12, and the connection of the first connection lines 21 remaining on the array substrate after the panel area 10 is cut into the array substrate to the flexible circuit board 12 can also be avoided. Specifically, as for the plurality of electrical terminals 11 for array detection arranged in two rows as shown in fig. 6 and 7, the two rows of electrical terminals 11 are staggered, one electrical terminal 11 in any row is located between two electrical terminals 11 in the other row, the electrical terminals 11 in the two rows form a staggered relationship, and for the electrical terminals 11 in this case, the gap between the adjacent electrical terminals 11 is not enough to provide the second connecting line 22, so that when one electrical terminal 11 in one row is connected to the array detection trace 20 through the second connecting line 22, the electrical terminal 11 in the other row having a partial area overlapping with the electrical terminal 11 can only be connected to the flexible circuit board 12 due to the insufficient width and space of the non-overlapping area, and connected to the array detection trace 20 through the first connecting line 21, and so on, the first electrical terminals 11a and the second electrical terminals 11b are formed at intervals as a whole, and also in a case where one row is all the first electrical terminals 11a and the other row is all the second electrical terminals 11b (here, it is discussed that each of the electrical terminals 11 shown in fig. 6 and 7 is an electrical terminal 11 for array inspection; in practice, each of the electrical terminals 11 shown in fig. 6 and 7 may be partially used for other purposes, in this case, the electrical terminals 11 for array inspection are arranged according to the principle as described above as the first electrical terminal 11a and the second electrical terminal 11b, and more electrical terminals 11 are preferably arranged as the second electrical terminals 11 b).
(5) Embodiment 5 of array substrate mother board
In this embodiment, the array substrate motherboard is also provided with a cutting line area CA, the cutting line area CA divides the array substrate motherboard into a plurality of panel areas 10, the array detection trace 20 is also provided in the cutting line area CA, and the structures and the arrangements of the cutting line area CA, the panel areas 10, and the array detection trace 20 are the same as those in embodiment 4, and thus, the description thereof is omitted. Only differences between the array substrate motherboard in the present embodiment and the above embodiment 4 will be described in detail.
In the present embodiment, as shown in FIG. 9, a plurality of electrical terminals 11 for array detection are arranged in n rows in the wiring region, where n is greater than or equal to 1; the electrical terminal 11 at the edge of one of the n rows of electrical terminals is a third electrical terminal 11c, and the third electrical terminal 11c has an outward extending line 110; a third connection line 23 is formed between the extension line 110 of the third electrical terminal 11c and the array detection trace 20.
In the embodiment 4, if the non-overlapping area between the third electrical terminal 11c and the other second electrical terminals 11b is smaller than the first predetermined value, that is, there is not enough space and width for arranging the second connection lines 22 at the third electrical terminal 11c, then the third electrical terminal 11c can only be used as the first electrical terminal 11a to connect to the flexible circuit board 12 and connect to the array detection trace 20 through the first connection line 21. However, in this embodiment, when the non-overlapping area between the third electrical terminal 11c and the other second electrical terminal 11b is smaller than the first predetermined value, the extending line 110 is obtained by extending outward, the non-overlapping area between the extending line 110 and the other second electrical terminal 11b is larger than the first predetermined value, the connecting line directly connected to the array detection trace 20 is provided with sufficient width and space, and is referred to as a third connecting line 23, so that the direct connection between the third electrical terminal 11c and the array detection trace 20 is realized through the extending line 110 and the third connecting line 23. The third electrical terminal 11c, which originally can only be connected with the array detection line 20 through the flexible circuit board 12 and the first connection line 21, is directly connected with the array detection line 20 through the third connection line 23, so that the number and occupation ratio of the electrical terminals 11 directly connected with the array detection line 20 in the plurality of electrical terminals 11 for array detection are improved.
Specifically, the third connection line 23 may also be an ITO trace, which may be formed synchronously in processes of preparing an ITO electrode in the display area 101 on the array substrate motherboard, and does not need to add one process.
In summary, in the array substrate mother board provided in embodiments 4 to 5 of the present invention, at least some of the electrical terminals 11 for array detection are the first electrical terminals 11 a; connect first electrical property terminal 11a to flexible circuit board 12, through forming the first connecting line 21 between flexible circuit board 12 and array detection line 20 and being connected with array detection line 20, set up like this and just need not all electrical property terminals 11 and all directly to be connected with array detection line 20 through the ITO line, avoid because the width of the ITO line that the line space is not enough leads to must set up thinner, make its resistance higher, thereby influence the problem that array detected, or, in order to increase the line space, lead to the width of frame to have to set up great problem.
(6) Embodiments of the array substrate
In this embodiment, the array substrate is cut according to the array substrate motherboard described in the above embodiments of the array substrate motherboard.
According to the array substrate obtained by cutting according to embodiments 1-3 of the array substrate motherboard, the array detection wires 20 at the edge have smaller fractures and/or the distance between the fractures of the adjacent array detection wires 20 is larger, so that static electricity is less likely to be generated, and the probability of bad or damaged array substrates caused by the conduction of the static electricity into the array substrate is reduced.
According to the array substrate obtained by cutting according to embodiments 4-5 of the array substrate motherboard, the problem that the array detection effect is impressed due to high resistance is solved during array detection, and a panel area on the array substrate motherboard with a defect can be well identified under the condition that the array detection effect is well guaranteed, so that the yield of the array substrate obtained by cutting is high. Or, when the array detection is carried out, a large frame is not required to be arranged, so that the frame width of the array substrate obtained by cutting is small.
(7) Embodiments of display Panel
In this embodiment, the display panel includes the array substrate described in the above embodiments of the array substrate.
The display panel provided by the embodiment includes the array substrate described in the embodiment of the array substrate, static electricity is less likely to be generated at the fracture of the array detection routing 20 at the edge of the display panel, and the probability of occurrence of defects or damage due to conduction of the static electricity to the inside of the display panel is reduced. Or, the defects generated in the preparation process can be identified in the early stage, so that the display panel has higher yield, or a larger frame is not required to be arranged in the preparation process, so that the width of the frame of the display panel is smaller.
(8) Embodiments of the display device
In this embodiment, the display device includes the display panel described in the embodiment of the display panel described above.
The display device provided by the embodiment includes the display panel described in the above embodiment of the display panel, static electricity is less likely to be generated at the fracture of the array detection trace 20 at the edge of the display device, and the probability of occurrence of defects or damage due to conduction of static electricity to the inside of the display device is reduced. Or, the defects generated in the preparation process can be identified in the early stage, so that the display panel has higher yield, or a larger frame is not required to be arranged in the preparation process, so that the width of the frame of the display panel is smaller.
It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The foregoing are merely exemplary embodiments of the present invention, which enable those skilled in the art to understand or practice the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (13)
1. The array substrate mother board is characterized in that cutting lines are arranged on the array substrate mother board, and the array substrate mother board is divided into a plurality of panel areas by the cutting lines;
a plurality of array detection wires are also formed on the array substrate motherboard, and each array detection wire is arranged on a main wire part in each panel area and a cross wire connecting part which connects the main wire parts of the adjacent panel areas together; the main line part is connected with an electric terminal used for array detection in the panel area; the overline connecting part spans the cutting line between the adjacent panel areas;
the width of the cross-line connecting part of each array detection wire is smaller than the width of the main line part of the array detection wire; and/or
The distance between the cross line connecting parts of any two adjacent array detection wires is larger than the distance between the main line parts of the two adjacent array detection wires.
2. The array substrate motherboard according to claim 1, wherein the width of the crossover connection portion of each array detection trace is 20-40 microns, and the width of the main line portion is 30-60 microns.
3. The array substrate motherboard according to claim 1, wherein the pitch of the crossover connecting portion of any two adjacent array detection traces is 20-40 microns, and the pitch of the main line portion is 10-30 microns.
4. The array substrate motherboard according to claim 1, wherein the width of the cross-line connecting portion of each array detection trace is smaller than the pitch of the cross-line connecting portions of any two adjacent array detection traces.
5. The array substrate motherboard according to any one of claims 1 to 4, wherein the width of the crossover connection portion of each array detection trace is 30 microns, and the width of the main line portion is 50 microns;
the distance between the cross-line connecting parts of any two adjacent array detection wires is 35 micrometers, and the distance between the main line parts is 25 micrometers.
6. An array substrate motherboard is characterized in that a cutting line area is arranged on the array substrate motherboard, the cutting line area divides the array substrate motherboard into a plurality of panel areas, and the cutting line area is provided with array detection wiring;
each panel area comprises a display area and a wiring area positioned on one side of the display area, and the wiring area is provided with a flexible circuit board and a plurality of electric terminals for array detection; the plurality of electrical terminals for array detection are connected with the array detection wires;
at least part of the plurality of electrical terminals for array detection is a first electrical terminal; the first electrical terminals are connected with the flexible circuit board and connected with the array detection wires through first connecting wires formed between the flexible circuit board and the array detection wires.
7. The array substrate motherboard of claim 6, wherein some of the plurality of electrical terminals for array inspection are second electrical terminals connected by second connecting lines formed between the electrical terminals and the array inspection traces.
8. The array substrate motherboard of claim 7, wherein a width of a non-overlapping area between a projection of each second electrical terminal on the array trace and a projection of the other second electrical terminals on the array trace is greater than a first predetermined value.
9. The array substrate motherboard according to claim 8, wherein the electrical terminals of the plurality of electrical terminals for array inspection have a width of a non-overlapping region between a projection of the array inspection trace and a projection of each second electrical terminal of the plurality of electrical terminals for array inspection trace, the width of the non-overlapping region being greater than a first predetermined value.
10. The array substrate motherboard according to any of claims 6 to 9, wherein the plurality of electrical terminals for array inspection are arranged in n rows in the wiring region, n is greater than or equal to 1;
the electric terminal at the edge of one of the n rows of electric terminals is a third electric terminal, and the third electric terminal is provided with an outward extension line; and a third connecting line is formed between the extension line of the third electrical terminal and the array detection line.
11. An array substrate, wherein the array substrate is cut according to the array substrate mother board of claims 1 to 5 or 6 to 10.
12. A display panel comprising the array substrate according to claim 11.
13. A display device characterized by comprising the display panel according to claim 12.
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| CN202111095061.7A CN113823643B (en) | 2021-09-17 | 2021-09-17 | Array substrate mother board, array substrate, display panel and display device |
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| CN202111095061.7A CN113823643B (en) | 2021-09-17 | 2021-09-17 | Array substrate mother board, array substrate, display panel and display device |
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| CN113823643B (en) | 2024-03-01 |
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