CN108490654B - Array substrate, array substrate motherboard and display device - Google Patents
Array substrate, array substrate motherboard and display device Download PDFInfo
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- CN108490654B CN108490654B CN201810291440.5A CN201810291440A CN108490654B CN 108490654 B CN108490654 B CN 108490654B CN 201810291440 A CN201810291440 A CN 201810291440A CN 108490654 B CN108490654 B CN 108490654B
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
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- G02F1/1309—Repairing; Testing
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Abstract
The application provides an array substrate, an array substrate mother board and a display device, wherein the array substrate mother board comprises a first test area and a second test area which are divided by a cutting line, a plurality of test units are arranged in the second test area, each test unit comprises a test short-circuit bar and a plurality of signal lines connected to the test short-circuit bar, and the test short-circuit bar is used for inputting detection signals to the signal lines; the test short-circuit bars of each test unit are sequentially connected in series through a series connection line, and the series connection line crosses the cutting line; the Array test before the cutting process and the Cell test after the cutting process are carried out through the same testing short-circuit rod, so that the defect of the testing short-circuit rod can be detected in the Array test stage, the next procedure is avoided flowing in, the abnormal lighting picture caused by the defect of the testing short-circuit rod is avoided in the Cell test stage, and the productivity and the yield of the Cell test stage are further improved.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, an array substrate motherboard and a display device.
Background
Currently, in the field of TFT-LCD detection, a short Bar (Shorting Bar) lighting method is widely used. Because the fixture is simple and stable in lighting, the operation cost and the maintenance cost can be effectively reduced. However, since the Cell testing shorting bar and the Array testing shorting bar are separately disposed, the opening defect of the via hole ITO on the Cell testing shorting bar cannot be detected in the Array testing stage, so that the Array substrate with the Cell testing shorting bar defect enters the next process, and further, the lighting screen abnormality (such as X-Line defect) occurs in the Cell testing stage, which seriously affects the productivity and yield of the Cell testing stage.
Disclosure of Invention
The invention provides an array substrate, an array substrate motherboard and a display device, which are used for improving the productivity and the yield of a Cell testing stage.
In order to solve the above problems, the present invention discloses an array substrate motherboard, including a first test region and a second test region divided by a cutting line, wherein the second test region is provided with a plurality of test units, each test unit includes a test shorting bar and a plurality of signal lines connected to the test shorting bar, and the test shorting bar is used for inputting detection signals to the signal lines;
the test short-circuit bars of each test unit are sequentially connected in series through a series line, and the series line crosses the cutting line and is distributed in the first test area and the second test area.
Optionally, the first test area is provided with a plurality of first signal input terminals, among the serially connected test shorting bars, a first test shorting bar and a last test shorting bar are connected to the corresponding first signal input terminals through leads, and the leads cross the cutting lines;
the first test area is provided with a plurality of second signal input terminals, and each test short-circuit rod is further connected with the corresponding second signal input terminal.
Optionally, the test shorting bar comprises a first shorting bar and a second shorting bar, the signal lines comprise a first signal line and a second signal line which are alternately arranged,
the first shorting bar is connected to the first signal line, and the second shorting bar is connected to the second signal line.
Optionally, the first shorting bar and the first signal line are disposed in the same layer and connected; the second short-circuit rod and the second signal line are arranged on different layers and connected.
Optionally, the first shorting bar, the first signal line, and the second signal line are formed in synchronization with a gate layer of the array substrate motherboard, and the second shorting bar is formed in synchronization with a data line of the array substrate motherboard.
Optionally, the second shorting bar and the second signal line are connected by a metal layer bridge.
Optionally, the metal layer is connected to the second shorting bar through a first via hole, and is connected to the second signal line through a second via hole.
Optionally, the size of the first via and the second via in the first direction is greater than or equal to 18 μm and less than or equal to 20 μm; a dimension in a direction perpendicular to the first direction is greater than or equal to 28 μm and less than or equal to 32 μm.
In order to solve the above problem, the present invention further discloses an array substrate, wherein the array substrate is obtained by cutting the array substrate motherboard according to any of the above embodiments along the cutting line, and includes the second test area.
In order to solve the above problem, the present invention further discloses a display device, including the above array substrate.
Compared with the prior art, the invention has the following advantages:
the application provides an array substrate, an array substrate mother board and a display device, wherein the array substrate mother board comprises a first test area and a second test area which are divided by a cutting line, a plurality of test units are arranged in the second test area, each test unit comprises a test short-circuit bar and a plurality of signal lines connected to the test short-circuit bar, and the test short-circuit bar is used for inputting detection signals to the signal lines; the test short-circuit bars of each test unit are sequentially connected in series through a series connection line, and the series connection line crosses the cutting line; the Array test before the cutting process and the Cell test after the cutting process are carried out through the same testing short-circuit rod, so that the defect of the testing short-circuit rod can be detected in the Array test stage, the next procedure is avoided flowing in, the abnormal lighting picture caused by the defect of the testing short-circuit rod is avoided in the Cell test stage, and the productivity and the yield of the Cell test stage are further improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments of the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive labor.
Fig. 1 is a schematic structural diagram illustrating an array substrate motherboard in the prior art;
fig. 2 is a block diagram illustrating a structure of a motherboard of an array substrate according to an embodiment of the present disclosure;
fig. 3 is a schematic plan view illustrating a motherboard of an array substrate according to an embodiment of the present disclosure;
fig. 4 is a schematic plan view illustrating a second shorting bar and a second signal line connected by a metal layer bridge according to an embodiment of the present disclosure;
FIG. 5 is a schematic cross-sectional view illustrating a second shorting bar and a second signal line connected by a metal layer bridge according to an embodiment of the present disclosure;
fig. 6 is a schematic plan view illustrating a cut array substrate motherboard according to an embodiment of the present disclosure;
description of reference numerals:
11-Array test shorting bar in prior art; 12-Cell test shorting bar in prior art; 13-cutting line in the prior art; 21-a cutting line; 22-a first test area; 23-a second test area; 24-a test unit; 25-a signal line; 26-test shorting bar; 27-a series connection; 261-a first shorting bar; 262-a second shorting bar; 251-a first signal line; 252-a second signal line; 31-a lead; 311-a first lead; 312 — a second lead; 32-a first signal input terminal; 321-a first even signal input terminal; 322-first odd signal input terminal; 33-second signal input terminal; 331-a second even signal input terminal; 332-second odd signal input terminal; 41-a metal layer; 42-a first via; 43-second via.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
In the manufacturing process of the display panel, referring to fig. 1, the Array test shorting bar 11 is generally used to perform the poor electrical performance detection on the Array substrate in the Array test stage. The Cell test is a post-Cell test, and generally, a display screen of a display panel is inspected by using a Cell test shorting bar 12 to detect poor electrical properties and poor visibility. The conventional Array test shorting bar 11 and Cell test shorting bar 12 are located in two regions divided by a cutting line 13, and since the Array test shorting bar 11 and the Cell test shorting bar 12 are separately arranged, the defects of the Cell test shorting bar 12 cannot be detected in the Array test stage, which results in abnormal lighting pictures in the Cell test stage.
In order to solve this problem, an embodiment of the present application provides an array substrate motherboard, and referring to fig. 2, the array substrate motherboard may include: a first test area 22 and a second test area 23 divided by the cutting line 21, wherein a plurality of test units 24 are arranged in the second test area 23, each test unit 24 comprises a test shorting bar 26 and a plurality of signal lines 25 connected to the test shorting bar 26, and the test shorting bar 26 is used for inputting detection signals to the signal lines 25; the test shorting bars 26 of each test unit 24 are serially connected in sequence through a serial connection line 27, and the serial connection lines 27 cross the cutting line 21 and are distributed in the first test area 22 and the second test area 23.
It should be noted that the array substrate motherboard described in this embodiment is described by taking an example of obtaining an array substrate after being cut along the cutting line 21. The plurality of test units 24 may correspond to a plurality of bonding binding regions on the array substrate, and the setting number and size of a specific test unit may be determined according to the strength of the input signal and the size of the array substrate, which is not specifically limited in this application.
In practical applications, the connection manner of the test shorting bar 26 and the signal lines 25 may be various, for example, the test shorting bar 26 may be a shorting bar that is disposed across the signal lines 25 and connected to all the signal lines 25; it is also possible to include a first shorting bar arranged to intersect the signal lines 25 and connected to the signal lines 25 of the even-numbered columns and a second shorting bar connected to the signal lines 25 of the odd-numbered columns, etc., and for the latter implementation, reference may be made to the description of the subsequent embodiments.
Before the Array substrate mother board is cut, an Array test signal can be input to the test shorting bar 26 through the Array test signal input terminal, and then the Array test signal is output to the signal line 25 through the test shorting bar 26, so that the Array substrate is tested. The Array test signal input terminal may be located in the first test area 22 or the second test area 23. Furthermore, the entire Array substrate motherboard may share one Array test signal input terminal, or a plurality of Array test signal input terminals may be provided to connect with the test shorting bars 26 in order to prevent signal attenuation, for example, the test shorting bars 26 of each test unit 24 are each connected to one Array test signal input terminal, or only the first and last test shorting bars 26 of the test shorting bars 26 connected in series are connected to the Array test signal input terminals.
After the above-described array substrate mother substrate is subjected to a cutting process along the cutting lines 21, a Cell test may be performed using the same test shorting bar 26. In the Cell test stage, a Cell test signal is input to the test shorting bar 26 through the Cell test signal input terminal, and then output to the signal line 25 through the test shorting bar 26. The Cell test signal input terminal may be located at the second test area 23. Since the serial line 27 is cut off in the dicing process, the plurality of test cells 24 are no longer connected in series, and therefore, each test Cell 24 is connected to at least one Cell test signal input terminal.
In this embodiment, through the same test shorting bar, Array test before the cutting process and Cell test after the cutting process can be carried out, so that the defect of the test shorting bar itself can be detected in the Array test stage, the next procedure is avoided flowing in, the abnormal lighting picture caused by the defect of the shorting bar in the Cell test stage is avoided, and the productivity and the yield of the Cell test stage are further improved.
In one implementation manner of this embodiment, referring to fig. 3, the test shorting bar 26 may include a first shorting bar 261 and a second shorting bar 262, the signal line 25 may include a first signal line 251 and a second signal line 252 alternately arranged, the first shorting bar 261 is connected to the first signal line 251, and the second shorting bar 262 is connected to the second signal line 252. By providing the first short bar 261 and the second short bar 262, it is possible to detect not only a failure of the test short bar itself in the Array test stage but also a failure such as dds (data and data short) in the Array test stage.
The first signal line 251 can be connected with the data lines in the even-numbered rows on the array substrate motherboard, and the second signal line 252 can be connected with the data lines in the odd-numbered rows on the array substrate motherboard; or the first signal line 251 is connected with the data lines of odd-numbered rows on the array substrate motherboard, and the second signal line 252 is connected with the data lines of even-numbered rows on the array substrate motherboard. Fig. 3 illustrates the first case.
Specifically, the first shorting bar 261 may be disposed in the same layer as the first signal line 251 and connected thereto; the second shorting bar 262 is disposed at a different layer from and connected to the second signal line 252. In this implementation manner, the first shorting bar 261 and the first signal line 251 are disposed on the same layer and connected, and a via hole switching signal is not needed, so that ITO Open failure of a via hole does not occur. It should be noted that the connection between the first shorting bar 261 and the first signal line 251, and the connection between the second shorting bar 262 and the second signal line 252 are not limited to this connection, and for example, the first shorting bar 261 and the first signal line 251 may be disposed and connected in different layers, and the second shorting bar 262 and the second signal line 252 may be disposed and connected in different layers; or the first shorting bar 261 and the first signal line 251 and the second shorting bar 262 and the second signal line 252 are disposed in different layers and connected, and the specific connection manner may be determined according to an actual structure and a process, which is not specifically limited in this application.
When the first shorting bar 261 is disposed on the same layer as the first signal line 251 and connected thereto; when the second shorting bar 262 and the second signal line 252 are disposed in different layers and connected to each other, the following specific structure may be implemented: the first shorting bar 261, the first signal line 251, and the second signal line 252 are formed in synchronization with the gate layer of the array substrate motherboard, and the second shorting bar 262 is formed in synchronization with the data line of the array substrate motherboard. In this case, the second shorting bar 262 and the second signal line 252 may be connected by a metal layer bridge, and may also be connected by a via hole provided on an insulating layer (e.g., a gate insulating layer between a data line layer and a gate layer) between the second shorting bar 262 and the second signal line 252.
Referring to fig. 4 and 5, a schematic plan view and a schematic cross-sectional view along AA' of the second shorting bar and the second signal line connected by the metal layer bridge are respectively shown. The metal layer bridging connection means that the metal layer 41 is connected to the second shorting bar 262 through the first via 42, and the metal layer 41 is connected to the second signal line 252 through the second via 43. Specifically, the metal layer 41 may be ITO (indium tin oxide) or the like.
In the prior art, the size of a via hole on the Cell testing shorting bar 12 is about (8-10 μm) by (10-12 μm), and Open failure is easy to occur in the production process. This is because the metal layer (e.g., ITO) at the via hole is a ring around the hole, and is easily broken by external forces during the process such as cutting and grinding, and when the via hole is small in size, there is a high possibility of complete Open. In order to avoid Open failures at the first via 42 and the second via 43, the first via 42 and the second via 43 may have a size of (18-20 μm) × (28-32 μm), and as shown in fig. 4, the shape may be made rectangular, i.e., the size in the first direction is greater than or equal to 18 μm and less than or equal to 20 μm; the dimension in the direction perpendicular to the first direction is greater than or equal to 28 μm and less than or equal to 32 μm. Since the signal transmission is not greatly affected by the metal layer fracture, the larger the via hole is, the lower the possibility of complete Open is. The first direction may be, for example, a direction parallel to the gate lines in the array substrate motherboard, and a direction perpendicular to the first direction may be a direction parallel to the data lines.
In this embodiment, since the first shorting bar 261 and the first signal line 251 are disposed on the same layer, via opening failure does not occur, and the first via hole 42 and the second via hole 43 connecting the second shorting bar 262 and the second signal line 252 can reduce the probability of via opening completely by adopting a large-size via hole design. That is, the present embodiment minimizes the probability of occurrence of abnormal false lighting failure due to a test shorting bar failure. Moreover, even if Open defects occur at the via holes in the Array process, the Open defects can be detected in the Array test stage, and the defective Array substrate mother board can be subjected to welding repair and then put into the next process.
Referring to fig. 3, an implementation of the Array test signal input terminal and the Cell test signal input terminal in the present embodiment is also shown. The first test area 22 is provided with a plurality of first signal input terminals 32, among the test shorting bars 26 connected in series, the first test shorting bar and/or the last test shorting bar are connected to the corresponding first signal input terminals 32 through leads 31, and the leads 31 cross the cutting lines 21; the first test area 22 is provided with a plurality of second signal input terminals 33, and each test shorting bar 26 is also connected to a corresponding second signal input terminal 33.
Among them, the first signal input terminal 32 may include a first even signal input terminal 321 connected to the first shorting bar 261 and a first odd signal input terminal 322 connected to the second shorting bar 262. The second signal input terminal 33 may include a second even signal input terminal 331 connected to the first shorting bar 261 and a second odd signal input terminal 332 connected to the second shorting bar 262. In order to reduce the influence of signal attenuation on the test results, the first test shorting bar and the last test shorting bar may be connected to the first signal input terminal 32 through the lead 31, as shown in fig. 3. Also, the second signal input terminals 33 may be provided in each of the test units 24 on both left and right sides of the test shorting bar 26, respectively, to reduce the influence of signal attenuation.
The lead lines 31 may include a first lead line 311 connecting the first even-numbered signal input terminal 321 and the first shorting bar 261, and a second lead line 312 connecting the first odd-numbered signal input terminal 322 and the second shorting bar 262.
The second signal input terminal 33 may be provided on the test shorting bar 26 in the second test region 23 or on the serial line 27 or the lead 31 connected to the test shorting bar 26. The second signal input terminal 33 is located in the second testing region 23 and connected to the testing shorting bar 26, and the specific location thereof is not limited in the present application.
The first testing short-circuit bar refers to the first testing short-circuit bar in the testing short-circuit bars connected in series, and may be the testing short-circuit bar in the leftmost testing unit in fig. 3; the last test shorting bar refers to the last test shorting bar in the test shorting bars connected in series, and may be the test shorting bar in the rightmost test unit in fig. 3. It should be noted that the first bit and the last bit are relatively general and can be defined according to specific situations.
In the following, with reference to the above-mentioned Array substrate motherboard, the signal transmission process in the Array test stage and the Cell test stage will be described separately by taking the example that the second signal input terminal is disposed on the test shorting bar in the second test area.
In the Array test phase, the signals for testing the first signal line 251 are transferred as follows: the Array test signal probe → the first even-numbered signal input terminal 321 → the first lead line 311 → the first shorting bar 261 → the second even-numbered signal input terminal 331 → the first shorting bar 261 → the first signal line 251; the signals for testing the second signal line 252 are passed as follows: the Array test signal probe → the first odd-numbered signal input terminal 322 → the second lead 312 → the second shorting bar 262 → the second odd-numbered signal input terminal 332 → the second shorting bar 262 → the first via 42 → the second via 43 → the second signal line 252.
In the Cell test phase, referring to fig. 6, the first test areas 22 located outside the cutting lines 21 are cut away and the test shorting bars 26 of the respective test cells 24 are not connected in series. The signals for testing the first signal line 251 are transferred as follows: cell test signal probe → the second even-numbered signal input terminal 331 → the first shorting bar 261 → the first signal line 251; the signals for testing the second signal line 252 are passed as follows: cell test signal probe → the second odd-numbered signal input terminal 332 → the second shorting bar 262 → the first via hole 42 → the second via hole 43 → the second signal line 252.
Another embodiment of the present application further provides an array substrate, which may be a substrate including the second test area and obtained by cutting the array substrate motherboard according to any one of the above-mentioned embodiments along the cutting line, as shown in fig. 6.
Another embodiment of the present application further provides a display device, which may include the array substrate.
The embodiment of the application provides an array substrate, an array substrate motherboard and a display device, wherein the array substrate motherboard comprises a first test area and a second test area which are divided by a cutting line, a plurality of test units are arranged in the second test area, each test unit comprises a test short-circuit bar and a plurality of signal lines connected to the test short-circuit bar, and the test short-circuit bar is used for inputting detection signals to the signal lines; the test short-circuit bars of each test unit are sequentially connected in series through a series connection line, and the series connection line crosses the cutting line; the Array test before the cutting process and the Cell test after the cutting process are carried out through the same testing short-circuit rod, so that the defect of the testing short-circuit rod can be detected in the Array test stage, the next procedure is avoided flowing in, the abnormal lighting picture caused by the defect of the testing short-circuit rod is avoided in the Cell test stage, and the productivity and the yield of the Cell test stage are further improved.
The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The array substrate, the array substrate motherboard and the display device provided by the invention are described in detail, specific examples are applied in the description to explain the principle and the implementation mode of the invention, and the description of the above embodiments is only used to help understanding the method and the core idea of the invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (8)
1. An array substrate mother board is characterized by comprising a first test area and a second test area which are divided by a cutting line, wherein a plurality of test units are arranged in the second test area, each test unit comprises a test short-circuit bar and a plurality of signal lines connected to the test short-circuit bar, and the test short-circuit bar is used for inputting detection signals to the signal lines;
the test short-circuit bars of each test unit are sequentially connected in series through a series connection line, and the series connection line crosses the cutting line and is distributed in the first test area and the second test area;
the first test area is provided with a plurality of first signal input terminals, the first test short-circuit bar and the last test short-circuit bar in the test short-circuit bars connected in series are connected to the corresponding first signal input terminals through lead wires, and the lead wires cross the cutting lines;
the first test area is provided with a plurality of second signal input terminals, and each test short-circuit rod is also connected with the corresponding second signal input terminal;
the test shorting bar comprises a first shorting bar and a second shorting bar, the signal lines comprise a first signal line and a second signal line which are alternately arranged,
the first shorting bar is connected to the first signal line, and the second shorting bar is connected to the second signal line.
2. The array substrate motherboard of claim 1, wherein the first shorting bar is disposed and connected to the first signal line in the same layer; the second short-circuit rod and the second signal line are arranged on different layers and connected.
3. The array substrate motherboard of claim 2, wherein the first shorting bar, the first signal line, and the second signal line are formed in synchronization with a gate layer of the array substrate motherboard, and the second shorting bar is formed in synchronization with a data line of the array substrate motherboard.
4. The array substrate motherboard of claim 2, wherein the second shorting bar is connected to the second signal line by a metal layer bridge.
5. The array substrate motherboard of claim 4, wherein the metal layer is connected to the second shorting bar through a first via and to the second signal line through a second via.
6. The array substrate motherboard of claim 5, wherein the first and second vias have a dimension in the first direction that is greater than or equal to 18 μ ι η and less than or equal to 20 μ ι η; a dimension in a direction perpendicular to the first direction is greater than or equal to 28 μm and less than or equal to 32 μm.
7. An array substrate, wherein the array substrate is a substrate including the second test region, which is obtained by cutting the array substrate motherboard according to any one of claims 1 to 6 along the cutting line.
8. A display device comprising the array substrate according to claim 7.
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| CN111176001B (en) * | 2020-01-14 | 2021-02-23 | 深圳市华星光电半导体显示技术有限公司 | Liquid crystal display panel and testing method thereof |
| CN111338139B (en) * | 2020-02-18 | 2023-11-24 | 合肥鑫晟光电科技有限公司 | Display substrate and display device |
| CN111653548A (en) * | 2020-06-18 | 2020-09-11 | 京东方科技集团股份有限公司 | Display substrate, display panel and preparation method thereof |
| CN111900174A (en) * | 2020-07-27 | 2020-11-06 | 滁州惠科光电科技有限公司 | Array substrate, manufacturing method thereof and display device |
| CN112068365A (en) * | 2020-09-02 | 2020-12-11 | 深圳市华星光电半导体显示技术有限公司 | Display panel |
| CN113554961B (en) * | 2021-07-06 | 2024-03-19 | 深圳市华星光电半导体显示技术有限公司 | Display panel |
| CN114578594B (en) * | 2022-03-03 | 2023-11-28 | Tcl华星光电技术有限公司 | Array substrate, display module thereof and manufacturing method |
| CN115167021B (en) * | 2022-08-05 | 2023-07-25 | 苏州华星光电技术有限公司 | Display panel detection method and detection device |
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2018
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