CN113823574A - Power type chip packaging method - Google Patents
Power type chip packaging method Download PDFInfo
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- CN113823574A CN113823574A CN202111389549.0A CN202111389549A CN113823574A CN 113823574 A CN113823574 A CN 113823574A CN 202111389549 A CN202111389549 A CN 202111389549A CN 113823574 A CN113823574 A CN 113823574A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 32
- 238000000034 method Methods 0.000 title claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 51
- 230000001681 protective effect Effects 0.000 claims abstract description 46
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 9
- 238000004080 punching Methods 0.000 claims description 2
- 230000017525 heat dissipation Effects 0.000 abstract description 33
- 230000000694 effects Effects 0.000 abstract description 10
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 230000020169 heat generation Effects 0.000 description 16
- 239000002184 metal Substances 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 238000000137 annealing Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 238000001035 drying Methods 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000005488 sandblasting Methods 0.000 description 2
- 238000005245 sintering Methods 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
- H01L23/467—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing gases, e.g. air
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The application belongs to the technical field of semiconductor packaging, and particularly discloses a power type chip packaging method, which comprises the following steps: configuring a packaging bottom plate; configuring a protective shell; the packaging bottom plate and the protective shell are formed in a hot connection mode; configuring a package substrate includes: determining a geometric center on the substrate, wherein the geometric center is used as two vertical axes to divide the substrate into four regions, one region is a low heat generating element region, and two regions adjacent to the low heat generating element region are a high heat generating high heat-resistant element region and a high heat generating low heat-resistant element region respectively; configuring the protective case includes: a concentrated outer conducting area with relatively thin thickness is formed in the middle of the protective shell, and the straight conducting area extends from the high-yield high-endurance area to the concentrated outer conducting area; forming a ring-shaped ring guide area with relatively thin thickness around the high-yield low-tolerance area; before the packaging bottom plate and the protective shell are formed in a hot joint mode, the power type chip is fixed on the substrate, and the packaging bottom plate and the protective shell are formed in a hot joint mode. The structure of the package is reserved to ensure the safety of the power type chip package, and the heat dissipation effect is excellent.
Description
Technical Field
The present invention relates to semiconductor packaging, and more particularly, to a power chip packaging method.
Background
The packaging method and related packaging structure of power type chip are relatively solidified in the prior art, for example, the related patent documents are representative of the technical content, the chinese patent application CN200910032590.5 discloses the packaging method for high power chip, the core of the technology is that a hole with a size slightly smaller than that of a copper base is drilled on a metal substrate, the copper base is embedded into the metal substrate, printing soldering paste on the copper base and the metal substrate, respectively mounting the chip and the terminal pin on the copper base and the metal substrate, sintering the chip, the terminal pin, the copper base and the metal substrate in a sintering furnace at the temperature of 210-230 ℃, bonding the chip and the terminal pin through a metal wire, checking whether the wire is stripped or not or bonding is missed under a microscope, coating glue on the surface of the chip, sealing the chip, covering the metal substrate with a shell, cutting ribs of the terminal pins, bending, testing the open short circuit condition, encapsulating and drying.
In this technology, the chip is exposed on the substrate, which is more beneficial to heat dissipation in practice, but the packaging method or structure of this technology frame also has many disadvantages, for example, the package also needs a package, which is a safety protection cover in practice, so that some safety protection problems can be solved, but the package may greatly reduce the heat dissipation effect, and is not beneficial to heat dissipation because the package is closed; therefore, a package technology which can not only maintain the structure of the package to ensure safety, but also has obvious heat dissipation effect is lacked in the prior art.
Disclosure of Invention
In order to overcome the defects in the prior art, the application provides a power type chip packaging method.
The technical scheme adopted by the application for solving the technical problem is as follows: a power die packaging method, comprising: configuring a packaging bottom plate; configuring a protective shell; the packaging bottom plate and the protective shell are formed in a hot connection mode;
wherein the configuration package substrate comprises: determining a geometric center on the substrate, and dividing the substrate into four regions by making two vertical axes through the geometric center, wherein one region is a low heat generating element region, and two regions adjacent to the low heat generating element region are a high heat generating high heat-resistant element region and a high heat generating low heat-resistant element region respectively; arranging corresponding element fixing holes on the high-heat-yield high-heat-resistance element area, the low-heat-generation element area and the high-heat-yield low-heat-resistance element area; wherein the high heat-producing high heat-resistant element region is specifically a region where a high heat-producing high heat-resistant element or a high heat-producing high heat-resistant chip is placed, wherein the low heat-producing element region is specifically a region where a low heat-producing element or a low heat-producing chip is placed, and wherein the high heat-producing low heat-resistant element region is specifically a region where a high heat-producing low heat-resistant element or a high heat-producing low heat-resistant chip is placed;
configuring the protective case includes: processing a substrate into a protective shell, forming a concentrated outer conducting area with relatively thin thickness in the middle of the protective shell, forming a high-yield high-endurance area and a high-yield low-endurance area on two sides of the concentrated outer conducting area respectively, forming a low-yield area in the middle of the high-yield high-endurance area and the high-yield low-endurance area and at a position which is not the concentrated outer conducting area, forming a strip-shaped straight conducting area with relatively thin thickness on two sides of the high-yield high-endurance area respectively, and extending the straight conducting area from the high-yield high-endurance area to the concentrated outer conducting area; forming a ring-shaped ring guide area with relatively thin thickness around the high-yield low-tolerance area;
before the packaging bottom plate and the protective shell are subjected to thermal bonding forming, the power type chip is fixed on the substrate, the high heat-resistant end of the power type chip is arranged in the high heat-production high heat-resistant element area, and the low heat-resistant end of the power type chip is arranged in the high heat-production low heat-resistant element area; the protection shell is firstly buckled on the substrate, and the part right below the high-yield high-resistance area is closest to the high-heat-production high-heat-resistance element area, the part right below the low-yield area is closest to the low-heat-production element area, the part right below the high-yield low-resistance area is closest to the high-heat-production low-heat-resistance element area, and the part right below the concentrated outer conducting area is closest to the geometric center; and then the packaging bottom plate and the protective shell are subjected to thermal bonding forming.
Furthermore, the ring guide area, the centralized external guide area and the straight guide area can be integrally formed on the protection shell in a punching mode.
Furthermore, the cross-sectional shapes of the substrate and the protective shell in a plan view are both square.
Further, the step of fixing the power chip on the substrate before the package base plate is thermally connected and molded with the protective shell further includes fixing other elements on the substrate.
Furthermore, the configuration package bottom plate also comprises a lead hole and a lead which are formed on the periphery of the substrate.
Further, when the element heat generation efficiency of the high heat-generating high heat-resistant element region is measured to be V1, the element heat generation efficiency of the low heat-generating element region is V2, the element heat generation efficiency of the high heat-generating low heat-resistant element region is V3, the heat dissipation efficiency of the high yield high heat-resistant region is V5, the comprehensive heat dissipation efficiency of the direct conduction region is V6, the total heat dissipation efficiency of the concentrated external conduction region is V7, the comprehensive heat dissipation efficiency of the ring conduction region is V8, the heat dissipation efficiency of the high yield low heat-resistant region is V9, the heat dissipation efficiency of the low yield region is V10, the comprehensive improved heat dissipation efficiency of the concentrated external conduction region to the high yield high heat-resistant region is V71, the comprehensive improved heat dissipation efficiency of the concentrated external conduction region to the high yield low heat-resistant region is V72 before the ring conduction region, the ring conduction region is first configured, then, a direct conducting region is configured, and then a concentrated external conducting region is configured, so that V9 + V8 + V72 is more than V3, V5 + V6 + V71 is more than or equal to V1, and V7 + V6 + V8 + V5 + V9 + V10 is more than or equal to V1 + V2 + V3.
Further, the first configuration of the ring guide region, the second configuration of the straight guide region, and the second configuration of the concentrated outer guide region includes first configuring a thickness and a specific region of the ring guide region and making a thickness of the ring guide region thinner than that of the protection shell or the high yield and low withstand voltage region, then configuring a thickness and a specific region of the straight guide region and making a thickness of the straight guide region thinner than that of the protection shell or the high yield and high withstand voltage region, and then configuring a thickness and a specific region of the concentrated outer guide region and making a thickness of the concentrated outer guide region thinner than that of the straight guide region and the ring guide region.
Further, the configuring of the ring guide region, the configuring of the straight guide region, and the configuring of the concentrated outer guide region further specifically include configuring a material of the ring guide region and/or a material of the straight guide region and/or a material of the concentrated outer guide region.
The beneficial effects of this application are that, this application is leading district or straight leading district or concentrating in the implementation and leading the district outward and all can realize radiating effect, especially this application can be in concentrating the regional from the bottom up's that leads the district under outside the hot-air flow of great region, and the ring leads district and leads the regional from the bottom up's that forms less region under district under with directly, and lead the district to concentrating the hot-air flow that also can form the horizontal direction outside leading district below from the ring, and it also can form the hot-air flow of horizontal direction to concentrate the district below leading outside to lead directly, like this can form the outside route that flows of directional hot-air at the protection casing of this application, and can actually improve radiating effect.
Particularly, the area below the high-heat-generation low-heat-resistance area can perform heat dissipation with the highest priority in the implementation of the present application (namely, the area of the high-heat-generation low-heat-resistance element, namely, the area where the high-heat-generation low-heat-resistance element or the high-heat-generation low-heat-resistance chip is placed), and secondly, the area below the high-heat-generation high-heat-resistance area and the area below the low-heat-generation area can also perform good heat dissipation effects, so that the high-heat-generation low-heat-resistance element or the high-heat-generation low-heat-resistance chip can perform heat dissipation with priority firstly, and the maximum safety of the chip or the element in operation can be ensured.
The heat dissipation device can ensure that the heat dissipation efficiency of the concentrated outer conducting area can meet the total requirement, can also ensure that the heat generation of the element in the independent high-heat-yield high-heat-resistance element area can be effectively dissipated, can also determine that the heat generation of the element in the independent high-heat-yield low-heat-resistance element area can be effectively dissipated, and the like.
The package structure can be reserved to ensure the safety of the power type chip package, and the heat dissipation effect is excellent.
Drawings
The present application is further described below with reference to the drawings and examples.
Fig. 1 is a schematic view of the substrate structure of the present application.
Fig. 2 is a schematic structural view of the protective case of the present application.
Fig. 3 is a schematic structural diagram of the protection case of the present application after the chip is packaged.
In the figure:
a protective case 101; a substrate 102; a high yield high endurance region 103; a low-yield zone 104; a concentrated outer conductive region 105; a high yield low-tolerance region 106; a loop-guiding region 107; a straight conductive region 108; high heat generation, high heat resistance element region 1020; a low heat generating element region 1021; geometric center 1023; high heat generation low heat resistant element region 1024.
Detailed Description
In specific implementation, the power chip packaging method of the present application mainly includes: configuring a packaging bottom plate; configuring a protective shell; the packaging bottom plate and the protective shell are formed in a hot connection mode; wherein the configuration package substrate comprises: as shown in fig. 1, a geometric center 1023 is defined on the substrate 102, and the substrate 102 is divided into four regions by the geometric center 1023 as two perpendicular axes, one region is a low heat-generating element region 1021, and two regions adjacent to the low heat-generating element region 1021 are a high heat-generating high heat-resistant element region 1020 and a high heat-generating low heat-resistant element region 1024, respectively; corresponding element fixing holes are arranged on the high heat-generation high heat-resistance element region 1020, the low heat-generation element region 1021 and the high heat-generation low heat-resistance element region 1024; wherein high heat resistant element region 1020 is specifically a region where a high heat resistant element or a high heat resistant chip is placed, wherein low heat generating element region 1021 is specifically a region where a low heat generating element or a low heat generating chip is placed, wherein high heat low heat resistant element region 1024 is specifically a region where a high heat low heat resistant element or a high heat low heat resistant chip is placed; in practice, the substrate 102 is further subjected to a process such as sandblasting, annealing, oxidation, and the like, and then subjected to a conventional process such as cleaning, drying, plating, and the like.
In practice, configuring the protective case comprises: as shown in fig. 2, a protective casing 101 is formed by processing a substrate, a concentrated outer conductive region 105 with a relatively thin thickness is formed in the middle of the protective casing 101, a high-yield high-withstand voltage region 103 and a high-yield low-withstand voltage region 106 are respectively formed on both sides of the concentrated outer conductive region 105, a low-yield region 104 is formed in the middle of the high-yield high-withstand voltage region 103 and the high-yield low-withstand voltage region 106 and at a position not concentrated by the concentrated outer conductive region 105, an elongated straight conductive region 108 with a relatively thin thickness is respectively formed on both sides of the high-yield high-withstand voltage region 103, and the straight conductive region 108 extends from the high-yield high-withstand voltage region 103 to the concentrated outer conductive region 105; forming a ring-shaped and relatively thin loop-guiding region 107 around the high yield low-resistance region 106; in practice, the corresponding protective housing 101 is also treated by conventional processes such as annealing and electroplating. In a preferred embodiment, the ring guide region 107, the concentrated outer guide region 105, and the straight guide region 108 may be integrally formed on the protection housing 101.
In a preferred embodiment, the cross-sectional shapes of the substrate 102 and the protective casing 101 are both square, and may be triangular.
Before the thermal molding of the package base and the protective shell is performed, as shown in fig. 3, the power chip is fixed on the substrate 102, and the high heat-resistant end of the power chip is placed in the high heat-generating high heat-resistant element region 1020, and the low heat-resistant end of the power chip is placed in the high heat-generating low heat-resistant element region 1024; the protective shell 101 is firstly buckled on the substrate 102, and the protective shell is made to be closest to a high heat-generating and high heat-resisting element area 1020 under the high-yield and high-resistance area 103, to be closest to a low heat-generating element area 1021 under the low-yield area 104, to be closest to a high heat-generating and low heat-resisting element area 1024 under the high-yield and low-resistance area 106, and to be closest to a geometric center 1023 under the concentrated outer conducting area 105; and then the packaging bottom plate and the protective shell are subjected to thermal bonding forming.
In the present application, the single protection casing 101, the ring guide area 107, the straight guide area 108, or the concentrated outer guide area 105 may achieve a heat dissipation effect, and particularly, the present application may form a large area of hot air flow from bottom to top directly under the concentrated outer guide area 105, and form a small area of hot air flow from bottom to top directly under the ring guide area 107 and the straight guide area 108, and also form a horizontal hot air flow from the ring guide area 107 to the lower part of the concentrated outer guide area 105, and also form a horizontal hot air flow from the straight guide area 108 to the lower part of the concentrated outer guide area 105, so that a directional hot air outward flow path may be formed in the protection casing 101 of the present application, and a heat dissipation effect may be actually improved.
In particular, in the present application, the area below the high heat-generating low-temperature resistant area 106 can perform the most preferential heat dissipation (i.e. the high heat-generating low-temperature resistant element area 1024, i.e. the area where the high heat-generating low-temperature resistant element or the high heat-generating low-temperature resistant chip is placed), and then the area below the high heat-generating high-temperature resistant area 103 and the area below the low-temperature resistant area 104 can also perform the good heat dissipation effect, so that the high heat-generating low-temperature resistant element or the high heat-generating low-temperature resistant chip can firstly perform the preferential heat dissipation, and the maximum safety of the chip or the element operation can be ensured.
Further, preferably, the configuring of the package substrate in the power type chip packaging method of the present application includes: defining a geometric center 1023 on the substrate 102, dividing the substrate 102 into four regions by two perpendicular axes passing through the geometric center 1023, one region being a low heat-generating element region 1021, and two regions adjacent to the low heat-generating element region 1021 being a high heat-generating high heat-resistant element region 1020 and a high heat-generating low heat-resistant element region 1024, respectively; corresponding element fixing holes are arranged on the high heat-generation high heat-resistance element region 1020, the low heat-generation element region 1021 and the high heat-generation low heat-resistance element region 1024; wherein high heat resistant element region 1020 is specifically a region where a high heat resistant element or a high heat resistant chip is placed, wherein low heat generating element region 1021 is specifically a region where a low heat generating element or a low heat generating chip is placed, wherein high heat low heat resistant element region 1024 is specifically a region where a high heat low heat resistant element or a high heat low heat resistant chip is placed; the implementation of the bottom plate for packaging also includes forming lead holes and leads around the substrate 102, and the substrate 102 is further processed by sand blasting, annealing, oxidation, and other processes, and then is further processed by conventional processes such as cleaning, drying, electroplating, and the like.
In practice, configuring the protective case comprises: processing a substrate into a protective shell 101, forming a concentrated outer conducting region 105 with a relatively thin thickness in the middle of the protective shell 101, forming a high-yield high-withstand voltage region 103 and a high-yield low-withstand voltage region 106 on two sides of the concentrated outer conducting region 105, respectively forming a low-yield region 104 in the middle of the high-yield high-withstand voltage region 103 and the high-yield low-withstand voltage region 106 and at a position other than the concentrated outer conducting region 105, forming a strip-shaped straight conducting region 108 with a relatively thin thickness on two sides of the high-yield high-withstand voltage region 103, respectively, wherein the straight conducting region 108 extends from the high-yield high-withstand voltage region 103 to the concentrated outer conducting region 105; forming a ring-shaped and relatively thin loop-guiding region 107 around the high yield low-resistance region 106; in practice, the corresponding protective housing 101 is also treated by conventional processes such as annealing and electroplating.
The heat generation efficiency of the high heat-generating high heat-resisting element region 1020 is V1, the heat generation efficiency of the low heat-generating element region 1021 is V2, the heat generation efficiency of the high heat-generating low heat-resisting element region 1024 is V3, the heat dissipation efficiency of the high-yield high-withstand region 103 is V5, the comprehensive heat dissipation efficiency of the straight conducting region 108 is V6, the total heat dissipation efficiency of the concentrated outer conducting region 105 is V7, the comprehensive heat dissipation efficiency of the ring conducting region 107 is V8, the heat dissipation efficiency of the high-yield low-withstand region 106 is V9, the heat dissipation efficiency of the low-yield region 104 is V10, the comprehensive improved heat dissipation efficiency of the concentrated outer conducting region 105 to the high-yield high-withstand region 103 is V71, the comprehensive improved heat dissipation efficiency of the concentrated outer conducting region 105 to the high-yield low-withstand region 106 is V6338, the ring conducting region 107 is configured first, the straight conducting region 108 is configured, the concentrated outer conducting region 105 is configured, the V6348 + V8 + V5 is greater than or equal to V638 and more than V638, and V7 + V6 + V8 + V5 + V9 + V10 is more than or equal to V1 + V2 + V3.
This sample application can ensure that the heat dissipation efficiency of the centralized conductive region 105 can meet the overall requirements, that heat generated by the components of the individual high heat-producing high heat-resistant component regions 1020 can be effectively dissipated, that heat generated by the components of the individual high heat-producing low heat-resistant component regions 1024 can be effectively dissipated, and the like.
In implementation, the first configuration of the ring conducting region 107, the second configuration of the straight conducting region 108, and the second configuration of the concentrated conducting region 105 are specifically configured by first configuring the thickness and specific area of the ring conducting region 107 and making the thickness of the ring conducting region 107 thinner relative to the protection housing 101 or the high-yield low-resistance region 106, then configuring the thickness and specific area of the straight conducting region 108 and making the thickness of the straight conducting region 108 thinner relative to the protection housing 101 or the high-yield high-resistance region 103, and then configuring the thickness and specific area of the concentrated conducting region 105 and making the thickness of the concentrated conducting region 105 thinner relative to the thickness of the straight conducting region 108 and the ring conducting region 107; further, the configuring of the ring guide region 107, the configuring of the straight guide region 108, and the configuring of the concentrated outer guide region 105 further specifically include configuring a material of the ring guide region 107 and/or configuring a material of the straight guide region 108 and/or configuring a material of the concentrated outer guide region 105.
Fixing the power chip on the substrate 102 before performing thermal bonding molding of the package substrate and the protective shell, and fixing other components on the substrate 102, and placing the high heat-resistant end of the power chip in the high heat-generating high heat-resistant component region 1020 and the low heat-resistant end of the power chip in the high heat-generating low heat-resistant component region 1024; the protective shell 101 is firstly buckled on the substrate 102, and the protective shell is made to be closest to a high heat-generating and high heat-resisting element area 1020 under the high-yield and high-resistance area 103, to be closest to a low heat-generating element area 1021 under the low-yield area 104, to be closest to a high heat-generating and low heat-resisting element area 1024 under the high-yield and low-resistance area 106, and to be closest to a geometric center 1023 under the concentrated outer conducting area 105; and then the packaging bottom plate and the protective shell are subjected to thermal bonding forming.
It will be appreciated by those of ordinary skill in the art that the present application can be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The embodiments disclosed above are illustrative and not exclusive in all respects. All changes that come within the scope of or equivalence to the scope of this application are intended to be embraced therein.
Claims (8)
1. A power type chip packaging method is characterized in that: the method comprises the following steps: configuring a packaging bottom plate; configuring a protective shell; the packaging bottom plate and the protective shell are formed in a hot connection mode;
wherein the configuration package substrate comprises: determining a geometric center on the substrate, and dividing the substrate into four regions by making two vertical axes through the geometric center, wherein one region is a low heat generating element region, and two regions adjacent to the low heat generating element region are a high heat generating high heat-resistant element region and a high heat generating low heat-resistant element region respectively; arranging corresponding element fixing holes on the high-heat-yield high-heat-resistance element area, the low-heat-generation element area and the high-heat-yield low-heat-resistance element area; wherein the high heat-producing high heat-resistant element region is specifically a region where a high heat-producing high heat-resistant element or a high heat-producing high heat-resistant chip is placed, wherein the low heat-producing element region is specifically a region where a low heat-producing element or a low heat-producing chip is placed, and wherein the high heat-producing low heat-resistant element region is specifically a region where a high heat-producing low heat-resistant element or a high heat-producing low heat-resistant chip is placed;
configuring the protective case includes: processing a substrate into a protective shell, forming a concentrated outer conducting area with relatively thin thickness in the middle of the protective shell, forming a high-yield high-endurance area and a high-yield low-endurance area on two sides of the concentrated outer conducting area respectively, forming a low-yield area in the middle of the high-yield high-endurance area and the high-yield low-endurance area and at a position which is not the concentrated outer conducting area, forming a strip-shaped straight conducting area with relatively thin thickness on two sides of the high-yield high-endurance area respectively, and extending the straight conducting area from the high-yield high-endurance area to the concentrated outer conducting area; forming a ring-shaped ring guide area with relatively thin thickness around the high-yield low-tolerance area;
before the packaging bottom plate and the protective shell are subjected to thermal bonding forming, the power type chip is fixed on the substrate, the high heat-resistant end of the power type chip is arranged in the high heat-production high heat-resistant element area, and the low heat-resistant end of the power type chip is arranged in the high heat-production low heat-resistant element area; the protection shell is firstly buckled on the substrate, and the part right below the high-yield high-resistance area is closest to the high-heat-production high-heat-resistance element area, the part right below the low-yield area is closest to the low-heat-production element area, the part right below the high-yield low-resistance area is closest to the high-heat-production low-heat-resistance element area, and the part right below the concentrated outer conducting area is closest to the geometric center; and then the packaging bottom plate and the protective shell are subjected to thermal bonding forming.
2. The method of claim 1, wherein: the ring guide area, the concentrated outer guide area and the straight guide area can be integrally formed on the protective shell in a punching mode.
3. The method of claim 2, wherein: the overlook cross-sectional shapes of the substrate and the protective shell are both square.
4. The method of claim 1, wherein: before the package bottom plate and the protective shell are thermally connected and molded, the power type chip is fixed on the substrate, and other elements are fixed on the substrate.
5. The method of claim 1, wherein: the configuration package bottom plate also comprises a lead hole and a lead which are formed on the periphery of the substrate.
6. The method of claim 1, wherein: the heat generating efficiency of the high heat-generating and high heat-resisting element area is V1, the heat generating efficiency of the low heat-generating element area is V2, the heat generating efficiency of the high heat-generating and low heat-resisting element area is V3, the heat dissipating efficiency of the high yield and high heat-resisting area is V5, the comprehensive heat dissipating efficiency of the direct conducting area is V6, the total heat dissipating efficiency of the concentrated external conducting area is V7, the comprehensive heat dissipating efficiency of the ring conducting area is V8, the heat dissipating efficiency of the high yield and low heat-resisting area is V9, the heat dissipating efficiency of the low yield area is V10, the comprehensive heat dissipating efficiency of the concentrated external conducting area to the high yield and high heat-resisting area is V71, the comprehensive heat dissipating efficiency of the concentrated external conducting area to the high yield and low heat-resisting area is V72, then the ring conducting area is firstly configured, then, a direct conducting region is configured, and then a concentrated external conducting region is configured, so that V9 + V8 + V72 is more than V3, V5 + V6 + V71 is more than or equal to V1, and V7 + V6 + V8 + V5 + V9 + V10 is more than or equal to V1 + V2 + V3.
7. The method of claim 6, wherein: the first configuration of the ring guide region, the second configuration of the straight guide region and the second configuration of the concentrated outer guide region includes first configuration of the thickness and the specific area of the ring guide region and making the thickness of the ring guide region thinner than that of the protection shell or the high-yield and low-tolerance region, then configuration of the thickness and the specific area of the straight guide region and making the thickness of the straight guide region thinner than that of the protection shell or the high-yield and high-tolerance region, and then configuration of the thickness and the specific area of the concentrated outer guide region and making the thickness of the concentrated outer guide region thinner than that of the straight guide region and the ring guide region.
8. The method of claim 7, wherein: the configuring of the ring guide region, the configuring of the straight guide region, and the configuring of the concentrated outer guide region further specifically include configuring a material of the ring guide region and/or a material of the straight guide region and/or a material of the concentrated outer guide region.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW571413B (en) * | 2002-12-31 | 2004-01-11 | Phoenix Prec Technology Corp | Method of manufacturing BGA substrate with high performance of heat dissipating structure |
| CN102709264A (en) * | 2012-05-16 | 2012-10-03 | 南京国博电子有限公司 | Radio frequency (RF) transceiving front end module and preparation method thereof |
| US20150276152A1 (en) * | 2014-04-01 | 2015-10-01 | Huga Optotech, Inc. | Led assembly and led bulb using the same |
| JP2016052135A (en) * | 2014-08-28 | 2016-04-11 | 富士電機株式会社 | Power conversion device |
| CN107360664A (en) * | 2017-04-07 | 2017-11-17 | 麦科勒（滁州）新材料科技有限公司 | A kind of heat-conduction circuit board and preparation method thereof |
| JP2017216772A (en) * | 2016-05-30 | 2017-12-07 | 三菱電機株式会社 | Electric power conversion system |
| US20210175155A1 (en) * | 2019-12-06 | 2021-06-10 | Alpha And Omega Semiconductor (Cayman) Ltd. | Power module having interconnected base plate with molded metal and method of making the same |
-
2021
- 2021-11-23 CN CN202111389549.0A patent/CN113823574B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW571413B (en) * | 2002-12-31 | 2004-01-11 | Phoenix Prec Technology Corp | Method of manufacturing BGA substrate with high performance of heat dissipating structure |
| CN102709264A (en) * | 2012-05-16 | 2012-10-03 | 南京国博电子有限公司 | Radio frequency (RF) transceiving front end module and preparation method thereof |
| US20150276152A1 (en) * | 2014-04-01 | 2015-10-01 | Huga Optotech, Inc. | Led assembly and led bulb using the same |
| JP2016052135A (en) * | 2014-08-28 | 2016-04-11 | 富士電機株式会社 | Power conversion device |
| JP2017216772A (en) * | 2016-05-30 | 2017-12-07 | 三菱電機株式会社 | Electric power conversion system |
| CN107360664A (en) * | 2017-04-07 | 2017-11-17 | 麦科勒（滁州）新材料科技有限公司 | A kind of heat-conduction circuit board and preparation method thereof |
| US20210175155A1 (en) * | 2019-12-06 | 2021-06-10 | Alpha And Omega Semiconductor (Cayman) Ltd. | Power module having interconnected base plate with molded metal and method of making the same |
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Denomination of invention: A Power Chip Packaging Method Granted publication date: 20220325 Pledgee: Zaozhuang rural commercial bank Limited by Share Ltd. Yicheng sub branch Pledgor: Shandong Hanxin Technology Co.,Ltd. Registration number: Y2024980003094 |