CN113809209B - LED epitaxial structure, preparation method thereof and LED chip - Google Patents

LED epitaxial structure, preparation method thereof and LED chip Download PDF

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CN113809209B
CN113809209B CN202111134402.7A CN202111134402A CN113809209B CN 113809209 B CN113809209 B CN 113809209B CN 202111134402 A CN202111134402 A CN 202111134402A CN 113809209 B CN113809209 B CN 113809209B
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quantum
alingan
type semiconductor
epitaxial structure
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CN113809209A (en
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万志
王莎莎
史成丹
程文涛
卓祥景
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Xiamen Changelight Co Ltd
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Xiamen Changelight Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H01L33/145—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
    • H01L33/32—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen

Abstract

The invention provides an LED epitaxial structure, a preparation method thereof and an LED chip, which are characterized in that: an electron cooling layer composed of undoped InGaN is arranged between the N-type semiconductor layer and the MQW layer, the quantum barrier comprises a GaN layer, and the quantum well comprises an InGaN layer; and the In component of the electron cooling layer is smaller than that of the quantum well. Because the lattice mismatch generated by the electronic cooling layer formed by InGaN and the GaN layer in the quantum barrier is extremely small, the improvement of the crystal quality is facilitated when the MQW layer is grown subsequently; meanwhile, the InGaN electron cooling layer can reduce the average free path of electrons in the MQW layer, can also play a role in blocking electrons at the early stage, reduces the barrier height of a valence band, and indirectly increases hole injection, so that the efficient recombination of current carriers in the MQW layer is promoted.

Description

LED epitaxial structure, preparation method thereof and LED chip
Technical Field
The invention relates to the field of light emitting diodes, in particular to an LED epitaxial structure, a preparation method thereof and an LED chip.
Background
In recent years, due to excellent physical and chemical characteristics (large forbidden bandwidth, high breakdown electric field, high electron saturation mobility and the like), group III-V nitrides have attracted extensive attention and applications in the electrical and optical fields, such as hot blue-green light display screen products on the market at present, ultraviolet light sterilization and disinfection modules for heat holding after new crown epidemic situations and the like. However, due to the limitations of materials, structures and processes in practical applications, various new LED products still have many problems in large-scale application, such as severe overflow caused by insufficient electron confinement; the hole injection efficiency is low, and the further improvement of the luminous efficiency is limited; strong polarization fields due to large lattice mismatch, etc., which prevent efficient recombination of carriers in the active region, and thus, present a great challenge to large-scale commercialization of LEDs. Therefore, the reduction of electron leakage, the increase of hole injection efficiency, the weakening of a strong polarization electric field and the promotion of efficient recombination of carriers in an active region become the key for improving the luminous efficiency of the LED.
Currently, to reduce electron leakage, an AlGaN electron blocking layer is usually inserted in front of a Multiple Quantum Well (MQW) and an AlGaN layer is embedded in the quantum barrier. However, the AlGaN electron blocking layer inserted in front of the MQW can play a role of blocking electrons at the early stage, but the lattice mismatch between the AlGaN electron blocking layer and the GaN is too large, so that the crystal growth quality of the subsequent MQW is inevitably influenced; an AlGaN layer is embedded in the quantum barrier, and the lattice mismatch is too large, so that the energy band is seriously bent, the polarization electric field is enhanced, the overlap of electron hole wave functions in the MQW is influenced, and the luminous efficiency is further reduced.
In view of the above, the present inventors have specially designed an LED epitaxial structure, a method for fabricating the same, and an LED chip.
Disclosure of Invention
The invention aims to provide an LED epitaxial structure, a preparation method thereof and an LED chip, so as to promote efficient recombination of current carriers in an active region and improve the luminous efficiency of an LED.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
an LED epitaxial structure, comprising:
the substrate, and an N-type semiconductor layer, an electron cooling layer, an MQW layer and a P-type semiconductor layer which are sequentially laminated on the surface of the substrate;
wherein the MQW layer includes quantum barriers and quantum wells alternately stacked in a first direction, and the quantum barriers include GaN layers, and the quantum wells include InGaN layers; the electron cooling layer comprises an undoped InGaN layer, and the In composition of the electron cooling layer is smaller than that of the quantum well, so that the mean free path of electrons In the MQW layer is reduced; the first direction is perpendicular to the substrate and directed toward the N-type semiconductor layer from the substrate.
Preferably, the thickness of the electron cooling layer is H, the thickness of the quantum barrier is L, and then L is less than or equal to H and less than or equal to 2L.
Preferably, each quantum barrier comprises a GaN layer with an AlInGaN insertion layer, and the Al composition of the AlInGaN insertion layer is graded; wherein the Al component is between 0 and 0.1, including 0.1.
Preferably, the Al composition in the multi-layered AlInGaN insertion layer is gradually increased along the first direction.
Preferably, except for the top quantum barrier close to the P-type semiconductor layer, the increase range of the Al component of two adjacent AlInGaN insertion layers is 0.01-0.03, inclusive.
Preferably, the Al composition of the AlInGaN insertion layer in the top quantum barrier is increased by an amount in the range of 0.1-0.15, inclusive, compared to the Al composition of the AlInGaN insertion layer in the previous quantum barrier.
Preferably, in the electron cooling layer, an In component decreases stepwise In the first direction.
Preferably, in the electron cooling layer, an In component increases stepwise In the first direction.
The invention also provides a preparation method of the LED epitaxial structure, which comprises the following steps:
providing a substrate;
sequentially growing an N-type semiconductor layer, an electron cooling layer, an MQW layer and a P-type semiconductor layer on the surface of the substrate;
wherein the MQW layer includes quantum barriers and quantum wells alternately stacked in a growth direction, and the quantum barriers include GaN layers, and the quantum wells include InGaN layers; the electron cooling layer comprises an InGaN layer, and the In component of the electron cooling layer is smaller than that of the quantum well, so that the mean free path of electrons In the MQW layer is reduced.
Preferably, a double pulse flux method is used to form a corresponding AlInGaN insertion layer in each of the quantum barriers, wherein the Al composition is between 0 and 0.1, including 0.1. Preferably, the Al composition in the multi-layered AlInGaN insertion layer increases gradually along the growth direction.
The invention also provides an LED chip, comprising;
the foregoing LED epitaxial structure;
the N-type electrode and the N-type semiconductor layer form ohmic contact;
and the P-type electrode and the P-type semiconductor layer form ohmic contact.
According to the technical scheme, the LED epitaxial structure provided by the invention is characterized in that: an electron cooling layer composed of undoped InGaN is arranged between the N-type semiconductor layer and the MQW layer, the quantum barrier comprises a GaN layer, and the quantum well comprises an InGaN layer; and the In component of the electron cooling layer is smaller than the In component of the quantum well. Because the lattice mismatch between the electronic cooling layer formed by InGaN and the GaN layer in the quantum barrier is very small, the improvement of the crystal quality during the subsequent growth of the MQW layer is facilitated; meanwhile, the average free path of electrons in the MQW layer is reduced, the effect of blocking electrons at the early stage can be achieved, the barrier height of a valence band is reduced, and hole injection is indirectly increased, so that efficient recombination of current carriers in the MQW layer is promoted. Meanwhile, the electron cooling layer is made of undoped InGaN, so that the electron blocking is guaranteed, and meanwhile, the lateral expansion of current is facilitated.
Furthermore, the thickness of the electron cooling layer is H, the thickness of the quantum barrier is L, and H is more than or equal to L and less than or equal to 2L. The problem that the electron mean free path cannot be reduced due to the fact that the thickness of the electron cooling layer is too thin is avoided; the problems of stress accumulation and poor crystal quality caused by too thick thickness of the electronic cooling layer are also avoided; meanwhile, when L is more than or equal to H and less than or equal to 2L, in is increased/decreased In a spatial gradient manner In the growth process.
Secondly, the method comprises the following steps: each quantum barrier comprises a GaN layer with an AlInGaN insertion layer, and the Al component of the AlInGaN insertion layer is arranged in a gradual change mode; enabling a higher conduction band barrier in the MQW layer, thereby providing more efficient electron blocking; meanwhile, the insertion layer is made of AlInGaN materials, so that lattice mismatch between the insertion layer and a GaN quantum barrier can be further reduced, and an excessively strong polarization electric field is avoided.
Then, the Al composition of the AlInGaN insertion layer in the top quantum barrier is increased by an amount in the range of 0.1-0.15, inclusive, compared to the Al composition of the AlInGaN insertion layer in the previous quantum barrier. The method has the advantages that the higher conduction band barrier can be generated, effective electron blocking is provided, meanwhile, the overlapping of electron hole wave functions is facilitated, and the phenomena that the lattice mismatch of the top layer quantum barrier and the P-type semiconductor layer is too large, the energy band is seriously bent and a strong polarization electric field is generated due to too high Al component can be effectively avoided. Meanwhile, the high-aluminum component AlInGaN insertion layer is arranged in the top quantum barrier, so that electron blocking can be well achieved without arranging an independent electron blocking layer between the MQW layer and the P-type semiconductor layer, and the problem of lattice mismatch caused by the electron blocking layer is further avoided.
The invention also provides a preparation method of the LED epitaxial structure, which is simple to operate and easy to realize while realizing the technical effects. Meanwhile, by adopting a double-pulse flux method, the corresponding AlInGaN insertion layers are formed in the quantum barriers, and the Al component in the AlInGaN insertion layers can be gradually increased by fine control, so that a high-crystal-quality material can be obtained more easily, and a better electronic blocking effect is provided.
The invention also provides an LED chip which is formed by utilizing the LED epitaxial structure, has a simple structure and well improves the luminous efficiency of the LED chip.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an LED epitaxial structure according to an embodiment of the present invention;
fig. 2 is a schematic conduction band diagram of each structural layer in an LED epitaxial structure according to an embodiment of the present invention;
fig. 3 is a schematic diagram illustrating indium composition transformation of an electron cooling layer in an LED epitaxial structure according to an embodiment of the present invention;
fig. 4 is a schematic diagram illustrating an indium composition transformation of an electron cooling layer in an LED epitaxial structure according to another embodiment of the invention;
fig. 5 is a schematic diagram illustrating an indium composition transformation of an electron cooling layer in an LED epitaxial structure according to another embodiment of the invention;
FIG. 6 is a schematic diagram illustrating an indium composition transformation of an electron cooling layer in an epitaxial structure of an LED according to still another embodiment of the invention;
fig. 7 is a schematic view illustrating a process control of growing an AlInGaN insertion layer by a double pulse method in a method for manufacturing an LED epitaxial structure according to an embodiment of the present invention;
the symbols in the drawings illustrate that: 1. the solar cell comprises a substrate, a 2 buffer layer, a 3 uGaN layer, a 4N-type semiconductor layer, a 5 electron cooling layer, a 6 quantum barrier, a 61 GaN layer, a 62 AlInGaN insertion layer, a 7 quantum well, a 8P-type semiconductor layer.
Detailed Description
In order to make the content of the present invention clearer, the content of the present invention is further explained below with reference to the attached drawings. The invention is not limited to this specific embodiment. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1, an LED epitaxial structure includes:
the semiconductor device comprises a substrate 1, an N-type semiconductor layer 4, an electron cooling layer 5, an MQW layer and a P-type semiconductor layer 8 which are sequentially laminated on the surface of the substrate 1;
wherein the MQW layer includes quantum barriers 6 and quantum wells 7 alternately stacked in a first direction, and the quantum barriers 6 include GaN layers 61, and the quantum wells 7 include InGaN layers; the electron cooling layer 5 comprises an undoped InGaN layer, and the In component of the electron cooling layer 5 is smaller than that of the quantum well 7, and is used for reducing the mean free path of electrons In the MQW layer; the first direction is perpendicular to the substrate 1 and is directed from the substrate 1 to the N-type semiconductor layer 4.
It is to be noted that the type of the substrate 1 is not limited in the present embodiment, and for example, the substrate 1 includes any one of sapphire, silicon carbide, silicon, gallium nitride, and aluminum nitride. In addition, the types of the N-type semiconductor layer 4 and the P-type semiconductor layer 8 may also be unlimited, for example, the N-type semiconductor layer 4 may be, but is not limited to, a gallium nitride layer, and accordingly, the P-type semiconductor layer 8 may be, but is not limited to, a gallium nitride layer.
Further, based on the above embodiment of the present invention, the thickness of the electron cooling layer is H, and the thickness of the quantum barrier is L, then L is not less than H and not more than 2L.
Further, according to the above embodiment of the present invention, each quantum barrier 6 includes Al x1 In 1-x A GaN layer 61 of GaN insertion layer, and Al composition of AlInGaN insertion layer 62 is graded; wherein the Al component is between 0 and 0.1, including 0.1.
Further, as shown in fig. 2, according to the above embodiment of the present invention, the Al composition of the AlInGaN multi-layered insert layer 62 is gradually increased along the first direction, wherein X1, X2, X3 \8230; \8230, xn denotes the Al composition value.
Further, based on the above embodiment of the present invention, the Al composition of the adjacent two AlInGaN insertion layers 62 except the top quantum barrier 6 near the P-type semiconductor layer 8 increases by a range of 0.01-0.03 inclusive.
Further, based on the above embodiment of the present invention, the Al composition of the AlInGaN insertion layer 62 in the top quantum barrier 6 is increased by an amount ranging from 0.1 to 0.15 inclusive, compared to the Al composition of the AlInGaN insertion layer 62 in the previous quantum barrier 6.
Further, according to the above embodiment of the present invention, in the electron cooling layer 5, the In component decreases stepwise In the first direction.
Further, according to the above embodiment of the present invention, in the electron cooling layer 5, the In composition increases stepwise In the first direction.
Further, according to the above embodiment of the present invention, the buffer layer 2 and the uGaN layer 3 are further disposed between the substrate 1 and the N-type semiconductor layer 4.
The embodiment of the invention also provides a preparation method of the LED epitaxial structure, and equipment used in the preparation method comprises but is not limited to MOCVD (metal organic chemical vapor deposition), namely trimethyl/ethyl gallium TMGa/TEGa, trimethyl aluminum TMAl and ammonia NH 3 Ga source, al source, N source as base material, H 2 As carrier gas, the N-type and P-type doping sources are respectively SiH 4 And metallocene magnesium CP 2 Mg。
The pressure of the whole reaction growth is 100-300 torr.
The preparation method comprises the following steps:
s01, providing a substrate 1;
in this step, the substrate 1 includes, but is not limited to, a sapphire substrate 1.
S02, sequentially forming a buffer layer 2, a uGaN layer 3 and an N-type semiconductor layer 4 on a substrate 1;
in the step, the substrate 1 is placed in an MOCVD reaction chamber, high-purity hydrogen is introduced to hydrogenate for about 5 minutes at the temperature of about 1100 ℃, then the temperature is reduced to about 960 ℃, and an undoped AlN buffer layer 2 with the thickness of about 10nm is grown by introducing an Al source and an N source.
And continuously heating to 1050-1100 ℃, closing the Al source, introducing the TMGa source, and growing an undoped GaN layer with the thickness of 2.0-2.5 mu m, wherein the aim is to reduce the lattice mismatch between the sapphire substrate 1 and a subsequent grown film layer material by growing a high-quality uGaN layer 3.
Then introducing an Al source, and growing an AlGaN layer at the ambient temperature of 980-1020 ℃ to the thickness of 10-20 nm; closing Al source, introducing silane, growing Si-doped GaN layer with doping concentration of 5 × 10 18 cm -3 -10×10 18 cm -3 (ii) a The two layers are alternately grown for 10 to 20 cycles, and finally the N-type semiconductor layer 4 is obtained.
The N-type semiconductor layer 4 can further block dislocation to improve the crystal quality, and the current spreading capability can be further enhanced by using an intermittent doping manner (i.e., undoped/doped/undoped/doped 8230; etc.).
S03, forming an electron cooling layer 5 on the surface of one side, away from the uGaN layer 3, of the N-type semiconductor layer 4, wherein the In component of the electron cooling layer 5 is smaller than that of the quantum well 7, and the electron cooling layer is used for reducing the mean free path of electrons In the MQW layer;
in the step, after the growth of the N-type semiconductor layer 4 is completed, the Al source is closed, the In source is introduced, and the undoped InGaN electronic cooling layer 5 with the thickness of 10-15nm is grown.
Further, as shown In fig. 3, in an embodiment of the present invention, in the electron cooling layer 5, the In component is reduced In a step shape along the growth direction for realizing the stress transition between the electron cooling layer 5 and the N-type semiconductor layer 4, so as to reduce lattice mismatch and improve the crystal quality.
In another embodiment of the present invention, as shown In fig. 4, in the electron cooling layer 5, the In component increases In a step shape along the growth direction for realizing the stress transition between the electron cooling layer 5 and the subsequently grown MQW layer, thereby reducing the lattice mismatch and improving the crystal quality.
In other embodiments of the present invention, as shown In fig. 5, the In composition of the electron cooling layer 5 may be gradually increased first and then gradually decreased; as shown In fig. 6, the In content of the electron cooling layer 5 may be gradually decreased and then gradually increased.
S04, forming an MQW layer on the surface of one side, away from the N-type semiconductor layer 4, of the electronic cooling layer 5;
the MQW layer comprises quantum barriers 6 and quantum wells 7 which are alternately stacked along the growth direction, each quantum barrier 6 comprises a GaN layer 61 with an AlInGaN insertion layer 62, and the Al composition of the AlInGaN insertion layers 62 is gradually changed, wherein the Al composition is between 0 and 0.1 and comprises 0.1; the quantum well 7 comprises an InGaN layer;
in the step, al source and In source are intermittently introduced, a GaN/AlInGaN/GaN quantum barrier 6 with the thickness of 10-15nm grows, and the Al component is between 0 and 0.1 and comprises 0.1; (ii) a As shown In fig. 7, the AlInGaN insertion layer 62 adopts a double-pulse growth method, that is, in the pulse growth period T, the In composition is precisely controlled by controlling the time T1 for introducing TMIn; in addition, for the introduction of TMAl, more fine time control is adopted, and the discontinuous period is t2.
Then, an InGaN quantum well 7 layer is grown again, the period is repeated, and the growth period is 5-10, so that the MQW layer is formed.
The preparation method described in this example only illustrates the case where the electron cooling layer is equivalent to the quantum barrier in thickness. In other embodiments of the invention, the thickness of each layer is not limited, and L is less than or equal to H and less than or equal to 2L as long as the thickness of the electron cooling layer is H and the thickness of the quantum barrier is L.
Further, in one embodiment of the present invention, the Al composition of two adjacent AlInGaN insertion layers 62, except for the top quantum barrier 6, increases by a range of 0.01-0.03 inclusive. A higher conduction band barrier can be generated in the MQW layer, so that more effective electron blocking is provided; meanwhile, the insertion layer is made of AlInGaN material, so that lattice mismatch between the insertion layer and the GaN quantum barrier 6 can be further reduced, and an excessively strong polarization electric field is avoided.
Further, based on the above embodiment of the present invention, the Al composition of the AlInGaN insertion layer 62 in the top quantum barrier 6 is increased by an amount ranging from 0.1 to 0.15 inclusive, compared to the Al composition of the AlInGaN insertion layer 62 in the previous quantum barrier 6. The method has the advantages that the higher conduction band barrier can be generated, effective electron blocking is provided, meanwhile, the overlapping of electron hole wave functions is facilitated, and the phenomena that the lattice mismatch of the top layer quantum barrier 6 and the P type semiconductor layer 8 is too large, the energy band is seriously bent and a strong polarization electric field is generated due to too high Al component can be effectively avoided. Meanwhile, the high-aluminum-composition AlInGaN insertion layer 62 is arranged in the top quantum barrier 6, so that electron blocking can be well achieved without arranging an independent electron blocking layer between the MQW layer and the P-type semiconductor layer 8, and the problem of lattice mismatch caused by the electron blocking layer is further avoided.
It is worth mentioning that in one embodiment of the present invention, the total thickness of all AlInGaN insertion layers 62 is 15-30nm, without limiting the thickness of each AlInGaN insertion layer 62.
S05, forming a P-type semiconductor layer 8 on the surface of one side, away from the electron cooling layer 5, of the MQW layer;
in the step, the temperature is adjusted to 900-1000 ℃, TMGa source, nitrogen source and magnesium dicyclopentadienyl are introduced to grow a P-type GaN layer with the thickness of 100-150nm and the doping concentration of 5 x 10 18 cm -3 To 10 x 10 18 cm -3 (ii) a Finally, the P-type semiconductor layer 8 is formed.
The embodiment of the invention also provides an LED chip, which comprises;
the foregoing LED epitaxial structure;
the N-type electrode is in ohmic contact with the N-type semiconductor layer 4;
and the P-type electrode is in ohmic contact with the P-type semiconductor layer 8.
It should be noted that, the embodiment does not limit the specific structure of the LED chip, and the LED chip may be a flip LED chip, a front-mounted LED chip, or a horizontal LED chip or a vertical LED chip, as the case may be.
As can be seen from the above technical solutions, the LED epitaxial structure provided in the embodiments of the present invention is formed by: an electron cooling layer 5 made of InGaN is arranged between the N-type semiconductor layer 4 and the MQW layer, the quantum barrier 6 comprises a GaN layer 61, and the quantum well 7 comprises an InGaN layer; and the In composition of the electron cooling layer 5 is smaller than that of the quantum well 7. Because the lattice mismatch between the electron cooling layer 5 made of InGaN and the GaN layer 61 in the quantum barrier 6 is extremely small, the improvement of the crystal quality during the subsequent growth of the MQW layer is facilitated; meanwhile, the average free path of electrons in the MQW layer is reduced, the effect of blocking electrons at the early stage can be achieved, the height of a valence band potential barrier is reduced, and hole injection is indirectly increased, so that efficient recombination of current carriers in the MQW layer is promoted. Meanwhile, the electron cooling layer 5 is made of undoped InGaN, so that the electron blocking is ensured, and the lateral expansion of current is facilitated.
Furthermore, the thickness of the electron cooling layer is H, the thickness of the quantum barrier is L, and H is more than or equal to L and less than or equal to 2L. The problem that the electron mean free path cannot be reduced due to the fact that the thickness of the electron cooling layer is too thin is avoided; the problems of stress accumulation and poor crystal quality caused by too thick thickness of the electronic cooling layer are also avoided; meanwhile, when L is more than or equal to H and less than or equal to 2L, in is increased/decreased In a spatial gradient manner In the growth process.
Secondly, the method comprises the following steps: each quantum barrier 6 comprises a GaN layer with an AlInGaN insertion layer 62, and the Al composition of the AlInGaN insertion layer 62 is graded; a higher conduction band barrier can be generated in the MQW layer, so that more effective electron blocking is provided; meanwhile, the insertion layer is made of AlInGaN material, so that lattice mismatch between the insertion layer and the GaN quantum barrier 6 can be further reduced, and an excessively strong polarization electric field is avoided.
The Al composition of the AlInGaN insertion layer 62 in the top quantum barrier 6 is then increased by an amount in the range of 0.1-0.15, inclusive, compared to the Al composition of the AlInGaN insertion layer 62 in the previous quantum barrier 6. The method has the advantages that the higher conduction band barrier can be generated, effective electron blocking is provided, meanwhile, the overlapping of electron hole wave functions is facilitated, and the phenomena that lattice mismatch of the top layer quantum barrier 6 and the P-type semiconductor layer 8 is too large, the energy band is seriously bent and a strong polarization electric field is generated due to too high Al component can be effectively avoided. Meanwhile, the high-aluminum-composition AlInGaN insertion layer 62 is arranged in the top quantum barrier 6, so that electron blocking can be well achieved without arranging an independent electron blocking layer between the MQW layer and the P-type semiconductor layer 8, and the problem of lattice mismatch caused by the electron blocking layer is further avoided.
The embodiment of the invention also provides a preparation method of the LED epitaxial structure, which is simple to operate and easy to realize while achieving the technical effects. Meanwhile, by adopting a double-pulse flux method, the corresponding AlInGaN insertion layer 62 is formed in each quantum barrier 6, and the Al component in the multi-layer AlInGaN insertion layer 62 can be gradually increased by fine control, so that a high-crystal-quality material can be obtained more easily, and a better electron blocking effect is provided.
The embodiment of the invention also provides the LED chip which is formed by utilizing the LED epitaxial structure, has a simple structure and well improves the luminous efficiency of the LED chip.
In the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrases "comprising one of the elements 8230 \8230;" does not exclude the presence of additional like elements in an article or device comprising the same element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (9)

1. An LED epitaxial structure, comprising:
the substrate, and an N-type semiconductor layer, an electron cooling layer, an MQW layer and a P-type semiconductor layer which are sequentially laminated on the surface of the substrate;
wherein the MQW layer includes quantum barriers and quantum wells alternately stacked in a first direction, and the quantum barriers include GaN layers, and the quantum wells include InGaN layers; the electron cooling layer comprises an undoped InGaN layer, and the In component of the electron cooling layer is smaller than that of the quantum well, so that the mean free path of electrons In the MQW layer is reduced; the first direction is vertical to the substrate and is directed to the N-type semiconductor layer by the substrate;
meanwhile, each quantum barrier comprises a GaN layer with an AlInGaN insertion layer, and the Al composition of the AlInGaN insertion layer is gradually changed; wherein the Al component is between 0 and 0.1, including 0.1.
2. The LED epitaxial structure of claim 1, wherein the electron cooling layer has a thickness H and the quantum barrier has a thickness L, such that L ≦ H ≦ 2L.
3. The LED epitaxial structure of claim 1, wherein the Al composition in the multiple AlInGaN intervening layers increases gradually along the first direction.
4. The LED epitaxial structure of claim 3, wherein the Al composition of two adjacent AlInGaN insertion layers except for the top quantum barrier near the P-type semiconductor layer increases by a magnitude in a range from 0.01 to 0.03 inclusive.
5. The LED epitaxial structure of claim 4, wherein the Al composition of the AlInGaN insertion layer in the top quantum barrier is increased by an amount in the range of 0.1-0.15, inclusive, compared to the Al composition of the AlInGaN insertion layer in the previous quantum barrier.
6. The LED epitaxial structure of claim 1, wherein In the electron cooling layer, in composition decreases stepwise along the first direction.
7. The LED epitaxial structure of claim 1, wherein In the electron cooling layer, the In composition increases stepwise along the first direction.
8. A preparation method of an LED epitaxial structure is characterized by comprising the following steps:
providing a substrate;
sequentially growing an N-type semiconductor layer, an electron cooling layer, an MQW layer and a P-type semiconductor layer on the surface of the substrate;
wherein the MQW layer includes quantum barriers and quantum wells alternately stacked in a growth direction, and the quantum barriers include GaN layers, and the quantum wells include InGaN layers; the electron cooling layer comprises an InGaN layer, and the In component of the electron cooling layer is smaller than that of the quantum well, so that the mean free path of electrons In the MQW layer is reduced;
meanwhile, a double-pulse flux method is adopted to form corresponding AlInGaN insertion layers in the quantum barriers, wherein the Al component is between 0 and 0.1 and comprises 0.1; and along the growth direction, the Al composition in the AlInGaN insertion layers is gradually increased.
9. An LED chip, comprising;
an LED epitaxial structure according to any one of claims 1 to 7;
the N-type electrode and the N-type semiconductor layer form ohmic contact;
and the P-type electrode and the P-type semiconductor layer form ohmic contact.
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