CN113792004A - High-speed interface line speed changing method and system based on RocktIO - Google Patents
High-speed interface line speed changing method and system based on RocktIO Download PDFInfo
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Abstract
The invention provides a high-speed interface line speed changing method based on a RockETIO, which is applied to a RockETIO high-speed interface line speed changing system; the RocktIO high-speed interface variable line speed system comprises a RocktIO interface board, a PCIe back board and a main control board; the RocktIO interface board is connected with a PCIe mainboard; the PCIe back plate is connected with the main control board; the installation RockIO interface board is a PCB board adopting Xilinx FPGA; the line speed changing method based on the RocktIO high-speed interface is realized by configuring a simple register list. The invention adopts a register list scheme with extremely simple configuration to realize the line speed changing scheme of the RocktIO, and the mode does not need to add other interfaces and has larger universality.
Description
Technical Field
The invention relates to the technical field of data storage technology and high-speed data transmission, in particular to a method and a system for changing line speed based on a RockeIO high-speed interface.
Background
In the field of information storage, computer storage architectures typically employ a PCIe bus architecture. In the face of various actual business requirements, various business data need to be transferred and stored into a storage medium through an optical fiber interface, and the process needs to be carried out through optical fiber interface information acquisition, information caching, PCIe interface data transfer, data or file information management, data storage and the like. The data unloading process from the optical fiber interface to the PCIe interface only relates to interface conversion tasks, and the optical fiber interface is generally independently designed into an interface board so as to meet the interface conversion requirement and the board card replacement requirement.
The rocketoi high-speed serial transceiver interface of Xilinx is a high-speed transceiver module which is integrated in a series of FPGA (field programmable gate array) above Virtex2 pro and can reach the Gb/s transmission speed, and is suitable for various high-speed data transmission protocols, such as: aurora, PCIe, Interlaken, SRIO, and the like.
RocktIO is a general name of a Ggabyte Transceiver (GT) series high-speed Transceiver in the field of saint, and at present, a GT has a plurality of series, such as GTX, GTH, GTY, GTZ and the like. Their rate ranges are different, for example, the line speed supported by GTH is currently 0.5Gb/s-16.375Gb/s, and the line speed supported by GTY is 0.5Gb/s-32.75 Gb/s. The FPGA high-speed interface supports high configurability and tight integration of logic resources. The internal structure block diagram mainly comprises a Physical medium Attachment (PMA Physical Media Attachment) and a Physical control layer (PCS Physical Coding subpayer). The physical medium layer (PMA) mainly includes a serializer and deserializer, transmission and reception buffers, a high-speed clock generator, and a line clock recovery unit. The physical control layer (PCS) mainly comprises 8B/10B or 64B/66B coding and decoding, comma detection and bit alignment, PRBS pseudo-random code generation and verification, TX phase correction and phase correction control, RX clock correction, channel binding and the like; the PMA mainly functions as TX pre-enhancement, OOB (Out-of-Band) and LPM low-power automatic linear adaptation.
Currently, there are 3 main ways for DRP dynamic configuration of rockio:
1) in the mode 1, a logic configuration state machine is designed in an FPGA, and registers related to variable linear speed are sequentially configured;
2) in the mode 2, an ARM core is arranged at a PS end of an SOC type FPGA, an AXI-lite GP low-speed interface of AXI is converted into a DRP interface time sequence, and a register related to speed change is configured by software;
3) in the mode 3, low-speed interfaces such as I2C, SPI, UART serial ports and the like are converted into DRP interface time sequences, and registers related to speed change are configured.
Currently, the above 3 ways are used to realize the dynamic configuration variable line speed of the RocketIO, and there are the following limitations:
1) in the mode 1, the DRP register is configured at one time through an FPGA internal design state machine, so that the flexibility is poor and the DRP register depends on the design of the FPGA;
2) mode 2, software configuration of the DRP register is performed through the SOC, which provides high flexibility. However, the non-SOC chip is not usable, but limited to the SOC chip.
3) In the mode 3, low-speed interfaces such as I2C, SPI, UART serial ports and the like are usually converted into an AXI-lite interface first and then into a DRP interface timing sequence, which is also flexible and has a certain market, but a new low-speed configuration interface is required.
In addition, there are almost 800 GTHE4_ COMMON and GTHE4_ CHANNEL registers related to DRP, and the number of registers is large, so it is also a key point to reduce the number of registers to be configured.
Disclosure of Invention
The invention aims to provide a method and a system for changing the line speed of a RockIO high-speed interface on an FPGA (field programmable gate array) based on Xilinx, so as to solve the problems in the technical background.
In order to achieve the purpose, the invention adopts the following technical scheme:
the invention provides a high-speed interface line speed changing method based on a RockETIO, which is applied to a RockETIO high-speed interface line speed changing system; the RocktIO high-speed interface variable line speed system comprises a RocktIO interface board, a PCIe back board and a main control board; the RocktIO interface board is connected with a PCIe mainboard; the PCIe back plate is connected with the main control board; the installation RockIO interface board is a PCB board adopting Xilinx FPGA; the high-speed interface line speed changing method based on the RocktIO comprises the following steps:
step S1, target linear speed IP generation: generating an IP core, IP0, of the target linear speed by using an IP generation guide of Xilinx;
step S2, new line speed IP generation: generating an IP core, IP1, of the target linear speed by using an IP generation guide of Xilinx;
step S3, extracting all parameters of the DRP configuration register: configuration parameters can be extracted using a high-level programming language, including: obtaining new parameter files IP0_ PARAM.txt and IP1_ PARAM.txt by the parameter name and the parameter value;
step S4, comparing and extracting register difference parameters: comparing the differences of the IP0_ PARAM.txt and IP1_ PARAM.txt files by using a text comparison tool, and copying a difference parameter line;
step S5, generating a minimal register list file: pasting the copied difference parameter line in a new text file to generate a very simple register configuration file diff _ param.txt; since the new line speed IP1 is the same as the original target line speed IP0 except that the line speed value is different, all other parameters are the same, the generated IP difference points are all time parameters related to line speed updating, such as PLL configuration parameters;
step S6: and generating a configuration register list file: looking up a DRP address mapping table by comparing with a Transceiver user manual of RocktIO, converting register parameter names and parameter values listed in diff _ param.txt into configuration values of register addresses corresponding to DRPs one by one, and generating a configuration register list file cfg _ param.txt;
step S7: writing a configuration program: and writing an initialization configuration file required by the main control board, wherein the initialization configuration file comprises a linear speed dynamic configuration function.
Preferably, the RocketIO interface board is a Xilinx FPGA PCB board provided with a RocketIO interface, and a high-speed serial transceiver interface is realized by utilizing a Xilinx transceiver IP interface; the Xilinx FPGA PCB board uses an AXI Master provided with a PCIe DMAendpoint IP self-contained, converts the DRP interface through the AXI Master, and configures a DRP configuration interface of the RocktIO.
Preferably, the RocktIO is a Xilinx GTX high-speed transceiver, which mainly comprises a physical medium layer PMA and a physical control layer PCS; the physical medium layer PMA mainly comprises a serializer and a deserializer, a sending and receiving buffer area, a high-speed clock generator and a line clock recovery unit; the physical control layer PCS mainly comprises 8B/10B or 64B/66B coding and decoding, comma detection and bit alignment, PRBS pseudo-random code generation and verification, TX phase correction and phase correction control, RX clock correction, channel binding and the like; the PMA mainly functions as TX pre-enhancement, OOB and LPM low-power consumption automatic linear adaptation.
Preferably, the Xilinx transceiver IP interface mainly includes four parts, namely, a GTX bus interface, a DRP port, an application layer data receiving and transmitting port, and a state debugging monitoring port.
Preferably, the GTX bus interface is a GTX physical fiber interface, and supports simplex and full duplex modes; the DRP port is a software or processor dynamic parameter configuration interface, and changes the working mode and the line rate of the RockettIO in a configuration register mode; the application layer transceiving data port consists of data sending and K code sending mark signals, data receiving and K code receiving mark signals; the state debugging monitoring ports comprise a clock recovery port, a TX configurable driving port, a RX equalizer (DFE/LPM) port, a RX polarity control port and a TX/RX8B/10B codec port.
Preferably, the main control board is a computer motherboard on which an operating system is installed.
Preferably, the high-level programming language includes a C language, a C + + language, a tcl language, or a python language.
Preferably, the text comparison tool is not limited to BeyondCompare.
Preferably, the method for changing the line speed based on the RocktIO high-speed interface is characterized by comprising the following specific processes:
a1, initializing a RocktIO system;
a2, configuring a DRP port line speed register of a certain lane of RocktIO according to the line speed changing method based on the RocktIO high-speed interface of claim 1;
a3, configuring a receiving and sending channel reset signal for soft resetting the lane;
a4, successfully initializing lane and pulling up a linkup signal;
a5, configuring DRP port line speed registers of other lanes of RockettIO;
a6: configuring a receiving and transmitting channel reset signal for soft resetting other lanes;
a7: the lane initialization is successful, and the link up signal is pulled up;
a8: when the configuration linear speeds of all the channels are finished, data are received and transmitted;
a9: and verifying whether the configuration is successful or not by using software.
The invention also provides a RockETIO high-speed interface variable linear speed system which is applied to any one of the above methods for changing the linear speed based on the RockETIO high-speed interface; the RocktIO high-speed interface variable line speed system comprises a RocktIO interface board, a PCIe back board and a main control board; the RocktIO interface board is connected with a PCIe mainboard; the PCIe back plate is connected with the main control board; the mounting RockIO interface board is a PCB board adopting Xilinx FPGA.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
the scheme realizes the line speed changing method of the RocktIO based on the register list scheme with extremely simple PCIe bus configuration, realizes independent configuration of multi-channel speed, does not need to newly add other interfaces, directly utilizes an AXI universal bus interface, and has higher universality.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application. In the drawings:
FIG. 1 is a schematic block diagram of a system in accordance with a preferred embodiment of the present invention;
FIG. 2 is a block diagram of the system components of the preferred embodiment of the present invention;
FIG. 3 is a diagram of the internal structure of a RocktIO port of the preferred embodiment of the present invention;
FIG. 4 is a block diagram of a RocktIO IP interface in accordance with a preferred embodiment of the present invention;
FIG. 5 is a DRP configuration parameter extraction flow of the preferred embodiment of the present invention;
fig. 6 is a DRP wire-speed configuration process of the preferred embodiment of the present invention.
Detailed Description
The invention provides a method and a system for changing a line speed based on a RocktIO high-speed interface, and in order to make the purpose, the technical scheme and the effect of the invention clearer and clearer, the invention is further described in detail by referring to the attached drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the above-described drawings are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order, it being understood that the data so used may be interchanged under appropriate circumstances. Furthermore, the terms "comprises," "comprising," and any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Example (b):
the invention provides a method and a system for changing a line speed based on a RocktIO high-speed interface, and a functional block diagram of the method and the system is shown in FIG. 1.
Fig. 2 is an example of a high-speed interface line speed changing system based on a RocketIO, where the system includes a rockeio interface board, a network interface board, an exchange board, a storage board, and a main control board.
The internal structure of a RockettIO interface board is shown in FIG. 3. The device mainly comprises a physical medium layer PMA and a physical control layer PCS; the physical medium layer PMA mainly comprises a serializer and a deserializer, a sending and receiving buffer area, a high-speed clock generator and a line clock recovery unit; the physical control layer PCS mainly comprises 8B/10B or 64B/66B coding and decoding, comma detection and bit alignment, PRBS pseudo-random code generation and verification, TX phase correction and phase correction control, RX clock correction, channel binding and the like; the PMA mainly functions as TX pre-enhancement, OOB and LPM low-power consumption automatic linear adaptation.
The Xilinx transceiver IP interface is shown in fig. 4, and mainly includes a GTX bus interface, a DRP port, an application layer data receiving and transmitting port, and a state debugging monitoring port. The GTX bus interface is a GTX physical optical fiber interface and supports simplex and full duplex modes; the DRP port is a software or processor dynamic parameter configuration interface, and changes the working mode and the line rate of the RockettIO in a configuration register mode; the application layer data receiving and transmitting port consists of data sending and K code mark signal sending, data receiving and K code mark signal receiving; the state debugging monitoring ports comprise a clock recovery port, a TX configurable driving port, a RX equalizer (DFE/LPM) port, a RX polarity control port and a TX/RX8B/10B codec port.
The main control board uses the kylin operating system.
The DRP configuration parameter extraction process is shown in fig. 5, and specifically as follows:
step S1, target linear speed IP generation: generating an IP core, IP0, of the target linear speed by using an IP generation guide of Xilinx;
step S2 new wire speed IP generation: generating an IP core, IP1, of the target linear speed by using an IP generation guide of Xilinx;
step S3, extracting all parameters of the DRP configuration register: the configuration parameters can be extracted by using C language, including: obtaining new parameter files IP0_ PARAM.txt and IP1_ PARAM.txt by the parameter name and the parameter value;
step S4, comparing and extracting register difference parameters: comparing the differences of the IP0_ PARAM.txt and IP1_ PARAM.txt files by using a text comparison tool, and copying a difference parameter line;
step S5, generating a minimal register list file: pasting the copied difference parameter line in a new text file to generate a difference result file diff _ param.txt which is a minimum parameter file needing configuration and is called as a minimal register configuration file;
step S6: and generating a configuration register list file: looking up a DRP address mapping table by comparing with a Transceiver user manual of RocktIO, converting register parameter names and parameter values listed in diff _ param.txt into configuration values of register addresses corresponding to DRPs one by one, and generating a configuration register list file cfg _ param.txt;
step S7: writing a configuration program: and writing an initialization configuration file required by the main control board by using a C language, wherein the initialization configuration file comprises a linear speed dynamic configuration function.
The transmission of the control information is transmitted to the main control board by the Ethernet through the network interface board and the exchange board; when data are recorded, large-flow data are processed by the optical port through the RocktIO interface board and then transmitted to the storage main control board through the exchange board for distributed information storage; during data playback, the main control board reads a large amount of data from the storage board, notifies the rockio interface board to relay to acquire the data, the rockio reads frame data from the main control board memory, and then sends the frame data out from the optical port, and the operation flow is as shown in fig. 6, specifically as follows:
step 1, successfully initializing a RockettIO system;
step 2, configuring a DRP port linear speed register of the 1 st lane of the RockettIO;
step 3, configuring a receiving and sending channel reset signal for soft resetting the lane;
step 4, successfully initializing lane and pulling up a linkup signal;
step 5, configuring DRP port linear speed registers of other lanes of RockettIO;
step 6, configuring the receiving and transmitting channel reset signals of other lanes for soft reset;
7, successfully initializing lane and pulling up a linkup signal;
step 8, after the configuration linear speeds of all channels are finished, data are received and transmitted;
and 9, verifying whether the configuration is successful or not by software.
Through the line speed configuration process of the invention, the RocktIO interface board realizes that the multichannel speed can be independently configured, such as: 10.3125G, 8G, 6.25G, 5G and 3.125G.
In summary, the adoption of the method for changing the line speed based on the RocktIO high-speed interface realizes independent configuration of the multi-channel rate, and the method directly utilizes an AXI universal bus interface without adding other interfaces and has greater universality.
The embodiments of the present invention have been described in detail, but the embodiments are merely examples, and the present invention is not limited to the embodiments described above. Any equivalent modifications and substitutions to those skilled in the art are also within the scope of the present invention. Accordingly, equivalent changes and modifications made without departing from the spirit and scope of the present invention should be covered by the present invention.
Claims (10)
1. A high-speed interface line speed changing method based on RocktIO is characterized by being applied to a RocktIO high-speed interface line speed changing system; the RocktIO high-speed interface variable line speed system comprises a RocktIO interface board, a PCIe back board and a main control board; the RocktIO interface board is connected with a PCIe mainboard; the PCIe back plate is connected with the main control board; the installation RockIO interface board is a PCB board adopting Xilinx FPGA; the high-speed interface line speed changing method based on the RocktIO comprises the following steps:
step S1: target line speed IP generation: generating an IP core, IP0, of the target linear speed by using an IP generation guide of Xilinx;
step S2: new line speed IP generation: generating an IP core, IP1, of the target linear speed by using an IP generation guide of Xilinx;
step S3: extracting all parameters of the DRP configuration register: configuration parameters can be extracted using a high-level programming language, including: obtaining new parameter files IP0_ PARAM.txt and IP1_ PARAM.txt by the parameter name and the parameter value;
step S4: register difference parameter comparison and extraction: comparing the differences of the IP0_ PARAM.txt and IP1_ PARAM.txt files by using a text comparison tool, and copying a difference parameter line;
step S5: generating a minimal register list file: pasting the copied difference parameter line in a new text file to generate a difference result file diff _ param.txt which is a minimum parameter file needing configuration and is called as a minimal register configuration file;
step S6: and generating a configuration register list file: looking up a DRP address mapping table by comparing with a Transceiver user manual of RocktIO, converting register parameter names and parameter values listed in diff _ param.txt into configuration values of register addresses corresponding to DRPs one by one, and generating a configuration register list file cfg _ param.txt;
step S7: writing a configuration program: and writing an initialization configuration file required by the main control board, wherein the initialization configuration file comprises a linear speed dynamic configuration function.
2. The method for changing the line speed based on the RocktIO high-speed interface according to claim 1, wherein the RocktIO interface board is a Xilinx FPGA PCB board provided with the RocktIO interface, and a high-speed serial transceiver interface is realized by using a Xilinx transceiver IP interface; the Xilinx FPGA PCB board uses an AXI Master provided with a PCIe DMA Endpoint IP, converts the DRP interface through the AXI Master, and configures a DRP configuration interface of the RocktIO.
3. The method for changing the line speed of the high-speed interface based on the RocktIO as claimed in claim 1, wherein the RocktIO is a Xilinx GTX high-speed transceiver, and comprises a physical medium layer PMA and a physical control layer PCS; the physical medium layer PMA comprises a serializer and a deserializer, a sending and receiving buffer area, a high-speed clock generator and a line clock recovery unit; the physical control layer PCS comprises 8B/10B or 64B/66B coding and decoding, comma detection and bit alignment, PRBS pseudo-random code generation and verification, TX phase correction and phase correction control, RX clock correction and channel binding; the physical medium layer PMA is used for TX pre-enhancement, OOB and LPM low-power consumption automatic linear adaptation.
4. The method as claimed in claim 1, wherein the Xilinx transitionarvip interface includes four parts, a GTX bus interface, a DRP port, an application layer data receiving and transmitting port, and a status debugging monitoring port.
5. The method for changing the line speed of the high-speed interface based on the RocktIO of claim 4, wherein the GTX bus interface is a GTX physical fiber interface and supports simplex and full-duplex modes; the DRP port is a software or processor dynamic parameter configuration interface, and changes the working mode and the line rate of the RockettIO in a configuration register mode; the application layer transceiving data port consists of data sending and K code sending mark signals, data receiving and K code receiving mark signals; the state debugging monitoring port comprises a clock recovery port, a TX configurable driving port, an RX equalizer port, an RX polarity control port and a TX/RX8B/10B codec port.
6. The method of claim 1, wherein the main control board is a computer main board provided with an operating system.
7. The method as claimed in claim 1, wherein the high-level programming language includes C language, C + + language, tcl language or python language.
8. The RocktIO high-speed interface-based line speed changing method as recited in claim 1, wherein the text comparison tool is not limited to BeyondCompare.
9. The method for changing the line speed of the high-speed interface based on the RocktIO according to claim 1, which is characterized by comprising the following specific processes:
a1: initializing a RockettIO system;
a2: the method for changing the wire speed of the RocktIO high-speed interface according to claim 1, wherein the DRP port wire speed register of a certain lane of the RocktIO is configured;
a3: configuring a receiving and transmitting channel reset signal for soft resetting the lane;
a4: the lane initialization is successful, and the link up signal is pulled up;
a5: configuring DRP port linear speed registers of other lanes of RockettIO;
a6: configuring a receiving and transmitting channel reset signal for soft resetting other lanes;
a7: the lane initialization is successful, and the link up signal is pulled up;
a8: when the configuration linear speeds of all the channels are finished, data are received and transmitted;
a9: and verifying whether the configuration is successful or not by using software.
The RocktIO high-speed interface variable linear speed system is characterized in that the RocktIO high-speed interface variable linear speed system method based on any one of claims 1-9 is applied; the RocktIO high-speed interface variable line speed system comprises a RocktIO interface board, a PCIe back board and a main control board; the RocktIO interface board is connected with a PCIe mainboard; the PCIe back plate is connected with the main control board; the mounting RockIO interface board is a PCB board adopting Xilinx FPGA.
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| JP2009276914A (en) * | 2008-05-13 | 2009-11-26 | Fujitsu Ltd | Pseudo ddr memory interface circuit |
| US20190179989A1 (en) * | 2017-12-12 | 2019-06-13 | Synopsys, Inc. | Fpga-based hardware emulator system with an inter-fpga connection switch |
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Application publication date: 20211214 |
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