JP2009276914A - Pseudo ddr memory interface circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To transmit/receive large amounts of data by using a DDR memory interface, and to shorten the reading (read) latency, concerning a pseudo DDR memory interface circuit for achieving a high speed interface between signal processing blocks. <P>SOLUTION: The address of a transfer data block is predetermined at the point of time of receiving an RAS address from a DDR memory controller 6-11 of the other signal processing block 6-1, and an internal CAS address generation part 1-2 is initialized to the leading CAS address value of a pertinent RAS address region before a CAS address is actually input from an external DDR memory controller during read-out processing, and the CAS address is generated by the increment processing of the internal CAS address generation part 1-2. Data are read by using the CAS address, and output from a data generation part 6-25. Thus, it is possible to quickly output the transfer data, and to set read latency as a value adaptive to JEDEC specifications. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a pseudo DDR memory interface circuit that realizes a high-speed interface between signal processing blocks. More specifically, for example, data transfer can be performed with a DDR memory interface that is an interface such as DDR-SDRAM between signal processing blocks that exchange large amounts of data, such as signal processing blocks of cellular receivers and base station devices. The present invention relates to a pseudo DDR memory interface circuit.

  In recent years, it has become essential to provide high-quality communication services in data communication and voice communication in mobile communication systems. In addition, the amount of data to be processed is increasing in proportion to the number of users increasing year by year. Along with an increase in the amount of processing data, a large amount of data can be transferred at high speed between semiconductor processing components such as signal processing blocks, for example, FPGA (Field Programmable Gate Array), LSI (Large Scale Integration), and DSP (Digital Signal Processor). There is a need to communicate.

  A high-speed interface circuit such as SRIO (Serial Rapid IO) is used as an interface for exchanging data between the signal processing blocks as described above. However, inexpensive signal processing block semiconductor components are not always provided with a high-speed interface circuit such as SRIO, and a general DDR (Double Data Rate) memory interface is also used to reduce costs. It is required to realize a high-speed interface circuit at a low cost using the above.

A DDR memory interface as an interface between an external semiconductor memory device such as a DDR-SDRAM (Double Data Rate-Synchronous Dynamic Random Access Memory) and a signal processing block is described in, for example, Patent Documents 1 to 3 below. However, the present invention relates to an interface circuit that exchanges data between signal processing blocks using a DDR memory interface, not an interface between such an external semiconductor memory device and a signal processing block.
JP 2000-132966 A (particularly paragraphs 0006 to 0007) JP 2002-182974 A JP 2003-45179 A

  A DDR memory interface circuit mounted on a semiconductor component of a signal processing block such as a general DSP or FPGA is an interface circuit for exchanging data with an external semiconductor memory device, and includes a memory interface including refresh of a memory Is a circuit configuration as a memory controller that supervises the above.

  Therefore, even if the two signal processing blocks are directly connected via the DDR memory interface circuit as they are, the interface between them does not function effectively. When both signal processing blocks having only a function as a DDR memory controller are connected, a pseudo DDR memory that transfers data by acting like a memory in accordance with an instruction from the other DDR memory controller. It is necessary to implement an interface circuit.

  FIG. 6 shows a general configuration example of the pseudo DDR memory interface circuit. This figure shows a connection configuration example between a first signal processing block (DSP) 6-1 and a second signal processing block (FPGA) 6-2. In this configuration example, the first signal processing block (DSP) 6-1 to the second signal processing block (FPGA) using the DDR memory controller 6-11 of the first signal processing block (DSP) 6-1. An example of a circuit configuration for reading and transferring data 6-2 is shown.

  As shown in FIG. 6, the second signal processing block (FPGA) 6-2 includes an address decoder 6-21, a RAM and FF control unit 6-22, an internal RAM and FF (register) group block 6-23, and data. A pseudo DDR memory interface circuit including a capturing unit 6-24 and a data generating unit 6-25 is provided.

  The second signal processing block (FPGA) 6-2 receives control signals such as xRAS / xCAS / xCS / xWE and data to be transferred from the first signal processing block (DSP) 6-1 through the DDR memory interface. An A (address bus) signal including RAS address and CAS address information indicating information and a BA (burst address bus) signal are input.

  The address decoder 6-21 recognizes a command from the control signal and decodes address information from the A (address bus) signal and the BA (burst address bus) signal. The RAM and FF control unit 6-22 manages transmission / reception of the corresponding data in the internal RAM and FF (register) group block 6-23 from the decoding result by the address decoder 6-21.

  The internal RAM and FF (register) group block 6-23 temporarily holds data to be transmitted to and received from the DDR memory controller 6-11 of the first signal processing block (DSP) 6-1 and stores the data in the internal circuit 6 Deliver to and from -26. The data capture unit 6-24 captures input data (write data as viewed from the DDR memory controller 6-11) from the external bidirectional data bus (DQ), and stores it in the internal RAM and FF (register) group block 6-23. Store.

  The data generation unit 6-25 takes out output data (read data as viewed from the DDR memory controller 6-11) from the internal RAM and FF (register) group block 6-23, and outputs the data to the external bidirectional data bus (DQ). Create output data in a predetermined format.

  The data generation unit 6-25 is prepared for a rising edge that outputs data at the rising edge of the clock signal and for the falling edge that outputs data at the falling edge of the clock signal. This is because data transfer is performed at a double speed of the clock signal.

  The pseudo DDR memory interface circuit identifies the data block to be transferred by acquiring the RAS address, and then decodes the acquired CAS address. If the storage process is a read process, data is read from the internal RAM or FF group corresponding to the address in the data block. The RAS address indicates which data block area the information is, and the CAS address indicates the address of the storage area of each data in the data block.

  As described above, when viewed from the DDR memory controller 6-11, an interface for transmitting and receiving a large amount of data is realized by providing a pseudo DDR memory interface circuit that behaves as if data is being transmitted to and received from an external memory such as a DDR-SDRAM. can do. FIG. 7 shows an operation flow of this pseudo DDR memory interface circuit, and FIG. 8 shows a time chart of a data transfer example.

  As shown in FIG. 7, the operation in the pseudo DDR memory interface determines whether the xCS (negative logic chip select) signal and the xRAS (negative logic low address strobe) signal are at a low level (7-1). The command is acquired (7-2). Then, it is determined whether or not the command is an act command. If the command is an act command, a RAS address is acquired and a data block to be transmitted / received is selected (7-4).

  Next, it is determined whether the xCS (negative logic chip select) signal and the xCAS (negative logic column address strobe) signal are at a low level (7-5). ) Next, it is determined whether or not the xWE (negative logic write enable) signal is at a high level (7-7). If the xWE (negative logic write enable) signal is at a high level, a read process is performed. Data is taken in from 23 (7-8). Then, from the data fetched from the internal RAM and FF (register) group block 6-23, the data generator 6-25 generates and outputs as output data in the format of the external bidirectional data bus (DQ) (7- 9).

  If it is determined in 7-7 above that the xWE (negative logic write enable) signal is not at a high level, data is fetched from the external bidirectional data bus (DQ) in order to perform write processing (7 -10), data is stored in the corresponding internal RAM and FF (register) group block 6-23 (7-11).

  By providing the above-described pseudo DDR memory interface circuit, it is possible to realize transmission and reception of a large amount of data between signal processing blocks such as between FPGA and DSP using the DDR memory interface. However, in both the writing process and the reading process, after acquiring the RAS address, the CAS address is taken in, and then the memory space or the FF group inside the signal processing block (FPGA) is accessed. It takes a lot of time to access. Therefore, the data transfer latency (waiting time) cannot satisfy the JEDEC (Joint Electronic Device Engineering Council) standard.

  As shown in the time chart example of FIG. 8, the reading process takes 2 clocks for decoding after fetching the CAS address from the external input signal at timing T1 in the pseudo DDR memory interface circuit, and then the internal data It takes 4 clocks to fetch the data and generate the output data, and the read data is output to the data bus (DQ) at timing T2. Therefore, the read latency from the timing T1 at which the CAS address is fetched to the timing T2 at which the data is output is 6. An enlarged view of the first half of the time chart of FIG. 8 is shown in FIG. 14, and an enlarged view of the second half of the time chart of FIG. 8 is shown in FIG.

  The write process is easy because the address bus signal and the data bus signal are both input signals to the second signal processing block (FPGA), and the number of FFs (the number of shift register stages) of any signal is adjusted. However, with regard to read processing, the number of FFs (the number of shift register stages) alone cannot cope with it, and the realization of the latency that satisfies the JEDEC standard is impossible only by improving the circuit. is there.

  FIG. 9 shows a list of DDR memory interface latencies according to JEDEC standardization and latencies in the above-described general pseudo DDR memory interface circuit. As shown in the table, according to the JEDEC standardization standard, a read (read) latency after capturing a CAS address is specified within 2 to 3 clocks, and a write (write) latency is specified within 1 clock.

  On the other hand, in the above-described general pseudo DDR memory interface circuit, the read (read) latency after fetching the CAS address is 6 clocks, and the write (write) latency is 2 clocks. Reed) latency was far away from the JEDEC standardization standard.

  An object of the present invention is to provide a pseudo DDR memory interface circuit that uses a DDR memory interface between signal processing blocks, enables transmission / reception of a large amount of data, has a small read (read) latency, and satisfies the JEDEC standardization standard. .

  In order to solve the above problem, the pseudo DDR memory interface circuit is a pseudo DDR memory interface circuit in a signal processing block that performs data transfer with another signal processing block and a DDR memory interface. When the RAS address indicating the area of the data block to be transferred to the signal processing block is received from the DDR memory controller, the CAS address that is the address of the storage area of each data in the data block is received from the DDR memory controller. Data is read using the internal CAS address generation means that is generated in advance and the CAS address generated by the internal CAS address generation means, and the read data is read in the format by the DDR memory interface. A data generating means for outputting to the issue processing block, in which with a.

  According to this pseudo DDR memory interface circuit, a large amount of data can be transmitted / received between inexpensive signal processing blocks not equipped with a high-speed interface circuit such as SRIO (Serial Rapid IO) by using a DDR memory interface, and also read out. (Lead) latency is low, and it is possible to achieve a latency that satisfies the JEDEC standardization standard.

  This pseudo DDR memory interface circuit internally generates a CAS address from the reception time of the RAS address and reads the data of the CAS address prior to the input of the CAS address from the DDR memory controller of another signal processing block. Thus, the read (read) latency is shortened. However, the following conditions are applied to the interface between signal processing blocks.

  First, as a first condition, burst transfer for transferring a group of continuous data between signal processing blocks is performed, and data of a CAS address whose address value is gradually increased (incremented) from data of the same RAS address. Shall be transferred. However, there is no limit on the size of transfer data.

  As a second condition, the RAS address designated from the external DDR memory controller is separated at the time of the writing process and at the time of the reading process, and the same data block is divided at the time of the writing process and the reading process. Designated by RAS address. For example, in order to read back the contents of a register that has undergone a write process, when a read process is performed on the same register, a different address different from that at the time of writing is assigned and read.

  By attaching the above conditions, it is possible to recognize the act command by the xCS signal and determine the write process or the read process when the RAS address is acquired, and specify the address of the block of the transfer target data. Thus, at the time of read processing, before the CAS address is actually input from the external DDR memory controller, the internal CAS address generation unit is initialized to the first CAS address value of the corresponding RAS address area, and the internal CAS address generation is performed. A CAS address is generated internally by incrementing the counter of each section.

  Then, using the internally generated CAS address, the transfer data can be quickly read out by reading the transfer data prior to the CAS address input from the DDR memory controller, and the read latency (CAS latency) conforms to the JEDEC standard. A suitable value can be set.

  Also, the actual CAS address input from the external DDR memory controller is monitored, and the output is controlled based on the actually input CAS address with respect to the preceding read data read in advance from the internal RAM or FF group. Thus, control is performed so that data (unnecessary data) other than the requested data is not output to the external memory controller.

  Note that the latency adjustment during the writing process can be easily adjusted by increasing / decreasing the number of shift register stages of the data bus (increasing / decreasing the number of FF stages) or the like, and thus the description thereof is omitted. However, since an auto-refresh command is interrupted from the external DDR memory controller to hold the memory contents at an arbitrary timing, it is necessary to have a function to cope with access interruption / recovery.

  Since auto-refresh occurs at an arbitrary timing, it is determined whether or not the data transfer is interrupted due to the occurrence of the auto-refresh. If the data transfer is interrupted, the CAS address requested before the data transfer is interrupted. Stops output of preceding read data other than data.

  After completion of the refresh operation, in accordance with a request from the external DDR memory controller, the internal address generation unit generates a CAS address from the continuation of the CAS address when the data transfer is interrupted, outputs the CAS address data, Perform no data transfer.

  FIG. 1 shows a configuration of a first embodiment of the above-described pseudo DDR memory interface circuit. This is a command decoder 1-1 for determining a command from xCS, xRAS signal, xCAS signal, xWE signal, and other control signals, instead of the address decoder 6-21 having the pseudo DDR memory interface circuit configuration shown in FIG. An internal CAS address generation unit 1-2 for generating a CAS address in advance, an interruption monitoring unit 1-3 for determining whether or not the occurrence of refresh is during data transfer, and a preceding based on the CAS address actually input And a CAS address decoder 1-4 for instructing an output mask for the read data.

  The command decoder 1-1 determines from the control signal input from the DDR memory controller 6-11 whether the input command is an act command, a refresh command, or a read or write when it is an act command. The internal CAS address generation unit 1-2 generates a CAS address by increment processing from the leading CAS address value in the RAS address area.

  When a refresh command is input, the interruption monitoring unit 1-3 compares the RAS address of data transfer input before the refresh command with the RAS address of data transfer input after the refresh command, If they are the same, it is determined that a refresh command has occurred during data transfer, and if they are different, it is determined that the refresh command has occurred during idle and does not affect data transfer.

  The CAS address decoder 1-4 decodes the CAS address actually input from the DDR memory controller 6-11, exceeds the CAS address of the data transfer requested from the DDR memory controller 6-11, and reads the preceding read data. The data generation unit 6-25 is instructed to mask the data output of the CAS address generated by the internal CAS address generation unit 1-2 so that it is not output.

  FIG. 2 shows an operation flow of the first embodiment. The processing operation of the first embodiment will be described below with reference to FIG. The command decoder 1-1 determines whether or not the xRAS (negative logic low address strobe) signal is at a low level (2-1), and obtains a command (2-2) when it is at a low level. Then, it is determined whether or not the command is an act command (2-3). If it is an act command, a RAS address is acquired and a data block to be transmitted / received is selected (2-4).

  Next, it is determined whether or not the refresh flag is set to 1 (2-5). If it is not set to 1, it is read (read) processing or write (write) processing from the acquired RAS address. Is determined (2-6). If it is determined that this is a write process, the write process is performed (2-14). The refresh flag will be described later in detail.

  If it is determined that the reading (reading) processing is performed in the above determination, it is determined whether or not the interruption flag is set to 1 (2-7). If the interruption flag is not set to 1, the acquired RAS address is used. The data block is determined, and the counter value of the internal CAS address generation unit 1-2 is initialized to the first address value of the data block (2-8). The interrupt flag will be described later in detail.

  Using the internal CAS address value generated from the internal CAS address generator 1-2 from the next clock, the data is fetched from the internal RAM and FF (register) group block 6-23, the data is converted in format and output. (2-9), and the counter of the internal CAS address generator 1-2 is incremented (2-10).

  At the same time, the xCAS signal is monitored to determine whether the xCAS signal is at a low level, that is, whether or not there is an access (2-11). repeat. When the xCAS signal is at a high level, that is, when the CAS access is stopped, the output of the data of the internal CAS address value is masked by the data generation unit 6-25, and the output of unrequested data is stopped. Then, the internal RAS address variable of the CAS address generation unit 1-2 is cleared (2-13), and the process ends. The RAS address variable will be described in detail later.

  FIG. 3 shows a time chart of the read process according to the first embodiment. As shown in FIG. 3, in the read process according to the first embodiment, after the CAS address is taken in from the external input signal at the timing T1 by the early data read start process by the internal generation of the internal CAS address, the read data is read at the timing T2 after 3 clocks. Is output to the data bus (DQ). An enlarged view of the first half of the time chart of FIG. 3 is shown in FIG. 10, and an enlarged view of the latter half of the time chart of FIG. 3 is shown in FIG.

  If 0x000, 0x004, 0x008, and 0X00C are captured as external CAS address latch information of the CAS address decoder (CAS decoding unit), data a (0, 1), b (2, corresponding to these CAS addresses are assumed. 3), ..., h (14, 15) are read and output. However, the last CAS address 0X00C is held, and output of data exceeding the CAS address 0X00C is masked.

  As described above, in the pseudo DDR memory interface circuit according to the first embodiment, the internal CAS address generation unit 1-2 generates the CAS address in advance and reads the data to thereby read the pseudo DDR memory interface illustrated in FIGS. The operation satisfying the read latency 3 can be performed by adjusting the timing interval from the act command to the CAS address input by one clock.

  However, the above-described processing alone cannot cope with interruption / resumption of data transfer due to a refresh command input from the external DDR memory controller 6-11 at an arbitrary timing, and data transfer is lost. .

  In order to cope with this, when the command decoder 1-1 recognizes the refresh command, the following processing is performed. In the processing flow of FIG. 2, it is determined whether or not the acquired command is a refresh command (2-21). If the command is a refresh command, the current RAS address is acquired and held in an internal RAS address variable. (2-22) The refresh flag is set to 1 (2-23), and the processing returns to the above-described processing flow 2-1, and the same processing is repeated.

  Next, when the act command is recognized (2-3) and the RAS address is acquired (2-4), the refresh flag is set to 1 in the determination of the refresh flag (2-5). If it is determined, the RAS address held last time is compared with the newly input RAS address, and it is determined whether or not they match (2-24).

  If they do not match, a refresh command is input in the idle state, that is, data transfer is not in progress, and it is determined that the data transfer has not been interrupted, the interrupt flag is set to 0, and the refresh flag is cleared ( 2-25). Then, the process proceeds to the above-described process flow 2-6, where the counter of the internal CAS address generation unit 1-2 is initialized with the newly acquired RAS address, and the read process is performed.

  If it is determined in the processing flow 2-24 that the RAS addresses coincide with each other, it is determined that the data transfer is interrupted by the refresh, the interrupt flag is set to 1, and the refresh flag is cleared (2-26). ) Then, the process proceeds to the above-described processing flow 2-6, and when it is determined that the interruption flag is set to 1 in the interruption flag determination (2-7), the counter of the internal CAS address generation unit 1-2 is initialized. Without performing the above, the value obtained by incrementing the latch information of the external CAS address output last time is loaded into the internal CAS counter, and the interruption flag is cleared (2-27).

  FIG. 4 shows a time chart of a processing example of interruption / recovery of data transfer by auto refresh. As shown in the figure, if a refresh command is fetched at timing T3, the interruption monitoring unit 1-3 reads the RAS address (indicated by “ROW” in the figure) 0x000 inputted before that, and thereafter The input RAS address 0x000 is compared and the interruption flag is set to a high level because they match. An enlarged view of the first half of the time chart of FIG. 4 is shown in FIG. 12, and an enlarged view of the latter half of the time chart of FIG. 4 is shown in FIG.

  Then, the value 0x10 obtained by incrementing the latch information 0x00C of the external CAS address at this time is set in the internal CAS address generation unit 1-2. Thus, after the refresh is completed, the transfer of the data k (16, 17) and k (18, 19) at the next CAS address 0x10 is resumed.

  FIG. 5 shows the configuration of the second embodiment. The difference from the first embodiment is that a CAS address monitoring unit 5-1 is newly provided. The CAS address monitoring unit 5-1 addresses the address value output from the internal CAS address generation unit 1-2 and the CAS address value input from the outside at the read data output timing, corresponding to the read data. Compare with each other.

  If the two addresses match, it is determined that the communication state is normal. If a mismatch between the two addresses is detected, the CAS address requested by the DDR memory controller 6-11 is determined. Since the data is not read from the correct address, it is determined that the communication state is abnormal and an interface error has occurred.

  When the occurrence of the interface error is detected, a reacquisition request for the corresponding RAS address area data is transmitted to the DDR memory controller 6-11, and the corresponding RAS address is reacquired from the DDR memory controller 6-11, resulting in an interface error. By transferring the data again, the reliability of data transfer can be improved.

  Further, a threshold value for the number of occurrences of interface errors is set in advance, and when the number of occurrences of interface errors exceeds the threshold value, alarm information is notified to a higher-level signal processing unit (MPU), and the signal processing block The reliability can be further improved by performing alarm processing (processing for failure) in the mounted card.

It is a figure which shows the structural example of a pseudo DDR memory interface circuit (Example 1). It is a figure which shows the operation | movement flow of a pseudo DDR memory interface circuit (Example 1). 6 is a time chart of a read process of a pseudo DDR memory interface circuit (first embodiment). It is a time chart of the example of a process of interruption and recovery of data transfer by auto refresh. It is a figure which shows the structural example of a pseudo DDR memory interface circuit (Example 2). It is a figure which shows the general structural example of a pseudo DDR memory interface circuit. It is a figure which shows the operation | movement flow of a general pseudo DDR memory interface circuit. It is a time chart of the data transfer example of a general pseudo DDR memory interface circuit. It is a figure which shows the latency list of the latency of a JEDEC standardization standard, and the latency of a general pseudo DDR memory interface circuit. FIG. 4 is an enlarged view of the first half portion of the time chart of FIG. 3. FIG. 4 is an enlarged view of the latter half of the time chart of FIG. 3. It is an enlarged view of the first half part of the time chart of FIG. It is an enlarged view of the second half part of the time chart of FIG. It is an enlarged view of the first half part of the time chart of FIG. It is an enlarged view of the second half part of the time chart of FIG.

Explanation of symbols

1-1 Command Decoder 1-2 Internal CAS Address Generation Unit 1-3 Suspension Monitoring Unit 1-4 CAS Address Decoder 5-1 CAS Address Monitoring Unit 6-1 First Signal Processing Block (DSP)
6-11 DDR memory controller 6-2 Second signal processing block (FPGA)
6-22 RAM and FF Control Unit 6-23 Internal RAM and FF (Register) Group Block 6-24 Data Capture Unit 6-25 Data Generation Unit 6-26 Internal Circuit

Claims (5)

A pseudo DDR memory interface circuit in a signal processing block that performs data transfer with another signal processing block and a DDR memory interface,
When the RAS address indicating the data block area to be transferred to the signal processing block is received from the DDR memory controller of the other signal processing block, the CAS address that is the address of the storage area of each data in the data block is Internal CAS address generation means for generating in advance before receiving from the DDR memory controller;
Data generation means for reading data using the CAS address generated by the internal CAS address generation means, and outputting the read data to the other signal processing block in a format by the DDR memory interface;
A pseudo DDR memory interface circuit comprising:   The output of the data read using the CAS address generated by the internal CAS address generation means to the other signal processing block is monitored based on the CAS address input from the DDR memory controller, and the DDR memory controller 2. The pseudo DDR memory interface circuit according to claim 1, wherein means for stopping output of data at a CAS address exceeding a value of a CAS address input from the data generation means is provided. Means for recognizing a refresh command input from the DDR memory controller and determining whether or not the data transfer is interrupted by the refresh command by determining whether the RAS addresses of the data transfer before and after the refresh process coincide with each other When,
When the data transfer is interrupted, after the refresh process is completed, a CAS address is generated by the internal CAS address generating means based on the CAS address before the data transfer is interrupted, and data is generated using the generated CAS address. Means for resuming reading and data transfer;
The pseudo DDR memory interface circuit according to claim 1, further comprising:   When the CAS address generated by the internal CAS address generation means and the CAS address input from the DDR memory controller are compared, and a mismatch is detected as the CAS address of the output data, it is determined that an interface error has occurred. 4. The apparatus according to claim 1, further comprising means for transmitting a request for reacquisition of the corresponding RAS address area data to the DDR memory controller, and retransmitting the data having the interface error again. Pseudo DDR memory interface circuit.   5. The pseudo DDR memory interface circuit according to claim 4, further comprising means for monitoring the number of occurrences of the interface error and notifying the upper signal processing device of alarm information when the number of occurrences exceeds a threshold value.

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