CN113782435B - Manufacturing method of cut-first SDB FinFET - Google Patents
Manufacturing method of cut-first SDB FinFET Download PDFInfo
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- CN113782435B CN113782435B CN202110924952.2A CN202110924952A CN113782435B CN 113782435 B CN113782435 B CN 113782435B CN 202110924952 A CN202110924952 A CN 202110924952A CN 113782435 B CN113782435 B CN 113782435B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 239000010410 layer Substances 0.000 claims abstract description 164
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 238000000151 deposition Methods 0.000 claims abstract description 28
- 229910052751 metal Inorganic materials 0.000 claims abstract description 19
- 239000002184 metal Substances 0.000 claims abstract description 19
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 16
- 239000011229 interlayer Substances 0.000 claims abstract description 14
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 13
- 238000000227 grinding Methods 0.000 claims abstract description 11
- 238000000137 annealing Methods 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 27
- 238000005498 polishing Methods 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 238000000231 atomic layer deposition Methods 0.000 claims description 3
- 238000011065 in-situ storage Methods 0.000 claims description 3
- 238000009740 moulding (composite fabrication) Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000010408 film Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
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- 230000003993 interaction Effects 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
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Abstract
The invention provides a manufacturing method of a cut-first SDB FinFET.A plurality of Fin structures are formed on a substrate at intervals along the longitudinal direction, and a SiN layer is formed on the Fin structures; depositing a thin oxide layer; annealing after depositing the dielectric layer; grinding to expose the upper surface of the SiN layer; forming an SDB photoresist pattern on the SiN layer; etching the SiN layer and the Fin structure along the SDB photoresist pattern to form an SDB groove; forming an oxide layer at the bottom of the SDB groove; forming SiN in the middle of the SDB groove; forming SiC on top of the SDB groove; removing the SiN layer to expose the upper surface of the Fin structure and expose the SiC; forming a plurality of dummy gates arranged at intervals along the transverse direction on the Fin structure and the SDB groove; forming a SiP epitaxial structure on the Fin structure between two adjacent dummy gates at one side of the SDB groove; forming a SiGe epitaxial structure on the Fin structure between two adjacent dummy gates on the other side of the SDB groove; depositing an interlayer dielectric layer to cover the pseudo grid electrode; grinding the interlayer dielectric layer until the top of the pseudo grid is exposed; removing the pseudo grid electrode to form a groove; forming HK metal gate.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a cut-first SDB FinFET.
Background
Logic designs in the logic standard cells are created using standard cells. The height of the cell is the number of tracks times the metal Pitch (Pitch), the tracks and Pitch being measured with metal layer 2 (M2). Fig. 1 shows a schematic diagram of a 7.5 track unit, with half the Power and Ground rail (Ground) heights in the upper and lower units, respectively.
The cell width is related to the poly contact pitch (contact poly pitch, CPP), and the number of CPPs that make up the cell width depends on the cell type and whether the cell has Double Diffused Break (DDB) or Single Diffused Break (SDB).
One DDB adds one half CPP on each side of the cell. For actual cells, such as NAND gates and cell scan flip-flops, the number of CPPs across the cell width is greater and the SDB has less impact on DDB.
In the cut-ahead SDB process, after ILD fill is formed and planarized, the dummy gate will be removed, followed by filling the HK metal gate stack, which will present two problems: 1) The spacing between the epitaxial layer and the polysilicon is very small around the SDB, and the interaction between the epitaxial layer and the polysilicon is also very strong; 2) After the dummy gate is removed, siGe or SiP stress is relieved, which will degrade device performance; 3) After the HK metal gate stack fills the recess, the metal gate and tungsten electrode pressures will react to SiGe or SiP pressures, which will be beneficial for PMOS or NMOS, but will reduce the performance of the other of the two; 4) In view of the above, SDB devices vary greatly in actual circuits depending on the actual situation.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a method for manufacturing a cut-first SDB FinFET, which is used to solve the problem that in the SDB cut-first process in the prior art, the metal gate and tungsten electrode pressures react to SiGe or SiP pressures, resulting in reduced device performance.
To achieve the above and other related objects, the present invention provides a method for manufacturing a cut-before-first SDB FinFET, comprising at least:
Providing a substrate, and forming a plurality of Fin structures which are arranged at intervals along the longitudinal direction on the substrate, wherein the length direction of the Fin structures is a transverse direction perpendicular to the longitudinal direction; a SiN layer is formed on the Fin structure; a first hard mask layer is formed on the SiN layer;
Depositing a thin oxide layer, wherein the thin oxide layer covers the upper surface of the substrate and the Fin structure;
Depositing a dielectric layer on the substrate to cover the upper surface of the substrate and the thin oxide layer, and then annealing;
grinding the dielectric layer and the thin oxide layer until the upper surface of the SiN layer is exposed;
Fifthly, forming an SDB photoresist pattern on the SiN layer of the Fin structure;
step six, etching the SiN layer and the Fin structure along the SDB photoresist pattern to form an SDB groove;
step seven, forming an oxide layer at the bottom of the SDB groove;
step eight, forming SiN on the middle part of the SDB groove and the oxide layer;
Step nine, forming SiC on the SiN at the top of the SDB groove;
removing the SiN layer to expose the upper surface of the Fin structure and expose the SiC;
Eleventh, forming a plurality of dummy grids and side walls attached to the dummy grids along the transverse interval on the Fin structure and the SDB groove;
Twelve, forming a SiP epitaxial structure on the Fin structure between the two adjacent dummy gates at one side of the SDB groove; forming a SiGe epitaxial structure on the Fin structure between the two adjacent dummy gates at the other side of the SDB groove;
thirteenth, depositing an interlayer dielectric layer to cover the dummy gates and filling the space between the dummy gates; grinding the interlayer dielectric layer until the top of the pseudo grid electrode is exposed;
Fourteen, removing the pseudo grid electrode to form a groove; and filling HK metal in the grooves to form HK metal gates.
Preferably, the method of depositing the thin oxide layer on the upper surface of the substrate and the side wall of the Fin structure in the second step is an atomic layer deposition method or an in-situ vapor generation method.
Preferably, the method for depositing the dielectric layer in the third step is FCVD.
Preferably, the polishing in the fourth step is chemical mechanical polishing.
Preferably, in the seventh step, the method for forming an oxide layer in the SDB groove includes: and depositing a layer of oxide on the SDB groove, and then carrying out back etching to form the oxide layer at the bottom of the SDB groove.
Preferably, in the eighth step, the method for forming SiN in the middle of the SDB groove includes: and depositing a layer of SiN in the SDB groove, and then etching back to form SiN in the middle of the SDB groove and on the oxide layer.
Preferably, in step nine, the method for forming SiC on top of the SDB groove is as follows: and depositing a layer of SiC on the SiN in the SDB groove, then forming back etching and grinding, and forming SiC with the upper surface flush with the upper surface of the SiN layer on the SiN of the SDB groove.
Preferably, in step eleven, the dummy gate includes a polysilicon layer, and a second hard mask layer on the polysilicon layer.
Preferably, in step twelve, the number of the SiP epitaxial structures formed on the Fin structure between the two adjacent dummy gates at one side of the SDB groove is two.
Preferably, in step twelve, the number of SiGe epitaxial structures formed on the Fin structure between the two adjacent dummy gates on the other side of the SDB groove is two.
As described above, the method for manufacturing the cut-first SDB FinFET of the present invention has the following advantages: the oxide layer is filled at the bottom of the SDB groove by using the FCVD method, so that the filling capacity is good; filling SiC at the top of the SDB groove can avoid the problem of film loss caused by subsequent SiN layer removal; according to the invention, three thin film stacks are formed in the SDB groove, so that the pressure release risk of the SiP epitaxial layer and the SiGe epitaxial layer is reduced; since the SiP epitaxial layer and the SiGe epitaxial layer are separate, the stress released by the HK metal gate does not affect the SiP epitaxial layer and the SiGe epitaxial layer.
Drawings
FIG. 1 shows a schematic diagram of a 7.5 track unit;
FIG. 2a is a schematic cross-sectional view of a Fin structure formed on a substrate according to the present invention;
FIG. 2b is a schematic longitudinal cross-sectional view of a substrate with Fin structures formed thereon according to the present invention;
FIG. 3a is a schematic cross-sectional view of a thin oxide layer formed on a substrate according to the present invention;
FIG. 3b is a schematic view of a longitudinal cross-section of the thin oxide layer formed on a substrate according to the present invention;
FIG. 4a is a schematic cross-sectional view of a dielectric layer formed on a substrate according to the present invention;
FIG. 4b is a schematic view showing a longitudinal cross-sectional structure of the present invention after forming a dielectric layer on a substrate;
FIG. 5a is a schematic cross-sectional view showing the structure of the SiN layer exposed after polishing in the present invention;
FIG. 5b is a schematic view showing a longitudinal cross-sectional structure of an exposed SiN layer after polishing according to the present invention;
FIG. 6a is a schematic diagram showing a cross-sectional structure of the SDB photoresist pattern formed according to the present invention;
6b is a schematic diagram of a longitudinal cross-sectional structure after SDB photoresist pattern is formed in the present invention;
FIG. 7a is a schematic diagram showing a cross-sectional view of the SDB groove formed in accordance with the present invention;
FIG. 7b is a schematic view showing a longitudinal cross-sectional structure of the SDB groove formed in the present invention;
FIG. 8a is a schematic diagram showing a cross-sectional view of an oxide layer formed in an SDB groove according to the present invention;
FIG. 8b is a schematic view showing a longitudinal cross-sectional structure of the SDB groove after forming an oxide layer in the SDB groove according to the present invention;
FIG. 9a is a schematic diagram showing a cross-sectional structure of the SDB groove of the present invention after SiN is formed in the middle of the groove;
FIG. 9b is a schematic view showing a longitudinal cross-sectional structure of the SDB groove of the present invention after SiN is formed in the middle of the groove;
FIG. 10a is a schematic cross-sectional view of the formation of SiC on top of an SDB groove in accordance with the present invention;
FIG. 10b is a schematic view of a longitudinal cross-section of the present invention for forming SiC on top of an SDB groove;
FIG. 11a is a schematic diagram showing a cross-sectional structure of the SiN layer removed after exposing the top surface of the Fin structure and SiC in accordance with the present invention;
FIG. 11b is a schematic view showing a longitudinal cross-sectional structure of the invention after removing the SiN layer to expose the top surface of the Fin structure;
FIG. 12a is a schematic cross-sectional view showing the structure of the present invention after removing the oxide between the Fin structure and the SiN layer;
FIG. 12b is a schematic view showing a longitudinal cross-sectional structure of the present invention after removing the oxide between the Fin structure and the SiN layer;
fig. 13a is a schematic cross-sectional view of the present invention after forming a dummy gate;
fig. 13b is a schematic view showing a longitudinal cross-sectional structure after forming the dummy gate in the present invention;
fig. 14a is a schematic cross-sectional view of the epitaxial structure formed in accordance with the present invention;
fig. 14b is a schematic view of a longitudinal cross-sectional structure of the invention after forming an epitaxial structure;
FIG. 15a is a schematic cross-sectional view of the present invention after deposition of an interlayer dielectric layer to cover the dummy gate;
FIG. 15b is a schematic view showing a longitudinal cross-section of the deposited interlayer dielectric layer covering the dummy gate in accordance with the present invention;
FIG. 16a is a schematic cross-sectional view of the HK metal gate formed in accordance with the present invention;
FIG. 16b is a schematic view showing a longitudinal cross-sectional structure of the HK metal gate after formation in accordance with the present invention;
fig. 17 is a flowchart illustrating a method of fabricating a cut-first SDB FinFET in accordance with the present invention.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 2 to 17. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
The invention provides a manufacturing method of a cut-first SDB FinFET, as shown in FIG. 17, FIG. 17 shows a flow chart of the manufacturing method of the cut-first SDB FinFET, which at least comprises the following steps:
Providing a substrate, and forming a plurality of Fin structures which are arranged at intervals along the longitudinal direction on the substrate, wherein the length direction of the Fin structures is a transverse direction perpendicular to the longitudinal direction; a SiN layer is formed on the Fin structure; a first hard mask layer is formed on the SiN layer; FIG. 2a is a schematic cross-sectional view of FIG. 2b, wherein FIG. 2a is a schematic cross-sectional view of a Fin structure formed on a substrate according to the present invention; FIG. 2b is a schematic longitudinal cross-sectional view of a substrate with Fin structures formed thereon according to the present invention; in the first step, a plurality of Fin structures 02 are formed on the substrate 01 at intervals along the longitudinal direction, and the length direction of the Fin structures 02 is a transverse direction perpendicular to the longitudinal direction; a SiN layer 03 is formed on the Fin structure 02; a first hard mask layer 04 is formed on the SiN layer 03.
Depositing a thin oxide layer, wherein the thin oxide layer covers the upper surface of the substrate and the Fin structure; as shown in fig. 3a and 3b, fig. 3a is a schematic cross-sectional view of the thin oxide layer formed on the substrate according to the present invention; FIG. 3b is a schematic view of a longitudinal cross-section of the thin oxide layer formed on a substrate according to the present invention; in the second step, the thin oxide layer 05 is deposited, and the thin oxide layer 05 covers the upper surface of the substrate 01 and the Fin structure 02.
In the second step of this embodiment, the method of depositing the thin oxide layer 05 on the upper surface of the substrate 01 and the side wall of the Fin structure 02 is an atomic layer deposition method or an in-situ vapor generation method.
Depositing a dielectric layer on the substrate to cover the upper surface of the substrate and the thin oxide layer, and then annealing; as shown in fig. 4a and 4b, fig. 4a is a schematic cross-sectional view of the dielectric layer formed on the substrate according to the present invention; fig. 4b is a schematic view of a longitudinal cross-section of the dielectric layer formed on the substrate according to the present invention. In the third step, a dielectric layer 06 is deposited on the substrate 01 to cover the upper surface of the substrate 01 and the thin oxide layer 05, and then annealing is performed.
In the third step of the present embodiment, the method for depositing the dielectric layer 06 is FCVD.
Grinding the dielectric layer and the thin oxide layer until the upper surface of the SiN layer is exposed; as shown in fig. 5a and 5b, fig. 5a is a schematic view showing a cross-sectional structure of an SiN layer exposed after polishing in the present invention;
FIG. 5b is a schematic view showing a longitudinal cross-sectional structure of an exposed SiN layer after polishing in the present invention. In the fourth step, the dielectric layer 06 and the thin oxide layer 05 are polished until the upper surface of the SiN layer 03 is exposed.
Further, the polishing in the step four of the present embodiment is chemical mechanical polishing.
Fifthly, forming an SDB photoresist pattern on the SiN layer of the Fin structure; as shown in fig. 6a and 6b, fig. 6a is a schematic diagram showing a lateral cross-sectional structure after SDB photoresist pattern formation in the present invention; fig. 6b is a schematic view showing a longitudinal cross-sectional structure after the SDB photoresist pattern is formed in the present invention. In the fifth step, an SDB photoresist pattern 07 is formed on the SiN layer 03 of the Fin structure 02.
Step six, etching the SiN layer and the Fin structure along the SDB photoresist pattern to form an SDB groove; as shown in fig. 7a and 7b, fig. 7a is a schematic view showing a transverse cross-sectional structure after forming the SDB groove according to the present invention; fig. 7b is a schematic view showing a longitudinal cross-sectional structure of the SDB groove formed in the present invention. In the sixth step, the SiN layer 03 and the Fin structure 02 are etched along the SDB photoresist pattern 07 to form an SDB groove 08.
Step seven, forming an oxide layer at the bottom of the SDB groove; as shown in fig. 8a and 8b, fig. 8a is a schematic view showing a cross-sectional structure of the SDB groove after forming an oxide layer in the SDB groove according to the present invention; fig. 8b is a schematic view showing a longitudinal cross-sectional structure of the SDB groove according to the present invention after an oxide layer is formed therein. In this step seven, the oxide layer 09 is formed at the bottom of the SDB groove 08.
The method for forming an oxide layer in the SDB groove in the seventh step of the present embodiment further includes: and depositing a layer of oxide on the SDB groove, and then carrying out back etching to form the oxide layer at the bottom of the SDB groove.
Step eight, forming SiN on the middle part of the SDB groove and the oxide layer; as shown in fig. 9a and 9b, fig. 9a is a schematic view showing a cross-sectional structure of the SDB groove of the present invention after SiN is formed in the middle of the SDB groove; fig. 9b is a schematic view showing a longitudinal cross-sectional structure of the present invention after SiN is formed in the middle of the SDB groove. In the eighth step, siN (10) is formed on the oxide layer 09 in the middle of the SDB groove.
In the eighth step of the present embodiment, the method for forming SiN in the middle of the SDB groove includes: and depositing a layer of SiN in the SDB groove, and then etching back to form SiN in the middle of the SDB groove and on the oxide layer.
Step nine, forming SiC on the SiN at the top of the SDB groove; as shown in fig. 10a and 10b, fig. 10a is a schematic view showing a lateral cross section of SiC formed on top of SDB grooves in the present invention; fig. 10b shows a schematic longitudinal cross-section of SiC formed on top of an SDB groove in accordance with the present invention. In step nine, siC (11) is formed on top of the SDB recess, on the SiN (10).
The method for forming SiC on top of the SDB groove in step nine of the present embodiment further includes: and depositing a layer of SiC on the SiN in the SDB groove, then forming back etching and grinding, and forming SiC with the upper surface flush with the upper surface of the SiN layer on the SiN of the SDB groove.
Removing the SiN layer to expose the upper surface of the Fin structure and expose the SiC; as shown in fig. 11a and 11b, fig. 11a is a schematic diagram showing a cross-sectional structure of the SiN layer removed after the Fin structure upper surface and SiC are exposed in the present invention; FIG. 11b is a schematic view showing a longitudinal cross-sectional structure of the invention after removing the SiN layer to expose the top surface of the Fin structure. In this embodiment, a layer of oxide is further present between the SiN layer and the upper surface of the Fin structure, as shown in fig. 12a and 12b, and fig. 12a is a schematic cross-sectional view of the Fin structure after removing the oxide between the Fin structure and the SiN layer in the present invention; FIG. 12b is a schematic view showing a longitudinal cross-sectional structure of the present invention after removing the oxide between the Fin structure and the SiN layer.
Eleventh, forming a plurality of dummy grids and side walls attached to the dummy grids along the transverse interval on the Fin structure and the SDB groove; as shown in fig. 13a and 13b, fig. 13a is a schematic view showing a cross-sectional structure after forming a dummy gate in the present invention; fig. 13b is a schematic view showing a longitudinal cross-sectional structure after forming the dummy gate in the present invention. In the eleventh step, a plurality of dummy gates 12 and spacers 13 attached to the dummy gates 12 are formed on the Fin structure 02 and the SDB groove and arranged at intervals in the lateral direction.
Further, in step eleven of this embodiment, the dummy gate 12 includes a polysilicon layer and a second hard mask layer on the polysilicon layer.
Twelve, forming a SiP epitaxial structure on the Fin structure between the two adjacent dummy gates at one side of the SDB groove; forming a SiGe epitaxial structure on the Fin structure between the two adjacent dummy gates at the other side of the SDB groove; as shown in fig. 14a and 14b, fig. 14a is a schematic view showing a cross-sectional structure after forming an epitaxial structure according to the present invention; fig. 14b is a schematic view of a longitudinal cross-sectional structure of the epitaxial structure formed in the present invention. Forming a SiP epitaxial structure 14 on the Fin structure between the two adjacent dummy gates on one side of the SDB groove in the step twelve; a SiGe epitaxial structure 15 is formed on the Fin structure between the adjacent two dummy gates on the other side of the SDB recess.
In the step twelve of the present embodiment, the number of the SiP epitaxial structures formed on the Fin structure between the two adjacent dummy gates at one side of the SDB groove is two.
In the step twelve of the present embodiment, the number of SiGe epitaxial structures formed on the Fin structure between the two adjacent dummy gates on the other side of the SDB groove is two.
Thirteenth, depositing an interlayer dielectric layer to cover the dummy gates and filling the space between the dummy gates; grinding the interlayer dielectric layer until the top of the pseudo grid electrode is exposed; as shown in fig. 15a and 15b, fig. 15a is a schematic cross-sectional view of the present invention after an interlayer dielectric layer is deposited to cover the dummy gate; fig. 15b is a schematic view of a vertical cross-section of the deposited interlayer dielectric layer covering the dummy gate in the present invention. Depositing the interlayer dielectric layer 16 to cover the dummy gate 12 and fill the space between the dummy gates in thirteenth step; the interlayer dielectric layer 16 is then polished until the top of the dummy gate is exposed.
Fourteen, removing the pseudo grid electrode to form a groove; and filling HK metal in the grooves to form HK metal gates. As shown in fig. 16a and 16b, fig. 16a is a schematic view showing a lateral cross-sectional structure after forming HK metal gate in the present invention; fig. 16b is a schematic view showing a longitudinal sectional structure of the HK metal gate after formation in the present invention.
In summary, the oxide layer is filled at the bottom of the SDB groove by using the FCVD method, so that the filling capacity is good; filling SiC at the top of the SDB groove can avoid the problem of film loss caused by subsequent SiN layer removal; according to the invention, three thin film stacks are formed in the SDB groove, so that the pressure release risk of the SiP epitaxial layer and the SiGe epitaxial layer is reduced; since the SiP epitaxial layer and the SiGe epitaxial layer are separate, the stress released by the HK metal gate does not affect the SiP epitaxial layer and the SiGe epitaxial layer. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (10)
1. A method of manufacturing a cut-first SDB FinFET, comprising at least:
Providing a substrate, and forming a plurality of Fin structures which are arranged at intervals along the longitudinal direction on the substrate, wherein the length direction of the Fin structures is a transverse direction perpendicular to the longitudinal direction; a SiN layer is formed on the Fin structure; a first hard mask layer is formed on the SiN layer;
Depositing a thin oxide layer, wherein the thin oxide layer covers the upper surface of the substrate and the Fin structure;
Depositing a dielectric layer on the substrate to cover the upper surface of the substrate and the thin oxide layer, and then annealing;
grinding the dielectric layer and the thin oxide layer until the upper surface of the SiN layer is exposed;
Fifthly, forming an SDB photoresist pattern on the SiN layer of the Fin structure;
step six, etching the SiN layer and the Fin structure along the SDB photoresist pattern to form an SDB groove;
step seven, forming an oxide layer at the bottom of the SDB groove;
step eight, forming SiN on the middle part of the SDB groove and the oxide layer;
Step nine, forming SiC on the SiN at the top of the SDB groove;
Removing the SiN layer to expose the upper surface of the Fin structure and expose the SiC; the upper surface of the SiC is flush with the upper surface of the SiN layer, the SiN layer on the Fin structure in the first step is removed to expose the upper surface of the Fin structure, and SiN in the SDB groove is not exposed at the same time of exposing the SiC;
Eleventh, forming a plurality of dummy grids and side walls attached to the dummy grids along the transverse interval on the Fin structure and the SDB groove;
twelve, forming a SiP epitaxial structure on the Fin structure between two adjacent dummy gates at one side of the SDB groove; forming a SiGe epitaxial structure on the Fin structure between the two adjacent dummy gates at the other side of the SDB groove;
thirteenth, depositing an interlayer dielectric layer to cover the dummy gates and filling the space between the dummy gates; grinding the interlayer dielectric layer until the top of the pseudo grid electrode is exposed;
Fourteen, removing the pseudo grid electrode to form a groove; and filling HK metal in the grooves to form HK metal gates.
2. The method of manufacturing a cut-first SDB FinFET of claim 1, wherein: and in the second step, the thin oxide layer deposited on the upper surface of the substrate and the side wall of the Fin structure is formed by an atomic layer deposition method or an in-situ water vapor generation method.
3. The method of manufacturing a cut-first SDB FinFET of claim 1, wherein: and in the third step, the method for depositing the dielectric layer is FCVD.
4. The method of manufacturing a cut-first SDB FinFET of claim 1, wherein: the polishing in the fourth step is chemical mechanical polishing.
5. The method of manufacturing a cut-first SDB FinFET of claim 1, wherein: in the seventh step, the method for forming the oxide layer in the SDB groove includes: and depositing a layer of oxide on the SDB groove, and then carrying out back etching to form the oxide layer at the bottom of the SDB groove.
6. The method of manufacturing a cut-first SDB FinFET of claim 1, wherein: in the eighth step, the method for forming SiN in the middle of the SDB groove includes: and depositing a layer of SiN in the SDB groove, and then etching back to form SiN in the middle of the SDB groove and on the oxide layer.
7. The method of manufacturing a cut-first SDB FinFET of claim 1, wherein: the method for forming SiC at the top of the SDB groove in the step nine comprises the following steps: and depositing a layer of SiC on the SiN in the SDB groove, then forming back etching and grinding, and forming SiC with the upper surface flush with the upper surface of the SiN layer on the SiN of the SDB groove.
8. The method of manufacturing a cut-first SDB FinFET of claim 1, wherein: in the eleventh step, the dummy gate includes a polysilicon layer and a second hard mask layer on the polysilicon layer.
9. The method of manufacturing a cut-first SDB FinFET of claim 1, wherein: in the step twelve, the number of the SiP epitaxial structures formed on the Fin structure between the two adjacent dummy gates at one side of the SDB groove is two.
10. The method of manufacturing a cut-first SDB FinFET of claim 1, wherein: and in the step twelve, the number of the SiGe epitaxial structures formed on the Fin structure between the two adjacent dummy gates at the other side of the SDB groove is two.
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| CN101123204A (en) * | 2006-08-10 | 2008-02-13 | 中芯国际集成电路制造(上海)有限公司 | Method for forming shallow groove separation structure and shallow groove separation structure |
| CN108122762A (en) * | 2016-11-30 | 2018-06-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| US10192746B1 (en) * | 2017-07-31 | 2019-01-29 | Globalfoundries Inc. | STI inner spacer to mitigate SDB loading |
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| CN103579004B (en) * | 2012-08-10 | 2016-05-11 | 中国科学院微电子研究所 | FinFET and manufacture method thereof |
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| CN101123204A (en) * | 2006-08-10 | 2008-02-13 | 中芯国际集成电路制造(上海)有限公司 | Method for forming shallow groove separation structure and shallow groove separation structure |
| CN108122762A (en) * | 2016-11-30 | 2018-06-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| US10192746B1 (en) * | 2017-07-31 | 2019-01-29 | Globalfoundries Inc. | STI inner spacer to mitigate SDB loading |
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