CN113782435A - Manufacturing method of first-cut SDB FinFET - Google Patents
Manufacturing method of first-cut SDB FinFET Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 239000010410 layer Substances 0.000 claims abstract description 163
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 238000000151 deposition Methods 0.000 claims abstract description 29
- 229910052751 metal Inorganic materials 0.000 claims abstract description 19
- 239000002184 metal Substances 0.000 claims abstract description 19
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 17
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 13
- 238000000227 grinding Methods 0.000 claims abstract description 12
- 239000011229 interlayer Substances 0.000 claims abstract description 11
- 238000000137 annealing Methods 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 36
- 238000005498 polishing Methods 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 238000000231 atomic layer deposition Methods 0.000 claims description 3
- 238000011065 in-situ storage Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 45
- 230000008569 process Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
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Abstract
The invention provides a manufacturing method of an SDB FinFET, which comprises the steps of forming a plurality of Fin structures which are arranged at intervals along the longitudinal direction on a substrate, wherein an SiN layer is formed on the Fin structures; depositing a thin oxide layer; annealing after depositing the dielectric layer; grinding and exposing the upper surface of the SiN layer; forming an SDB photoresist pattern on the SiN layer; etching the SiN layer and the Fin structure along the SDB photoresist pattern to form an SDB groove; forming an oxide layer at the bottom of the SDB groove; forming SiN in the middle of the SDB groove; forming SiC on the top of the SDB groove; removing the SiN layer to expose the upper surface of the Fin structure and expose the SiC; forming a plurality of dummy gates arranged at intervals along the transverse direction on the Fin structure and the SDB groove; forming a SiP epitaxial structure on the Fin structure between two adjacent pseudo gates on one side of the SDB groove; forming a SiGe epitaxial structure on the Fin structure between two adjacent dummy gates on the other side of the SDB groove; depositing an interlayer dielectric layer to cover the dummy gate; grinding the interlayer dielectric layer until the top of the pseudo grid is exposed; removing the pseudo grid to form a groove; forming the HK metal gate.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a cut-first SDB FinFET.
Background
The logic design in the logic standard cell is created using the standard cell. The height of the cell is the number of tracks times the metal Pitch (Pitch), which is measured with metal layer 2 (M2). Fig. 1 shows a schematic diagram of a 7.5 track cell with Power (Power) and half the height of the Ground (Ground) located in the upper and lower cells, respectively.
The cell width is related to the poly contact pitch (CPP), and the number of CPPs constituting the cell width depends on the cell type and whether the cell has a Double Diffusion Break (DDB) or a Single Diffusion Break (SDB).
One DDB adds one half-CPP per side of the cell. For practical cells, such as NAND gates and cell scan flip-flops, the number of CPPs across the width of the cell is large and SDB has less impact on DDB.
In the cut-first SDB process, after ILD fill is formed and planarized, the dummy gate will be removed and then the HK metal gate stack is filled, which will present two problems: 1) around the SDB, the spacing between the epitaxial layer and the polysilicon is very small, and the interaction between the two is also very strong; 2) after the dummy gate is removed, the SiGe or SiP stress is relaxed, which will degrade the device performance; 3) after the HK metal gate stack fills the recess, the metal gate and tungsten electrode pressures will react to the SiGe or SiP pressures, which will be beneficial for PMOS or NMOS, but will degrade the performance of the other; 4) in view of the above, the SDB device may vary greatly in actual circuits according to actual situations.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, it is an object of the present invention to provide a method for manufacturing a cut-first SDB FinFET, which is used to solve the problem that the performance of the device is degraded due to the reaction of the metal gate and tungsten electrode pressure on the SiGe or SiP pressure in the SDB cut-first process in the prior art.
To achieve the above and other related objects, the present invention provides a method for manufacturing a cut-first SDB FinFET, comprising:
providing a substrate, and forming a plurality of Fin structures which are arranged at intervals along the longitudinal direction on the substrate, wherein the length direction of the Fin structures is the transverse direction which is vertical to the longitudinal direction; a SiN layer is formed on the Fin structure; a first hard mask layer is formed on the SiN layer;
depositing a thin oxide layer, wherein the thin oxide layer covers the upper surface of the substrate and the Fin structure;
depositing a dielectric layer on the substrate to cover the upper surface of the substrate and the thin oxide layer, and then annealing;
grinding the dielectric layer and the thin oxide layer until the upper surface of the SiN layer is exposed;
fifthly, forming an SDB photoresist pattern on the SiN layer of the Fin structure;
sixthly, etching the SiN layer and the Fin structure along the SDB photoresist pattern to form an SDB groove;
seventhly, forming an oxide layer at the bottom of the SDB groove;
step eight, forming SiN on the oxidation layer and the middle part of the SDB groove;
step nine, forming SiC on the top of the SDB groove and the SiN;
step ten, removing the SiN layer to expose the upper surface of the Fin structure and expose the SiC;
step eleven, forming a plurality of dummy gates arranged at intervals along the transverse direction and side walls attached to the dummy gates on the Fin structure and the SDB groove;
step twelve, forming a SiP epitaxial structure on the Fin structure between the two adjacent dummy gates on one side of the SDB groove; forming a SiGe epitaxial structure on the Fin structure between the two adjacent dummy gates on the other side of the SDB groove;
thirteen, depositing an interlayer dielectric layer to cover the dummy gates and fill the spaces between the dummy gates; grinding the interlayer dielectric layer until the top of the pseudo grid is exposed;
fourteen, removing the pseudo grid to form a groove; and then filling HK metal in the grooves to form HK metal gates.
Preferably, the method for depositing the thin oxide layer on the upper surface of the substrate and the sidewall of the Fin structure in the second step is an atomic layer deposition method or an in-situ water vapor generation method.
Preferably, the method for depositing the dielectric layer in the third step is an FCVD method.
Preferably, the polishing in step four is chemical mechanical polishing.
Preferably, the method for forming the oxide layer in the SDB groove in the seventh step includes: and depositing a layer of oxide in the SDB groove, and then carrying out back etching to form the oxide layer at the bottom of the SDB groove.
Preferably, the method for forming SiN in the middle of the SDB groove in the eighth step is: and firstly depositing a layer of SiN in the SDB groove, and then etching back, and forming SiN on the middle part of the SDB groove and the oxide layer.
Preferably, the method for forming SiC on the top of the SDB groove in the ninth step is: and depositing a layer of SiC on the SiN in the SDB groove, then forming etching back and grinding, and forming SiC with the upper surface flush with the upper surface of the SiN layer on the SiN of the SDB groove.
Preferably, in the eleventh step, the dummy gate includes a polysilicon layer and a second hard mask layer located on the polysilicon layer.
Preferably, the number of the SiP epitaxial structures formed on the Fin structure between the two adjacent dummy gates at one side of the SDB recess in the twelfth step is two.
Preferably, in the twelfth step, the number of the SiGe epitaxial structures formed on the Fin structure between the two adjacent dummy gates on the other side of the SDB recess is two.
As described above, the method for manufacturing the pre-cut SDB FinFET of the present invention has the following advantages: according to the invention, the oxidation layer is filled at the bottom of the SDB groove by using an FCVD (plasma chemical vapor deposition) method, so that the filling capacity is good; SiC is filled at the top of the SDB groove, so that the problem of film loss caused by removing the SiN layer in the subsequent process can be avoided; three layers of film lamination are formed in the SDB groove, so that the pressure release risk of the SiP epitaxial layer and the SiGe epitaxial layer is reduced; since the SiP epitaxial layer and the SiGe epitaxial layer are independently separated, the stress released by the HK metal gate does not affect the SiP epitaxial layer and the SiGe epitaxial layer.
Drawings
FIG. 1 shows a schematic view of a 7.5 track unit;
FIG. 2a is a schematic cross-sectional view of a substrate with a Fin structure formed thereon according to the present invention;
FIG. 2b is a schematic longitudinal cross-sectional view of a Fin structure formed on a substrate according to the present invention;
FIG. 3a is a schematic cross-sectional view of a thin oxide layer formed on a substrate according to the present invention;
FIG. 3b is a schematic longitudinal cross-sectional view of the thin oxide layer formed on the substrate according to the present invention;
FIG. 4a is a schematic cross-sectional view of a dielectric layer formed on a substrate according to the present invention;
FIG. 4b is a schematic diagram showing a longitudinal cross-sectional structure of the present invention after a dielectric layer is formed on a substrate;
FIG. 5a is a schematic cross-sectional view of a polished exposed SiN layer according to the present invention;
FIG. 5b is a schematic diagram showing a longitudinal cross-sectional structure of an exposed SiN layer after polishing in accordance with the present invention;
FIG. 6a is a schematic diagram showing a lateral cross-sectional structure of the SDB photoresist pattern formed in the present invention;
6b is a schematic diagram showing the longitudinal section structure after the SDB photoresist pattern is formed in the invention;
FIG. 7a is a schematic diagram of a cross-sectional view of the SDB groove after forming the SDB groove in accordance with the present invention;
FIG. 7b is a schematic diagram showing a longitudinal cross-sectional structure of the SDB groove formed in the present invention;
FIG. 8a is a schematic diagram showing a lateral cross-sectional structure of the SDB trench after an oxide layer is formed thereon;
FIG. 8b is a schematic diagram showing a longitudinal cross-sectional structure of the SDB trench after an oxide layer is formed thereon;
FIG. 9a is a schematic diagram showing a lateral cross-sectional structure of the SDB after SiN is formed in the middle of the SDB groove according to the present invention;
FIG. 9b is a schematic diagram showing a longitudinal cross-sectional structure of the SDB after SiN is formed in the middle of the SDB groove according to the present invention;
FIG. 10a is a schematic diagram showing a lateral cross-section of SiC formed on top of an SDB recess in accordance with the present invention;
FIG. 10b shows a schematic longitudinal cross-sectional view of SiC formation on top of an SDB groove in the present invention;
FIG. 11a is a schematic diagram showing a lateral cross-sectional structure of the present invention after removing the SiN layer to expose the upper surface of the Fin structure and the SiC;
FIG. 11b is a schematic diagram showing a longitudinal cross-sectional structure of the present invention after removing the SiN layer to expose the upper surface of the Fin structure and the SiC;
FIG. 12a is a schematic diagram showing a lateral cross-sectional structure of the present invention after removing the oxide between the Fin structure and the SiN layer;
FIG. 12b is a schematic diagram showing a longitudinal cross-sectional structure of the present invention after removing the oxide between the Fin structure and the SiN layer;
FIG. 13a is a schematic diagram showing a lateral cross-sectional structure after forming a dummy gate according to the present invention;
FIG. 13b is a schematic diagram showing a longitudinal cross-sectional structure of the dummy gate of the present invention after forming the dummy gate;
FIG. 14a is a schematic diagram illustrating a lateral cross-sectional structure of the present invention after an epitaxial structure is formed;
FIG. 14b is a schematic longitudinal cross-sectional view of an epitaxial structure of the present invention after formation;
FIG. 15a is a schematic cross-sectional view of a dummy gate overlying a deposited interlevel dielectric layer in accordance with the present invention;
FIG. 15b is a schematic longitudinal cross-sectional view of a dummy gate covered by an interlevel dielectric layer deposited in accordance with the present invention;
FIG. 16a is a schematic diagram showing a lateral cross-sectional structure after forming a HK metal gate in accordance with the present invention;
FIG. 16b is a schematic diagram showing a longitudinal cross-sectional structure after forming the HK metal gate in the present invention;
fig. 17 is a flow chart of a method of manufacturing a cut-first SDB FinFET in accordance with the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 2 to 17. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
The present invention provides a method for manufacturing a cut-first SDB FinFET, as shown in fig. 17, where fig. 17 is a flowchart of a method for manufacturing a cut-first SDB FinFET of the present invention, the method at least includes the following steps:
providing a substrate, and forming a plurality of Fin structures which are arranged at intervals along the longitudinal direction on the substrate, wherein the length direction of the Fin structures is the transverse direction which is vertical to the longitudinal direction; a SiN layer is formed on the Fin structure; a first hard mask layer is formed on the SiN layer; as shown in fig. 2a and 2b, fig. 2a is a schematic lateral cross-sectional view illustrating a Fin structure formed on a substrate according to the present invention; FIG. 2b is a schematic longitudinal cross-sectional view of a Fin structure formed on a substrate according to the present invention; in the first step, a plurality of Fin structures 02 arranged at intervals along a longitudinal direction are formed on the substrate 01, and the length direction of the Fin structures 02 is a transverse direction perpendicular to the longitudinal direction; a SiN layer 03 is formed on the Fin structure 02; a first hard mask layer 04 is formed on the SiN layer 03.
Depositing a thin oxide layer, wherein the thin oxide layer covers the upper surface of the substrate and the Fin structure; as shown in fig. 3a and 3b, fig. 3a is a schematic cross-sectional view of a thin oxide layer formed on a substrate according to the present invention; FIG. 3b is a schematic longitudinal cross-sectional view of the thin oxide layer formed on the substrate according to the present invention; and depositing the thin oxide layer 05, wherein the thin oxide layer 05 covers the upper surface of the substrate 01 and the Fin structure 02.
Further, in the second step of this embodiment, the method for depositing the thin oxide layer 05 on the upper surface of the substrate 01 and the sidewall of the Fin structure 02 is an atomic layer deposition method or an in-situ steam generation method.
Depositing a dielectric layer on the substrate to cover the upper surface of the substrate and the thin oxide layer, and then annealing; as shown in fig. 4a and 4b, fig. 4a is a schematic diagram illustrating a lateral cross-sectional structure of the present invention after a dielectric layer is formed on a substrate; FIG. 4b is a schematic diagram of a longitudinal cross-sectional structure of the present invention after forming a dielectric layer on a substrate. In the third step, a dielectric layer 06 is deposited on the substrate 01 to cover the upper surface of the substrate 01 and the thin oxide layer 05, and then annealing is carried out.
Further, the method for depositing the dielectric layer 06 in step three of this embodiment is an FCVD method.
Grinding the dielectric layer and the thin oxide layer until the upper surface of the SiN layer is exposed; as shown in FIGS. 5a and 5b, FIG. 5a is a schematic diagram illustrating a lateral cross-sectional structure of the SiN layer exposed after polishing in the present invention;
FIG. 5b is a schematic diagram showing a longitudinal cross-sectional structure of an exposed SiN layer after polishing in the present invention. In the fourth step, the dielectric layer 06 and the thin oxide layer 05 are polished until the upper surface of the SiN layer 03 is exposed.
Further, the polishing in step four of this embodiment is a chemical mechanical polishing.
Fifthly, forming an SDB photoresist pattern on the SiN layer of the Fin structure; as shown in fig. 6a and 6b, fig. 6a is a schematic diagram showing a lateral cross-sectional structure after forming an SDB photoresist pattern according to the present invention; and 6b is a schematic diagram showing the longitudinal cross-sectional structure of the SDB photoresist pattern formed in the present invention. In this step five, an SDB photoresist pattern 07 is formed on the SiN layer 03 of the Fin structure 02.
Sixthly, etching the SiN layer and the Fin structure along the SDB photoresist pattern to form an SDB groove; as shown in fig. 7a and 7b, fig. 7a is a schematic diagram illustrating a transverse cross-sectional structure after forming the SDB groove in the present invention; fig. 7b is a schematic diagram showing the longitudinal cross-sectional structure of the SDB groove formed in the present invention. In the sixth step, the SiN layer 03 and the Fin structure 02 are etched along the SDB photoresist pattern 07 to form an SDB groove 08.
Seventhly, forming an oxide layer at the bottom of the SDB groove; as shown in fig. 8a and 8b, fig. 8a is a schematic diagram illustrating a lateral cross-sectional structure of the SDB after an oxide layer is formed in the SDB recess according to the present invention; FIG. 8b is a schematic diagram showing the longitudinal cross-sectional structure of the SDB after an oxide layer is formed in the SDB groove. In this seventh step, the oxide layer 09 is formed at the bottom of the SDB recess 08.
Further, in step seven of this embodiment, the method for forming the oxide layer in the SDB recess includes: and depositing a layer of oxide in the SDB groove, and then carrying out back etching to form the oxide layer at the bottom of the SDB groove.
Step eight, forming SiN on the oxidation layer and the middle part of the SDB groove; as shown in fig. 9a and 9b, fig. 9a is a schematic diagram showing a lateral cross-sectional structure of the SDB after SiN is formed in the middle of the SDB recess according to the present invention; FIG. 9b is a schematic diagram showing the longitudinal cross-sectional structure of the SDB after SiN is formed in the middle of the SDB groove according to the present invention. In the eighth step, SiN (10) is formed on the oxide layer 09 and in the middle of the SDB groove.
Further, in the eighth step of this embodiment, the method for forming SiN in the middle of the SDB groove includes: and firstly depositing a layer of SiN in the SDB groove, and then etching back, and forming SiN on the middle part of the SDB groove and the oxide layer.
Step nine, forming SiC on the top of the SDB groove and the SiN; as shown in fig. 10a and 10b, fig. 10a is a schematic diagram showing a lateral cross-section of SiC formed on top of an SDB recess in the present invention; fig. 10b shows a schematic longitudinal cross-section of SiC formed on top of SDB recess in accordance with the present invention. In this ninth step SiC (11) is formed on top of the SDB recess, on the SiN (10).
Further, in the ninth step of this embodiment, the method for forming SiC on the top of the SDB groove includes: and depositing a layer of SiC on the SiN in the SDB groove, then forming etching back and grinding, and forming SiC with the upper surface flush with the upper surface of the SiN layer on the SiN of the SDB groove.
Step ten, removing the SiN layer to expose the upper surface of the Fin structure and expose the SiC; as shown in fig. 11a and 11b, fig. 11a is a schematic diagram showing a lateral cross-sectional structure of the present invention after the SiN layer is removed to expose the upper surface of the Fin structure and SiC; FIG. 11b is a schematic diagram showing the longitudinal cross-sectional structure of the present invention after removing the SiN layer to expose the upper surface of the Fin structure and the SiC. In this embodiment, a layer of oxide is further present between the upper surface of the Fin structure and the SiN layer, as shown in fig. 12a and 12b, fig. 12a is a schematic diagram showing a lateral cross-sectional structure of the present invention after the oxide between the Fin structure and the SiN layer is removed; FIG. 12b is a schematic diagram showing a longitudinal cross-sectional structure of the present invention after removing the oxide between the Fin structure and the SiN layer.
Step eleven, forming a plurality of dummy gates arranged at intervals along the transverse direction and side walls attached to the dummy gates on the Fin structure and the SDB groove; as shown in fig. 13a and 13b, fig. 13a is a schematic diagram illustrating a lateral cross-sectional structure after forming a dummy gate according to the present invention; FIG. 13b is a schematic diagram showing a vertical cross-sectional structure of the dummy gate of the present invention after forming the dummy gate. In the eleventh step, a plurality of dummy gates 12 arranged at intervals in the lateral direction and sidewalls 13 attached to the dummy gates 12 are formed on the Fin structure 02 and the SDB recess.
Further, in the eleventh step of this embodiment, the dummy gate 12 includes a polysilicon layer and a second hard mask layer located on the polysilicon layer.
Step twelve, forming a SiP epitaxial structure on the Fin structure between the two adjacent dummy gates on one side of the SDB groove; forming a SiGe epitaxial structure on the Fin structure between the two adjacent dummy gates on the other side of the SDB groove; as shown in fig. 14a and 14b, fig. 14a is a schematic diagram illustrating a lateral cross-sectional structure after an epitaxial structure is formed in the present invention; fig. 14b is a schematic longitudinal cross-sectional view of the epitaxial structure of the present invention. A step twelve of forming a SiP epitaxial structure 14 on the Fin structure between the two adjacent dummy gates on one side of the SDB groove; and forming a SiGe epitaxial structure 15 on the Fin structure between the two adjacent dummy gates on the other side of the SDB groove.
Further, in the twelfth step of this embodiment, the number of the SiP epitaxial structures formed on the Fin structure between the two adjacent dummy gates on one side of the SDB recess is two.
Furthermore, in the twelfth step of this embodiment, the number of the SiGe epitaxial structures formed on the Fin structure between the two adjacent dummy gates on the other side of the SDB recess is two.
Thirteen, depositing an interlayer dielectric layer to cover the dummy gates and fill the spaces between the dummy gates; grinding the interlayer dielectric layer until the top of the pseudo grid is exposed; as shown in fig. 15a and 15b, fig. 15a is a schematic diagram illustrating a lateral cross-sectional structure of the present invention after an interlayer dielectric layer is deposited to cover a dummy gate; FIG. 15b is a schematic diagram showing a longitudinal cross-sectional structure of the present invention after an interlevel dielectric layer is deposited to cover the dummy gate. Depositing the interlayer dielectric layer 16 to cover the dummy gates 12 and fill the spaces between the dummy gates in the thirteenth step; and then grinding the interlayer dielectric layer 16 until the top of the dummy gate is exposed.
Fourteen, removing the pseudo grid to form a groove; and then filling HK metal in the grooves to form HK metal gates. As shown in fig. 16a and 16b, fig. 16a is a schematic diagram showing a lateral cross-sectional structure after forming the HK metal gate in the present invention; fig. 16b is a schematic diagram showing a longitudinal cross-sectional structure after forming the HK metal gate in accordance with the present invention.
In conclusion, the oxidation layer is filled at the bottom of the SDB groove by the FCVD method, so that the filling capacity is good; SiC is filled at the top of the SDB groove, so that the problem of film loss caused by removing the SiN layer in the subsequent process can be avoided; three layers of film lamination are formed in the SDB groove, so that the pressure release risk of the SiP epitaxial layer and the SiGe epitaxial layer is reduced; since the SiP epitaxial layer and the SiGe epitaxial layer are independently separated, the stress released by the HK metal gate does not affect the SiP epitaxial layer and the SiGe epitaxial layer. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. A method of manufacturing a cut-first SDB FinFET, comprising:
providing a substrate, and forming a plurality of Fin structures which are arranged at intervals along the longitudinal direction on the substrate, wherein the length direction of the Fin structures is the transverse direction which is vertical to the longitudinal direction; a SiN layer is formed on the Fin structure; a first hard mask layer is formed on the SiN layer;
depositing a thin oxide layer, wherein the thin oxide layer covers the upper surface of the substrate and the Fin structure;
depositing a dielectric layer on the substrate to cover the upper surface of the substrate and the thin oxide layer, and then annealing;
grinding the dielectric layer and the thin oxide layer until the upper surface of the SiN layer is exposed;
fifthly, forming an SDB photoresist pattern on the SiN layer of the Fin structure;
sixthly, etching the SiN layer and the Fin structure along the SDB photoresist pattern to form an SDB groove;
seventhly, forming an oxide layer at the bottom of the SDB groove;
step eight, forming SiN on the oxidation layer and the middle part of the SDB groove;
step nine, forming SiC on the top of the SDB groove and the SiN;
step ten, removing the SiN layer to expose the upper surface of the Fin structure and expose the SiC;
step eleven, forming a plurality of dummy gates arranged at intervals along the transverse direction and side walls attached to the dummy gates on the Fin structure and the SDB groove;
step twelve, forming a SiP epitaxial structure on the Fin structure between the two adjacent dummy gates on one side of the SDB groove; forming a SiGe epitaxial structure on the Fin structure between the two adjacent dummy gates on the other side of the SDB groove;
thirteen, depositing an interlayer dielectric layer to cover the dummy gates and fill the spaces between the dummy gates; grinding the interlayer dielectric layer until the top of the pseudo grid is exposed;
fourteen, removing the pseudo grid to form a groove; and then filling HK metal in the grooves to form HK metal gates.
2. The method of manufacturing a pre-cut SDB FinFET of claim 1, wherein: and in the second step, the method for depositing the thin oxide layer on the upper surface of the substrate and the side wall of the Fin structure is an atomic layer deposition method or an in-situ water vapor generation method.
3. The method of manufacturing a pre-cut SDB FinFET of claim 1, wherein: the method for depositing the dielectric layer in the third step is an FCVD method.
4. The method of manufacturing a pre-cut SDB FinFET of claim 1, wherein: the polishing in the fourth step is chemical mechanical polishing.
5. The method of manufacturing a pre-cut SDB FinFET of claim 1, wherein: in the seventh step, the method for forming the oxide layer in the SDB groove comprises the following steps: and depositing a layer of oxide in the SDB groove, and then carrying out back etching to form the oxide layer at the bottom of the SDB groove.
6. The method of manufacturing a pre-cut SDB FinFET of claim 1, wherein: in the eighth step, the method for forming SiN in the middle of the SDB groove comprises the following steps: and firstly depositing a layer of SiN in the SDB groove, and then etching back, and forming SiN on the middle part of the SDB groove and the oxide layer.
7. The method of manufacturing a pre-cut SDB FinFET of claim 1, wherein: the method for forming SiC on the top of the SDB groove in the ninth step comprises the following steps: and depositing a layer of SiC on the SiN in the SDB groove, then forming etching back and grinding, and forming SiC with the upper surface flush with the upper surface of the SiN layer on the SiN of the SDB groove.
8. The method of manufacturing a pre-cut SDB FinFET of claim 1, wherein: and eleventh, the dummy gate comprises a polysilicon layer and a second hard mask layer positioned on the polysilicon layer.
9. The method of manufacturing a pre-cut SDB FinFET of claim 1, wherein: and step twelve, the number of the SiP epitaxial structures formed on the Fin structure between the two adjacent dummy gates on one side of the SDB groove is two.
10. The method of manufacturing a pre-cut SDB FinFET of claim 1, wherein: and step twelve, the number of the SiGe epitaxial structures formed on the Fin structure between the two adjacent dummy gates on the other side of the SDB groove is two.
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| CN101123204A (en) * | 2006-08-10 | 2008-02-13 | 中芯国际集成电路制造(上海)有限公司 | Method for forming shallow groove separation structure and shallow groove separation structure |
| US20150221769A1 (en) * | 2012-08-10 | 2015-08-06 | Institute of Microelectronics, Chinese Academy of Sciences | Finfet and method for manufacturing the same |
| CN108122762A (en) * | 2016-11-30 | 2018-06-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| US10192746B1 (en) * | 2017-07-31 | 2019-01-29 | Globalfoundries Inc. | STI inner spacer to mitigate SDB loading |
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| CN101123204A (en) * | 2006-08-10 | 2008-02-13 | 中芯国际集成电路制造(上海)有限公司 | Method for forming shallow groove separation structure and shallow groove separation structure |
| US20150221769A1 (en) * | 2012-08-10 | 2015-08-06 | Institute of Microelectronics, Chinese Academy of Sciences | Finfet and method for manufacturing the same |
| CN108122762A (en) * | 2016-11-30 | 2018-06-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| US10192746B1 (en) * | 2017-07-31 | 2019-01-29 | Globalfoundries Inc. | STI inner spacer to mitigate SDB loading |
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