CN113394109A - Manufacturing method of first-cut SDB FinFET - Google Patents
Manufacturing method of first-cut SDB FinFET Download PDFInfo
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- CN113394109A CN113394109A CN202110597511.6A CN202110597511A CN113394109A CN 113394109 A CN113394109 A CN 113394109A CN 202110597511 A CN202110597511 A CN 202110597511A CN 113394109 A CN113394109 A CN 113394109A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 229910052751 metal Inorganic materials 0.000 claims abstract description 25
- 239000002184 metal Substances 0.000 claims abstract description 25
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 16
- 238000000151 deposition Methods 0.000 claims abstract description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 15
- 229920005591 polysilicon Polymers 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 10
- 239000010410 layer Substances 0.000 claims description 117
- 239000000758 substrate Substances 0.000 claims description 24
- 238000000034 method Methods 0.000 claims description 23
- 229920002120 photoresistant polymer Polymers 0.000 claims description 11
- 239000011229 interlayer Substances 0.000 claims description 10
- 238000000227 grinding Methods 0.000 claims description 7
- 238000000137 annealing Methods 0.000 claims description 3
- 238000000231 atomic layer deposition Methods 0.000 claims description 3
- 238000011065 in-situ storage Methods 0.000 claims description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 16
- 230000008569 process Effects 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a manufacturing method of an SDB FinFET, which comprises the steps of forming a plurality of Fin structures which are arranged at intervals along the longitudinal direction, and etching the Fin structures to form an SDB groove; depositing a dielectric layer to fill the SDB groove; etching to expose the upper end of the Fin structure and a part of the upper end of the SDB groove; forming a plurality of pseudo gates arranged at intervals along the transverse direction and side walls of the pseudo gates on the Fin structure and the SDB groove; respectively forming a SiP epitaxial structure and a SiGe epitaxial structure on the Fin structure between two adjacent pseudo gates at two sides of the SDB groove; removing the dummy gates except the dummy gates on the SDB grooves to form grooves; and filling the HK metal in the grooves of the removed dummy gates to form HK metal gates. The invention reserves the polysilicon of SDB, and reduces the pressure release risk of SiP epitaxial layer and SiGe epitaxial layer; the HK metal gate is not filled in the SDB recess, so that the stress of the HKK metal layer will not interact with the stress of the epitaxial layer, and device performance is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a cut-first SDB FinFET.
Background
The logic design in the logic standard cell is created using the standard cell. The height of the cell is the number of tracks times the metal Pitch (Pitch), which is measured with metal layer 2 (M2). Fig. 1 shows a schematic diagram of a 7.5 track cell with Power (Power) and half the height of the Ground (Ground) located in the upper and lower cells, respectively.
The cell width is related to the poly contact pitch (CPP), and the number of CPPs constituting the cell width depends on the cell type and whether the cell has a Double Diffusion Break (DDB) or a Single Diffusion Break (SDB).
One DDB adds one half-CPP per side of the cell. For practical cells, such as NAND gates and cell scan flip-flops, the number of CPPs across the width of the cell is large and SDB has less impact on DDB.
In the cut-first SDB process, after ILD fill is formed and planarized, the dummy gate will be removed and then the HK metal gate stack is filled, which will present two problems: 1) around the SDB, the spacing between the epitaxial layer and the polysilicon is very small, and the interaction between the two is also very strong; 2) after the dummy gate is removed, the SiGe or SiP stress is relaxed, which will degrade the device performance; 3) after the HK metal gate stack fills the recess, the metal gate and tungsten electrode pressures will react to the SiGe or SiP pressures, which will be beneficial for PMOS or NMOS, but will degrade the performance of the other; 4) in view of the above, the SDB device may vary greatly in actual circuits according to actual situations.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, it is an object of the present invention to provide a method for manufacturing a cut-first SDB FinFET, which is used to solve the problem that the performance of the device is degraded due to the reaction of the metal gate and tungsten electrode pressure on the SiGe or SiP pressure in the SDB cut-first process in the prior art.
To achieve the above and other related objects, the present invention provides a method for manufacturing a cut-first SDB FinFET, comprising:
providing a substrate, and forming a plurality of Fin structures which are arranged at intervals along the longitudinal direction on the substrate, wherein the length direction of the Fin structures is the transverse direction which is vertical to the longitudinal direction; then forming a SiN layer on the Fin structure; then forming a first hard mask layer on the SiN layer;
depositing a thin oxide layer, wherein the thin oxide layer covers the upper surface of the substrate and the side wall of the Fin structure;
step three, forming an SDB photoresist pattern on the first hard mask layer of the Fin structure;
etching the first hard mask layer, the SiN layer and the Fin structure along the SDB photoresist pattern to form an SDB groove;
depositing a dielectric layer on the substrate to cover the upper surface of the substrate and the thin oxide layer, filling the SDB groove, and then annealing;
step six, grinding the dielectric layer and the thin oxide layer until the upper surface of the SiN layer is exposed;
seventhly, removing the SiN layer;
step eight, etching the dielectric layer until part of the upper end of the Fin structure is exposed, and simultaneously exposing part of the upper end of the SDB groove;
step nine, forming a gate oxide layer on the surfaces of the exposed Fin structure and the SDB groove;
step ten, forming a plurality of dummy gates arranged at intervals along the transverse direction and side walls attached to the dummy gates on the Fin structure and the SDB groove;
eleven, forming a SiP epitaxial structure on the Fin structure between the two adjacent dummy gates on one side of the SDB groove; forming a SiGe epitaxial structure on the Fin structure between the two adjacent dummy gates on the other side of the SDB groove;
step twelve, depositing an interlayer dielectric layer to cover the dummy gates and fill spaces between the dummy gates; grinding the interlayer dielectric layer until the top of the pseudo grid is exposed;
thirteenth, removing the dummy gates except the dummy gates on the SDB groove to form a groove;
and step fourteen, filling HK metal in the grooves of the removed dummy gates to form HK metal gates.
Preferably, the method for depositing the thin oxide layer on the upper surface of the substrate and the sidewall of the Fin structure in the second step is an atomic layer deposition method or an in-situ water vapor generation method.
Preferably, the method for depositing the dielectric layer in the fifth step is an FCVD method.
Preferably, in the tenth step, the dummy gate includes a polysilicon layer and a second hard mask layer located on the polysilicon layer.
Preferably, in the eleventh step, the number of the SiP epitaxial structures formed on the Fin structure between the two adjacent dummy gates on one side of the SDB recess is two.
Preferably, in the eleventh step, the number of the SiGe epitaxial structures formed on the Fin structure between the two adjacent dummy gates on the other side of the SDB recess is two.
Preferably, the part of the dummy gate removed in the thirteenth step includes the polysilicon layer and the second hard mask layer, and the side wall is reserved.
As described above, the method for manufacturing the pre-cut SDB FinFET of the present invention has the following advantages: in the invention, in the process of removing the polysilicon in the pseudo grid, the polysilicon in the SDB area is reserved, so that the pressure release risk of the SiP epitaxial layer and the SiGe epitaxial layer is reduced; the HK metal gate is not filled in the SDB recess, so that the stress of the HKK metal layer will not interact with the stress of the epitaxial layer, and device performance is improved.
Drawings
FIG. 1 shows a schematic view of a 7.5 track unit;
FIG. 2 is a schematic view of Fin structure on a substrate according to the present invention;
FIG. 3 is a schematic diagram of a thin oxide layer deposited according to the present invention;
FIG. 4 is a schematic diagram of the structure of the Fin structure after the SDB photoresist pattern is formed thereon;
FIG. 5 is a schematic diagram of the Fin structure after forming the SDB groove thereon;
FIG. 6 is a schematic diagram of a structure after a dielectric layer is formed in the present invention;
FIG. 7 is a schematic diagram of the structure of the present invention after polishing the dielectric layer and the thin oxide layer;
FIG. 8 is a schematic view of the SiN layer removed structure according to the present invention;
FIG. 9 is a schematic structural view showing the upper end portion of the Fin structure exposed by etching the dielectric layer according to the present invention;
FIG. 10 is a schematic structural diagram of the Fin structure and the SDB groove after a gate oxide layer is formed on the surface;
FIG. 11 is a schematic diagram showing a structure of the dummy gate of the present invention after forming the dummy gate;
FIG. 12 is a schematic diagram of a SiP epitaxial structure and a SiGe epitaxial structure after forming the same in accordance with the present invention;
FIG. 13 is a schematic view of a structure after an interlayer dielectric layer is formed in the present invention;
FIG. 14 is a schematic view of the structure of the present invention after removing the dummy gate;
FIG. 15 is a schematic diagram of the structure of the HK metal gate of the present invention after forming the HK metal gate;
fig. 16 is a flow chart of a method of manufacturing a cut-first SDB FinFET in the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 2 to 16. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
The present invention provides a method for manufacturing a cut-first SDB FinFET, as shown in fig. 16, fig. 16 is a flowchart of a method for manufacturing a cut-first SDB FinFET in the present invention, and at least includes:
providing a substrate, and forming a plurality of Fin structures which are arranged at intervals along the longitudinal direction on the substrate, wherein the length direction of the Fin structures is the transverse direction which is vertical to the longitudinal direction; then forming a SiN layer on the Fin structure; then forming a first hard mask layer on the SiN layer; as shown in fig. 2, fig. 2 is a schematic diagram of a Fin structure on a substrate in the present invention, in this step, a plurality of Fin structures 02 arranged at intervals along a longitudinal direction are formed on the substrate 01, and a length direction of the Fin structures 02 is a transverse direction perpendicular to the longitudinal direction; the arrangement direction of the plurality of Fin structures is a direction perpendicular to the paper surface in fig. 2 (the longitudinal direction), and the longitudinal direction of the Fin structures is a left-right direction in fig. 2 (the lateral direction). The SiN layer 03 is formed on the Fin structure 02, and then the first hard mask layer 04 is formed on the SiN layer 03.
Depositing a thin oxide layer, wherein the thin oxide layer covers the upper surface of the substrate and the side wall of the Fin structure;
as shown in fig. 3, fig. 3 is a schematic structural view of the thin oxide layer deposited in the present invention. In the second step, the thin oxide layer 05 covers the upper surface of the substrate 01 and the sidewalls of the Fin structure 02. Further, the method for depositing the thin oxide layer on the upper surface of the substrate and the sidewall of the Fin structure in the second step of this embodiment is an atomic layer deposition method or an in-situ steam generation method.
Step three, forming an SDB photoresist pattern on the first hard mask layer of the Fin structure; as shown in fig. 4, fig. 4 is a schematic structural view after an SDB photoresist pattern is formed on a Fin structure according to the present invention. In the third step, a photoresist is spin-coated on the first hard mask layer 04 on the Fin structure 02, and then the SDB photoresist pattern 06 is formed through exposure and development.
Etching the first hard mask layer, the SiN layer and the Fin structure along the SDB photoresist pattern to form an SDB groove; as shown in fig. 5, fig. 5 is a schematic structural diagram of the Fin structure after forming the SDB groove thereon according to the present invention. In the fourth step, the first hard mask layer 04, the SiN layer 03 and the Fin structure 02 are etched along the SDB photoresist pattern to form the SDB groove 07.
Depositing a dielectric layer on the substrate to cover the upper surface of the substrate and the thin oxide layer, filling the SDB groove, and then annealing; as shown in fig. 6, fig. 6 is a schematic structural diagram after a dielectric layer is formed in the present invention. In the fifth step, the dielectric layer 08 is deposited on the substrate 01, the dielectric layer 08 covers the upper surface of the substrate 01 and the thin oxide layer, the SDB groove is filled, and then the whole structure is annealed.
Step six, grinding the dielectric layer and the thin oxide layer until the upper surface of the SiN layer is exposed; as shown in fig. 7, fig. 7 is a schematic structural diagram of the dielectric layer and the thin oxide layer after being polished according to the present invention. In the sixth step of this embodiment, a chemical mechanical polishing method is used to polish the thin oxide layer and the dielectric layer until the upper surface of the SiN layer 03 is exposed.
Seventhly, removing the SiN layer; as shown in FIG. 8, FIG. 8 is a schematic structural view of the SiN layer removed in the present invention.
Step eight, etching the dielectric layer until part of the upper end of the Fin structure is exposed, and simultaneously exposing part of the upper end of the SDB groove; as shown in fig. 9, fig. 9 is a schematic structural view illustrating that the upper end portion of the Fin structure is exposed by etching the dielectric layer according to the present invention. In the eighth step, the dielectric layer is etched until a part of the upper ends of the Fin structures 02 is exposed (i.e., the upper ends of the plurality of Fin structures are exposed), and a part of the upper ends of the SDB grooves is also exposed.
Step nine, forming a gate oxide layer on the surfaces of the exposed Fin structure and the SDB groove; as shown in fig. 10, fig. 10 is a schematic structural diagram after a gate oxide layer is formed on the surfaces of the Fin structure and the SDB groove in the present invention. This step nine forms the gate oxide layer 09 on the exposed surfaces of the Fin structure 02 and the SDB groove 08.
Step ten, forming a plurality of dummy gates arranged at intervals along the transverse direction and side walls attached to the dummy gates on the Fin structure and the SDB groove; as shown in fig. 11, fig. 11 is a schematic structural diagram after forming dummy gates, and in this step ten, a plurality of dummy gates arranged at intervals along the transverse direction (the left-right direction of the plane of fig. 11) and sidewalls 12 attached to the dummy gates are formed on the Fin structure and the SDB groove.
Further, in the tenth step of this embodiment, the dummy gate includes a polysilicon layer 10 and a second hard mask layer 11 located on the polysilicon layer 10.
Eleven, forming a SiP epitaxial structure on the Fin structure between the two adjacent dummy gates on one side of the SDB groove; forming a SiGe epitaxial structure on the Fin structure between the two adjacent dummy gates on the other side of the SDB groove; as shown in fig. 12, fig. 12 is a schematic structural view of the SiP epitaxial structure and the SiGe epitaxial structure formed in the present invention. In the eleventh step, a SiP epitaxial structure 14 is formed on the Fin structure between the two adjacent dummy gates on one side of the SDB groove; and forming a SiGe epitaxial structure 13 on the Fin structure between the two adjacent dummy gates on the other side of the SDB groove.
Further, in the eleventh step of this embodiment, the number of the SiP epitaxial structures formed on the Fin structure between the two adjacent dummy gates on one side of the SDB recess is two.
Further, in the eleventh step of this embodiment, the number of the SiGe epitaxial structures formed on the Fin structure between the two adjacent dummy gates on the other side of the SDB recess is two.
Step twelve, depositing an interlayer dielectric layer to cover the dummy gates and fill spaces between the dummy gates; grinding the interlayer dielectric layer until the top of the pseudo grid is exposed; as shown in fig. 13, fig. 13 is a schematic structural view after an interlayer dielectric layer is formed in the present invention. In the twelfth step, an interlayer dielectric layer 15 is deposited to cover the dummy gates and fill the spaces between the dummy gates; and then grinding the interlayer dielectric layer until the top of the pseudo grid is exposed.
Thirteenth, removing the dummy gates except the dummy gates on the SDB groove to form a groove; as shown in fig. 14, fig. 14 is a schematic structural view of the invention after the dummy gate is removed. In the thirteenth step, the dummy gates on the SDB recesses are remained, and the dummy gates in other portions are all removed.
Further, the removing the dummy gate in the thirteenth step of this embodiment includes removing the polysilicon layer 10 and the second hard mask layer 11, and retaining the sidewall 12.
And step fourteen, filling HK metal in the grooves of the removed dummy gates to form HK metal gates. As shown in fig. 15, fig. 15 is a schematic structural view after forming the HK metal gate in the present invention, as shown in fig. 15. In the fourteenth step, the HK metal is filled in the groove after the dummy gate is removed, so as to form the HK metal gate 16.
In summary, in the invention, in the process of removing the polysilicon in the dummy gate, the polysilicon in the SDB region is retained, so that the pressure release risk of the SiP epitaxial layer and the SiGe epitaxial layer is reduced; the HK metal gate is not filled in the SDB recess, so that the stress of the HKK metal layer will not interact with the stress of the epitaxial layer, and device performance is improved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (7)
1. A method of manufacturing a cut-first SDB FinFET, comprising:
providing a substrate, and forming a plurality of Fin structures which are arranged at intervals along the longitudinal direction on the substrate, wherein the length direction of the Fin structures is the transverse direction which is vertical to the longitudinal direction; then forming a SiN layer on the Fin structure; then forming a first hard mask layer on the SiN layer;
depositing a thin oxide layer, wherein the thin oxide layer covers the upper surface of the substrate and the side wall of the Fin structure;
step three, forming an SDB photoresist pattern on the first hard mask layer of the Fin structure;
etching the first hard mask layer, the SiN layer and the Fin structure along the SDB photoresist pattern to form an SDB groove;
depositing a dielectric layer on the substrate to cover the upper surface of the substrate and the thin oxide layer, filling the SDB groove, and then annealing;
step six, grinding the dielectric layer and the thin oxide layer until the upper surface of the SiN layer is exposed;
seventhly, removing the SiN layer;
step eight, etching the dielectric layer until part of the upper end of the Fin structure is exposed, and simultaneously exposing part of the upper end of the SDB groove;
step nine, forming a gate oxide layer on the surfaces of the exposed Fin structure and the SDB groove;
step ten, forming a plurality of dummy gates arranged at intervals along the transverse direction and side walls attached to the dummy gates on the Fin structure and the SDB groove;
eleven, forming a SiP epitaxial structure on the Fin structure between the two adjacent dummy gates on one side of the SDB groove; forming a SiGe epitaxial structure on the Fin structure between the two adjacent dummy gates on the other side of the SDB groove;
step twelve, depositing an interlayer dielectric layer to cover the dummy gates and fill spaces between the dummy gates; grinding the interlayer dielectric layer until the top of the pseudo grid is exposed;
thirteenth, removing the dummy gates except the dummy gates on the SDB groove to form a groove;
and step fourteen, filling HK metal in the grooves of the removed dummy gates to form HK metal gates.
2. The method of manufacturing a pre-cut SDB FinFET of claim 1, wherein: and in the second step, the method for depositing the thin oxide layer on the upper surface of the substrate and the side wall of the Fin structure is an atomic layer deposition method or an in-situ water vapor generation method.
3. The method of manufacturing a pre-cut SDB FinFET of claim 1, wherein: and the method for depositing the dielectric layer in the fifth step is an FCVD method.
4. The method of manufacturing a pre-cut SDB FinFET of claim 1, wherein: and step ten, the dummy gate comprises a polysilicon layer and a second hard mask layer positioned on the polysilicon layer.
5. The method of manufacturing a pre-cut SDB FinFET of claim 1, wherein: in the eleventh step, the number of the SiP epitaxial structures formed on the Fin structure between the two adjacent dummy gates on one side of the SDB groove is two.
6. The method of manufacturing a pre-cut SDB FinFET of claim 1, wherein: in the eleventh step, the number of the SiGe epitaxial structures formed on the Fin structure between the two adjacent dummy gates on the other side of the SDB groove is two.
7. The method of manufacturing a pre-cut SDB FinFET of claim 4, wherein: and removing the part of the pseudo gate in the thirteenth step, namely removing the polycrystalline silicon layer and the second hard mask layer, and reserving the side wall.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20180061830A1 (en) * | 2016-08-26 | 2018-03-01 | Semiconductor Manufacturing International (Shanghai) Corporation | Semiconductor structure and fabrication method thereof |
| US20190006360A1 (en) * | 2017-06-28 | 2019-01-03 | United Microelectronics Corp. | Semiconductor device and method for fabricating the same |
| CN110854194A (en) * | 2018-08-20 | 2020-02-28 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN112687622A (en) * | 2020-12-25 | 2021-04-20 | 上海华力集成电路制造有限公司 | Single diffusion region cutting structure of fin field effect transistor and forming method thereof |
-
2021
- 2021-05-31 CN CN202110597511.6A patent/CN113394109A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20180061830A1 (en) * | 2016-08-26 | 2018-03-01 | Semiconductor Manufacturing International (Shanghai) Corporation | Semiconductor structure and fabrication method thereof |
| US20190006360A1 (en) * | 2017-06-28 | 2019-01-03 | United Microelectronics Corp. | Semiconductor device and method for fabricating the same |
| CN110854194A (en) * | 2018-08-20 | 2020-02-28 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN112687622A (en) * | 2020-12-25 | 2021-04-20 | 上海华力集成电路制造有限公司 | Single diffusion region cutting structure of fin field effect transistor and forming method thereof |
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