CN113777471A - Method for calibrating relative voltage offset error of measurement module - Google Patents
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- 101000864076 Caenorhabditis elegans Smu-1 suppressor of mec-8 and unc-52 protein Proteins 0.000 description 9
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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Abstract
The invention provides a method for calibrating relative voltage deviation errors of measurement modules, which comprises the steps of selecting a fixed resistor and four measurement modules; fixed resistance leads out four terminals A, B, C, D; calibrating any two measuring modules comprises the steps that the measuring module 1 applies current I to the end A, and the measuring module 2 applies voltage V to the end B; measuring module 3 and measuring module 4 measure C, D the potential V across them1、V2Obtaining the resistance value R of the fixed resistor1(ii) a The measuring module 1 applies voltage V to the end A, and the measuring module 2 applies current I to the end B; measuring module 3 and measuring module 4 measure C, D the potential V across them1’、V2', obtaining the resistance R of the fixed resistor2(ii) a Carrying out average calculation to obtain a real resistance R; by R1Or R2And the difference value of the voltage and the current is R, the relative voltage offset error of the measurement module 3 and the measurement module 4 is delta V. By calibrating the relative voltage bias error between the measurement modules, the measurement modules are prevented from being electrically connectedThe pressure offset error has a great influence on the measurement accuracy of the test equipment.
Description
Technical Field
The invention relates to the technical field of semiconductor device testing, in particular to a method for calibrating relative voltage offset error of a measuring module in electrical property testing equipment.
Background
Various measurement modules, such as a selective modular source measurement unit, are required for electrical testing of semiconductor devices. The modular Source Measurement Unit (SMU) is a precision instrument with high sensitivity and accuracy. The SMU combines source and measurement functions on the same pin or connector, which can provide not only a voltage source with a measurement resolution of less than 1mV, but also a current source with a measurement resolution of less than 1uA, which can simultaneously perform synchronous source measurements on the current and voltage of the same channel. The SMU also provides remote sensing capability and has a four quadrant output capability that integrates bipolar voltage and absorbed power capabilities. The SMU can provide a linear scan voltage and scan current, enabling the IV characteristic of the instrument to be obtained. SMUs are now widely used in industry and are common components in many automated test systems.
Kelvin Four-wire sensing, also known as Four-terminal sensing (4T sensing), Four-wire sensing or 4-point probe method, is an electrical impedance measurement technique that determines a resistance value by measuring a voltage across and a current flowing through a resistance to be measured, by virtue of which a contact resistance and a lead resistance can be eliminated, is widely applied to the measurement of resistances, especially low-resistance resistances, and can perform more accurate measurement than the conventional two-terminal (2T) sensing.
The KLV method also plays an important role in the field of electrical testing of integrated circuits. In the electrical parameter test, the resistance of some resistors is lower than 1 Ω or even 0.1 Ω, and in order to protect the device, the current flowing through the resistors is usually only in mA level during the test. According to ohm's law, the voltage difference between two ends of the resistor to be tested is only mV level or even lower, and the voltage measurement precision of the SMU commonly used for the KLV test of the electrical property test equipment is 0.1mV level, at this time, the measurement error of the SMU can be compared with the real voltage value, so that the KLV test error is larger, and the accurate resistance value cannot be obtained.
The general KLV test method in the electrical parameter test is shown in figure 1, and four ends I are led out from a resistor to be tested1、I2、V1、V2。I1End-applied current signals I, V1、V2Measuring the voltage V by using SMUM1、VM2In which V isM1>VM2Then the resistance value R to be measuredKLV=（VM1-VM2)/I。
The error of the KLV test method mainly comes from the voltage difference measured between two ends of a resistor to be tested, namely VM1-VM2. The SMU Error (Error) for measuring the voltage signal is mainly composed of an offset Error and a gain Error, wherein the offset Error is an absolute Error of the SMU, and the gain Error is a percentage of a reading of the voltage measured by the SMU. Taking an SMU commonly used for electrical parameter testing as an example, when the measured voltage is only mV or even lower, the absolute error is 0.3mV under the applicable range, and the gain error is the voltage reading VM0.02%, i.e. Error =0.02% VM+0.3mV, the gain error is only 0.02% of the ratio, negligible, while the offset error is comparable to the true value and is the main source of KLV test error.
In order to solve the problem of KLV test errors in electrical test equipment, a method for calibrating SMU bias errors needs to be sought.
Disclosure of Invention
The invention provides a method for calibrating a relative voltage offset error of a measurement module, which can calibrate the offset error of an SMU, avoid the influence of the measurement error of the SMU on a KLV test and improve the accuracy of the KLV measurement resistance value.
Other objects and advantages of the present invention will be further understood from the technical features disclosed in the present invention.
To achieve one or a part of or all of the above or other objects, an embodiment of the present invention provides a method for calibrating a relative voltage deviation error of a measurement module, including: step 1: selecting a fixed resistor and four measuring modules which are marked as a measuring module 1, a measuring module 2, a measuring module 3 and a measuring module 4; step 2: the fixed resistor leads out four terminals A, B, C, D; and step 3: and calibrating the relative voltage bias errors of any two of the four measurement modules.
Wherein the calibrating comprises: measuring for the first time: the measuring module 1 applies a current signal I at an A end, and the measuring module 2 applies a voltage signal V at a B end; the measuring module 3 and the measuring module 4 measure C, D the potential across, respectively, denoted as V1、V2Calculating the resistance R of the first measured fixed resistor1(ii) a The measuring module 1 applies a voltage signal V to the end A, and the measuring module 2 applies a current signal I to the end B; the measuring module 3 and the measuring module 4 measure C, D the potential V at the two ends respectively1’、V2', calculating the resistance R of the first measured fixed resistor2(ii) a The resistance value R of the real resistor of the fixed resistor is obtained by the average calculation of the two measurements; through the first measurement of the resistance R of the fixed resistor1Or the resistance value R of the fixed resistor obtained by the second measurement2And calculating the difference value between the actual resistance value R of the fixed resistor and the resistance value R of the real resistor to obtain the relative voltage offset error delta V of the measuring module 3 and the measuring module 4.
Further comprising the step 4: and writing the relative voltage bias errors of any two measurement modules into test software of the test equipment, and outputting correct results by correcting the relative voltage bias errors of the measurement modules in the test. The technical scheme has the advantages that the relative voltage offset error between the measurement modules is calibrated, and the error is written into the test equipment, so that the measurement modules are corrected in the test to obtain a correct result, the voltage offset error of the measurement modules is prevented from generating great influence on the measurement precision of the test equipment, and the method has very important significance particularly in the electrical test of integrated circuits with the test sensitivity in the pA and mV grades.
The measurement module 1 and the measurement module 2 in the step 3 are replaced by any two measurement modules in the four measurement modules, so that the relative voltage offset error of every any two measurement modules can be measured.
The voltage signal V may have a positive value or a negative value, and the current signal I may have a positive value or a negative value. Preferably, in order to simplify the measurement steps and calculation, the value of the voltage signal V is zero; the value of the current signal I is larger than zero.
And in the step 3, the calibration of the relative voltage offset errors of any two measurement modules is realized through manual test and calculation. Or, in the step 3, the code is written into the control software of the test equipment, and the control software realizes calibration of the relative voltage deviation error of any two measurement modules through continuous tests.
The measuring module is a source measuring unit.
Compared with the prior art, the invention has the beneficial effects that: by the method for calibrating the relative voltage offset error of the measurement modules, the calibration of the relative voltage offset error between the measurement modules in the electrical test equipment can be realized, so that the voltage offset error is prevented from generating great influence on the measurement precision of the test equipment. Because the current and the voltage are very small in the electrical test of the integrated circuit, and the test sensitivity is in the pA and mV level, the method has very important significance in the field of the electrical test of the integrated circuit.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings described below are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive efforts.
Fig. 1 is a schematic view of a method for testing KLV by using electrical parameters in the prior art.
FIG. 2 is a diagram illustrating a method for calibrating a relative voltage offset error of a measurement module according to an embodiment of the present invention.
FIG. 3 is a flowchart of a method for calibrating a relative voltage offset error of a measurement module according to an embodiment of the present invention.
Detailed Description
The foregoing and other technical and scientific aspects, features and advantages of the present invention will be apparent from the following detailed description of a preferred embodiment, which is to be read in connection with the accompanying drawings. Directional terms as set forth in the following examples, for example: up, down, left, right, front or rear, etc., are referred to only in the direction of the attached drawings. Accordingly, the directional terminology is used for purposes of illustration and is in no way limiting.
Fig. 2 and fig. 3 are a schematic diagram and a flowchart of a method for calibrating a relative voltage offset error of a measurement module according to an embodiment of the present invention. Referring to fig. 2 and fig. 3 in combination, the method includes: step 1, selecting a fixed resistor R and four measurement modules, where the measurement module in this embodiment is a source measurement unit SMU, hereinafter referred to as SMU for short. These four measurement blocks are labeled SMU1, SMU2, SMU3, SMU4, respectively.
And 2, leading four ends out of the fixed resistor R, wherein the four ends are respectively marked as A, B, C, D.
And 3, calibrating the relative voltage offset errors of any two measurement modules in the four measurement modules. Exemplified by SMU1 and SMU2, the calibration includes: measuring for the first time: the SMU1 applies a current signal I at the A terminal, and the SMU2 applies a voltage signal V at the B terminal; SMU3 and SMU4 measure the potential at C, D ends, respectively, and are denoted as V1、V2I.e. C, D voltage is V1-V2(ii) a At this time, the resistance value R of the fixed resistor is measured1=｜V1-V2｜/ I。
And (3) second measurement: the SMU1 applies a voltage signal V at the A terminal, and the SMU2 applies a current signal I at the B terminal; SMU3 and SMU4 measure the potential V across C, D, respectively1’、V2', i.e. C, D the voltage across it is V1’-V2'; at this time, the resistance value R of the fixed resistor is measured2=｜V1’- V2’｜/ I。
The resistance value R = (R) of the real resistance of the fixed resistance is obtained by the average calculation of the two measurements1+ R2）/2。
By measuring the resistance R of the fixed electrons for the first time1The difference between the resistance value R of the real resistance and the fixed resistance is calculated to give a relative voltage offset error of Δ V = (R) for SMU3 and SMU41-R）*I。
Of course, in other embodiments, the resistance value R of the fixed resistor obtained by the second measurement may be obtained2The difference between the resistance value R of the real resistance and the fixed resistance is calculated to give a relative voltage offset error of Δ V = (R) for SMU3 and SMU42-R）*I。
And 4, writing the relative voltage bias errors of any two measurement modules into test software of the test equipment, and outputting correct results by correcting the relative voltage bias errors of the measurement modules during the test.
The values of the voltage signal V and the current signal I may be positive or negative. For convenience of measurement and calculation, in this embodiment, the voltage signal V takes a value of zero, and the current signal I takes a value greater than zero.
In addition, in the embodiment, calibration of relative voltage offset errors of the SMUs 3 and the SMUs 4 is realized through manual testing and calculation in step 3; of course, in other embodiments, the test code may be written into the control software of the test equipment in a code form, and the control software may calibrate the relative voltage offset errors of SMU3 and SMU4 through continuous testing.
It should be noted that, in step 3 of this embodiment, the SMU1 and SMU2 may be replaced by any two measurement modules in the four measurement modules, so as to measure the relative voltage offset error of each any two measurement modules. For example, replacing the SMU2 with the terminal a, replacing the SMU3 with the terminal B, repeating the calibration step in the step 3, and measuring the potentials at the two ends of C, D by the SMU1 and the SMU4 respectively to calculate the relative voltage offset errors of the SMU1 and the SMU 4; for another example, replacing SMU3 to terminal a, replacing SMU4 to terminal B, repeating the calibration step in step 3, and measuring the potentials at terminals C, D by SMU1 and SMU2 respectively to calculate the relative voltage offset errors of SMU1 and SMU 2. Similarly, by repeating the step 3, the relative voltage offset errors of the SMUs 1 and 3, the SMUs 2 and 3, and the like can be obtained.
The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the invention, which is defined by the claims and the description of the invention, and all simple equivalent changes and modifications made therein are also within the scope of the invention. Moreover, it is not necessary for any embodiment or claim of the invention to address all of the objects, advantages, or features disclosed herein. In addition, the abstract and the title of the invention are provided for assisting the retrieval of patent documents and are not intended to limit the scope of the invention. Furthermore, the terms "first", "second", and the like in the description or the claims are used only for naming elements (elements) or distinguishing different embodiments or ranges, and are not used for limiting the upper limit or the lower limit on the number of elements.
Claims (7)
1. A method for calibrating a measurement module for relative voltage offset error, comprising:
step 1: selecting a fixed resistor and four measuring modules which are marked as a measuring module 1, a measuring module 2, a measuring module 3 and a measuring module 4;
step 2: the fixed resistor leads out four terminals A, B, C, D;
and step 3: calibrating the relative voltage bias errors of any two of the four measurement modules; wherein the calibrating comprises:
measuring for the first time: the measuring module 1 applies a current signal I at an A end, and the measuring module 2 applies a voltage signal V at a B end; the measuring module 3 and the measuring module 4 measure C, D the potential across, respectively, denoted as V1、V2Calculating the resistance R of the first measured solid resistance1；
And (3) second measurement: the measuring module 1 applies a voltage signal V to the end A, and the measuring module 2 applies a current signal I to the end B; the measuring module 3 and the measuring module 4 are dividedSeparately measuring C, D the potential V across1’、V2', calculating the resistance R of the first measured solid resistance2；
The resistance value R of the real resistor of the fixed resistor is obtained by the average calculation of the two measurements;
through the first measurement of the resistance R of the fixed resistor1Or the resistance value R of the fixed resistor obtained by the second measurement2Calculating a relative voltage offset error delta V between the measurement module 3 and the measurement module 4 according to a difference value between the resistance value R of the real resistor and the fixed resistor;
further comprising the step 4: and writing the relative voltage bias errors of any two measurement modules into test software of the test equipment, and outputting correct results by correcting the relative voltage bias errors of the measurement modules in the test.
2. The method for calibrating relative voltage offset errors of measurement modules according to claim 1, wherein the measurement module 1 and the measurement module 2 in the step 3 are replaced by any two measurement modules of the four measurement modules, so as to measure the relative voltage offset error of every any two measurement modules.
3. The method of calibrating relative voltage offset error of a measurement module of claim 1, wherein said voltage signal V is zero.
4. The method of calibrating relative voltage offset error of a measurement module of claim 1, wherein said current signal I is greater than zero.
5. The method for calibrating the relative voltage offset errors of the measurement modules according to claim 1, wherein the calibration of the relative voltage offset errors of any two measurement modules is realized through manual test and calculation in the step 3.
6. The method for calibrating relative voltage offset errors of measurement modules according to claim 1, wherein in step 3, codes are written into control software of the testing equipment, and the control software realizes calibration of relative voltage offset errors of any two measurement modules through continuous testing.
7. A method of calibrating relative voltage offset errors of a measurement module according to any of claims 1 to 6, wherein the measurement module is a source measurement unit.
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Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09203764A (en) * | 1996-01-25 | 1997-08-05 | Hioki Ee Corp | Method for judging presence or absence of poorly connected lead by using four-terminal measuring method |
| JPH10123189A (en) * | 1996-10-16 | 1998-05-15 | Adetsukusu Kk | Measurement method and device for resistance value |
| JP2001153902A (en) * | 1999-11-30 | 2001-06-08 | Hioki Ee Corp | Method of measuring resistance |
| JP2007192723A (en) * | 2006-01-20 | 2007-08-02 | Nissan Motor Co Ltd | Current sensor correcting system and technique |
| CN102829888A (en) * | 2011-06-15 | 2012-12-19 | 上海电器科学研究院 | Method for eliminating three-wire heating resistor measurement errors |
| CN107664739A (en) * | 2016-07-28 | 2018-02-06 | 全球能源互联网研究院 | A kind of HVDC IGCTs level damping resistance dynamic parameter on-line monitoring method |
| CN109142870A (en) * | 2018-09-23 | 2019-01-04 | 东南大学 | The method that a kind of pair of Multi-channel hot resistance carries out wireless accurate measurement |
| KR102079454B1 (en) * | 2018-10-01 | 2020-02-19 | 동의대학교 산학협력단 | Method and apparatus for sensing current of bidirectional single-phase pulse width modulation converter |
| CN111025016A (en) * | 2019-12-18 | 2020-04-17 | 华虹半导体(无锡)有限公司 | Resistance testing method of Kelvin structure |
| CN111736104A (en) * | 2020-08-03 | 2020-10-02 | 苏州华兴源创科技股份有限公司 | Current detection calibration method and device and display device |
| CN112098899A (en) * | 2020-10-13 | 2020-12-18 | 中国人民解放军火箭军工程大学 | Portable intelligent detector and detection method for micro-current multi-core cable test |
| TWI729631B (en) * | 2019-12-18 | 2021-06-01 | 致茂電子股份有限公司 | Method for measuring impedance |
-
2021
- 2021-09-09 CN CN202111055621.6A patent/CN113777471B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09203764A (en) * | 1996-01-25 | 1997-08-05 | Hioki Ee Corp | Method for judging presence or absence of poorly connected lead by using four-terminal measuring method |
| JPH10123189A (en) * | 1996-10-16 | 1998-05-15 | Adetsukusu Kk | Measurement method and device for resistance value |
| JP2001153902A (en) * | 1999-11-30 | 2001-06-08 | Hioki Ee Corp | Method of measuring resistance |
| JP2007192723A (en) * | 2006-01-20 | 2007-08-02 | Nissan Motor Co Ltd | Current sensor correcting system and technique |
| CN102829888A (en) * | 2011-06-15 | 2012-12-19 | 上海电器科学研究院 | Method for eliminating three-wire heating resistor measurement errors |
| CN107664739A (en) * | 2016-07-28 | 2018-02-06 | 全球能源互联网研究院 | A kind of HVDC IGCTs level damping resistance dynamic parameter on-line monitoring method |
| CN109142870A (en) * | 2018-09-23 | 2019-01-04 | 东南大学 | The method that a kind of pair of Multi-channel hot resistance carries out wireless accurate measurement |
| KR102079454B1 (en) * | 2018-10-01 | 2020-02-19 | 동의대학교 산학협력단 | Method and apparatus for sensing current of bidirectional single-phase pulse width modulation converter |
| CN111025016A (en) * | 2019-12-18 | 2020-04-17 | 华虹半导体(无锡)有限公司 | Resistance testing method of Kelvin structure |
| TWI729631B (en) * | 2019-12-18 | 2021-06-01 | 致茂電子股份有限公司 | Method for measuring impedance |
| CN111736104A (en) * | 2020-08-03 | 2020-10-02 | 苏州华兴源创科技股份有限公司 | Current detection calibration method and device and display device |
| CN112098899A (en) * | 2020-10-13 | 2020-12-18 | 中国人民解放军火箭军工程大学 | Portable intelligent detector and detection method for micro-current multi-core cable test |
Non-Patent Citations (2)
| Title |
|---|
| 周翔;雷民;严强虎: "一种改进的高压高阻标准箱设计", 中国测试, vol. 46, no. 011, 31 December 2020 (2020-12-31) * |
| 李楚元;: "基于相频特性的电流传感器相位校准", 电气技术, no. 10, 15 October 2018 (2018-10-15) * |
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