CN113764409A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN113764409A
CN113764409A CN202110735266.0A CN202110735266A CN113764409A CN 113764409 A CN113764409 A CN 113764409A CN 202110735266 A CN202110735266 A CN 202110735266A CN 113764409 A CN113764409 A CN 113764409A
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China
Prior art keywords
layer
gate
source
drain
transistor
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CN202110735266.0A
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English (en)
Inventor
杨智铨
包家豪
林佑宽
洪连嵘
王屏薇
林士豪
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN113764409A publication Critical patent/CN113764409A/zh
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    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H10B10/125—Static random access memory [SRAM] devices comprising a MOSFET load element the MOSFET being a thin film transistor [TFT]
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Abstract

本发明实施例提供一种半导体装置，包括栅极延伸结构、第一源极/漏极特征和第二源极/漏极特征、沿着一个方向在第一源极/漏极特征和第二源极/漏极特征之间延伸的通道构件的垂直堆叠以及围绕通道构件的垂直堆叠中的每一个堆叠的栅极结构。栅极延伸结构直接接触第一源极/漏极特征。

Description

半导体装置
技术领域
本发明实施例涉及一种半导体装置，尤其涉及具有将一个晶体管的源极/漏极特征连接至另一个晶体管的栅极结构的连接结构的半导体装置。
背景技术
半导体集成电路(integrated circuit；IC)工业呈指数成长。在IC材料及IC设计的技术进步产生多个IC世代，每一个IC世代比上一个IC世代有更小及更复杂的电路。在IC发展过程中，几何尺寸(例如：工艺可做出的最小部件(或线路))会下降，而功能密度(例如:每一芯片区域的相连元件数量)通常都会增加。此微缩过程藉由增加生产效率及降低相关成本提供了优势。此微缩亦增加了IC工艺及制造的复杂性。
举例来说，随着集成电路(IC)技术朝着更小的技术节点发展，已经引入了多栅极装置，以藉由增加栅极-通道耦合、减小关闭状态电流(off-state current)以及减小短通道效应(short-channel effect；SCE)来改善栅极控制。多栅极装置通常是指具有设置在通道区的多于一侧上方的栅极结构或其一部分的装置。类鳍式场效晶体管(Fin-like fieldeffect transistor；FinFET)和多桥通道(multi-bridge-channel；MBC)晶体管是多栅极装置的示例，其已成为高效能和低漏电应用的热门和有望的候选。FinFET的升高通道(elevated channel)在多于一侧上被栅极围绕(例如：栅极围绕从基板延伸的半导体材料的“鳍片”的顶部和侧壁)。MBC晶体管具有可以部分或全部围绕通道区延伸的栅极结构，以在两侧或更多侧上对通道区提供访问。由于MBC晶体管的栅极结构围绕通道区，因此MBC晶体管也可以称为围绕栅极晶体管(surrounding gate transistor：SGT)或环绕式栅极(gate-all-around(；GAA)晶体管。MBC晶体管的通道区可以由纳米线、纳米片或其他纳米结构形成，并且由于这个原因，MBC晶体管也可以被称为纳米线晶体管或纳米片晶体管。
在实现多栅极装置的一些IC电路中，可以藉由各种接点结构(contactstructure)来实现栅极结构和源极/漏极特征之间的连接。举例来说，到栅极结构的栅极接点可以通过对接接点(butted contact)耦接至到源极/漏极特征的源极/漏极接点。对接接点不是自我对准的，并且需要额外的光刻操作，这可能会导致成本增加。此外，对接接点可能会占用金属线层中的空间并且影响布线。因此，尽管常规的栅极至源极/漏极连接(gate-to-source/drain connection)通常已足以满足其预期目的，但它们并非在各个方面都令人满意。
发明内容
本公开提供一种半导体装置。半导体装置包括栅极延伸结构、第一源极/漏极特征和第二源极/漏极特征、多个通道构件的垂直堆叠以及栅极结构。通道构件沿着一个方向在第一源极/漏极特征和第二源极/漏极特征之间延伸。栅极结构围绕通道构件的垂直堆叠的每一个。栅极延伸结构直接接触第一源极/漏极特征。
本公开提供一种静态随机存取存储器单元。静态随机存取存储器单元包括第一上拉多桥通道晶体管和第一下拉多桥通道晶体管、第二上拉多桥通道晶体管和第二下拉多桥通道晶体管、第一传输栅多桥通道晶体管以及第二传输栅多桥通道晶体管。第一上拉多桥通道晶体管和第一下拉多桥通道晶体管耦接在一起以形成第一反相器。第二上拉多桥通道晶体管和第二下拉多桥通道晶体管耦接在一起以形成第二反相器。第一传输栅多桥通道晶体管耦接至第一反相器的输出和上第二反相器的输入。第二传输栅多桥通道晶体管耦接至第二反相器的输出和第一反相器的输入。第一下拉多桥通道晶体管的第一栅极电极直接接触第二上拉多桥通道晶体管的第一源极/漏极特征。第二下拉多桥通道晶体管的第二栅极电极直接接触第一上拉多桥通道晶体管的第二源极/漏极特征。
本公开提供一种半导体装置的制造方法。半导体装置的制造方法包括接收工件，工件包括鳍状结构。鳍状结构沿着第一方向纵向延伸，其中鳍状结构在末端表面纵向终止，鳍状结构包括基部和在基部上方的堆叠部，并且堆叠部包括多个通道层，通道层与多个牺牲层交错设置。半导体装置的制造方法还包括形成隔离特征，隔离特征沿着基部和末端表面的下部的多个侧壁延伸；在堆叠部上方沉积包覆层，其中包覆层包括端部，端部沿着末端表面的上部延伸；在包覆层和隔离特征上方沉积鳍片间隔物层；在沉积鳍片间隔物层之后，在工件上方沉积介电层；使鳍状结构的源极/漏极区凹陷，以形成源极/漏极凹陷；在源极/漏极凹陷中沉积源极/漏极特征；选择性地移除包覆层的端部，以通过末端表面的上部暴露源极/漏极特征；以及在末端表面的上部上方沉积栅极电极层，以直接接触源极/漏极特征。
附图说明
本公开实施例可通过阅读以下的详细说明以及范例并配合相应的附图以更详细地了解。需要注意的是，依照本领域的标准操作，各种特征部件并未依照比例绘制。事实上，为了清楚论述，各种特征部件的尺寸可以任意地增加或减少。
图1根据本公开的一或多个方面显示了用于形成半导体装置的方法的流程图。
图2A、图2D以及图3A、图4A、图5A、图6A、图7A、图8A、图9A根据本公开的一或多个方面显示了在图1的方法的各个工艺站点期间的工件的局部示意图。
图2B、图3B、图4B、图5B、图6B、图7B、图8B、图9B、图10、图11、图12、图13、图14、图15、图16以及图2C、图3C、图4C、图5C、图6C、图7C、图8C、图9C根据本公开的一或多个方面显示了在图1的方法的各个工艺站点期间的工件的局部剖面图。
图17根据本公开的一或多个方面显示了静态随机存取存储器(static randomaccess memory；SRAM)单元的电路图。
图18和图19根据本公开的一或多个方面显示了用于实现图17中的SRAM单元的布局。
附图标记说明如下：
100:方法
102～132:操作
200:工件、半导体装置
202:基板
204:堆叠
206:牺牲层
208:通道层
209:第一层
210:硬掩膜层
211:第二层
212:鳍状结构
212B:基部
212S:堆叠部
213:鳍片切割开口
215:末端表面、末端侧壁
214:隔离特征
2100:硅衬垫
216:包覆层
218:鳍片间隔物
220:填充层
224:冗余介电层
226:冗余电极
230:冗余栅极堆叠
2160:末端包覆层
212C:通道区
212SD:源极/漏极区
234:栅极间隔物
236:源极/漏极沟槽
238:内部间隔物凹陷
240:底部特征
241:空隙
242:内部间隔物特征
243:接点蚀刻停止层
244:层间介电层
245:源极/漏极特征
246:外层
248:内层
250:栅极沟槽
252:末端沟槽
2080:通道构件
253:光阻特征
219:隔离结构
254:界面层
256:栅极介电层
258:功函数层
260:金属填充层
261:栅极电极层
262:栅极覆盖层
264:栅极自我对准接点介电层
270:栅极结构
280:栅极延伸结构
266:硅化物层
268:源极/漏极接点
300:静态随机存取存储器单元
301:第一下拉晶体管
302:第二下拉晶体管
303:第一上拉晶体管
304:第二上拉晶体管
305:第一传输栅晶体管
306:第二传输栅晶体管
308:第一反相器
310:第二反相器
QB:第一储存节点
Q:第二储存节点
400:布局
402:第一栅极结构
404:第二栅极结构
406:第一漏极
408:第二漏极
410:第一栅极延伸结构
420:第二栅极延伸结构
10:N阱
20:第一P阱
22:第二P阱
430:电源轨
具体实施方式
本公开提供许多不同的实施例或范例以实施本案的不同特征。以下的公开内容叙述各个构件及其排列方式的特定实施例，以简化说明。当然，这些特定的范例并非用以限定。举例来说，若是本公开叙述了一第一特征形成于一第二特征之上或上方，即表示其可能包含上述第一特征与上述第二特征是直接接触的实施例，亦可能包含了有附加特征形成于上述第一特征与上述第二特征之间，而使上述第一特征与第二特征可能未直接接触的实施例。另外，以下本公开不同实施例可能重复使用相同的参考符号及/或标记。这些重复为了简化与清晰的目的，并非用以限定所讨论的不同实施例及/或结构之间有特定的关系。
此外，其与空间相关用词。例如“在……下方”、“下方”、“较低的”、“上方”、“较高的”及类似的用词，为了便于描述图示中一个元件或特征与另一个(些)元件或特征之间的关系。除了在附图中示出的方位外，这些空间相关用词意欲包含使用中或操作中的装置的不同方位。除此之外，设备可能被转向不同方位(旋转90度或其他方位)，则在此使用的空间相关词也可依此相同解释。此外，当数字或数字范围以“约”、“近似”等描述时，除非另有说明，否则该术语旨在涵盖在所述数值的+/-10％内的数值。举例来说，术语“约5nm”包括4.5nm至5.5nm的尺寸范围。
本公开总体上涉及多栅极装置之间的接点结构，并且更具体地涉及栅极结构和源极/漏极特征之间的连接。
IC制造流程通常可以分为三类：前段(front-end-of-line；FEOL)工艺、中段(middle-end-of-line；MEOL)工艺和后段(back-end-of-line；BEOL)工艺。FEOL工艺通常包括与制造IC装置(如晶体管)相关的工艺。举例来说，FEOL工艺可以包括形成隔离特征、栅极结构以及源极/漏极特征。MEOL工艺通常包括与制造到IC装置的导电特征的接点(例如到栅极结构及/或源极/漏极特征的接点)相关的工艺。BEOL工艺通常包括与制造多层互连(MLI)特征相关的工艺，多层互连特征与藉由FEOL和MEOL工艺制造的IC特征互连，从而实现IC装置的操作。由FEOL工艺制造的特征可以被称为FEOL特征。由MEOL工艺制造的特征可以被称为MEOL特征。由BEOL工艺制造的特征可以被称为BEOL特征。
一些IC装置包括在FEOL结构之间的连接。举例来说，一些静态随机存取存储器(SRAM)单元包括一个晶体管的源极/漏极特征到另一个晶体管的栅极结构之间的连接。由于缺少FEOL接点结构，因此制造了MEOL或甚至BEOL接点特征(例如对接接点)来实现这种连接。这样的MEOL或BEOL接点特征可能需要额外的光刻工艺，并且可能增加制造成本。
本公开提供了一种半导体结构，半导体结构包括FEOL接点结构以将一个晶体管的源极/漏极特征连接至另一个晶体管的栅极结构。在一些实施例中，包覆层(claddinglayer)沉积在鳍状结构上方，鳍状结构包括由基板形成的基部和由多个通道层的堆叠形成的堆叠部，通道层与多个牺牲层交错设置。鳍状结构可以经受鳍片切割工艺并且可以包括末端表面(end surface)。包覆层也沉积在鳍状结构的末端表面上方。在形成内部间隔物特征、形成源极/漏极特征、从牺牲层释放通道层以形成通道构件以及沿着末端表面移除包覆层之后，源极/漏极特征的多个部分可以从末端表面暴露。因为包覆层由可以相对于通道构件被选择性地蚀刻的材料形成，所以源极/漏极特征从末端表面的暴露是自我对准的。接着将栅极电极层沉积在源极/漏极特征的暴露部分上，以电性耦接至源极/漏极特征。本公开的此连接特征(其在FEOL阶级(level)形成)可以排除形成MEOL或甚至BEOL接点结构以连接栅极结构和源极/漏极特征的需要。
现在将参照附图更详细地描述本公开的各个方面。图1根据本公开的一或多个方面显示了从工件形成半导体装置的方法100的流程图。方法100仅是一个示例，并不旨在将本公开限制于方法100中明确说明的内容。可以在方法100之前、之中和之后提供额外操作，并且对于方法的额外实施例，可以替换、消除或移动所述的一些操作。为了简单起见，此处没有详细描述所有操作。下面结合图2A至图9A、图2B至图16、图2C至图9C和图2D描述方法100，其显示了根据方法100的实施例在不同制造站点的工件200的局部示意图或剖面图。为了说明装至和方法实施例的各个方面，以字母“A”结尾的附图显示了工件200的局部示意图、以字母“B”结尾的附图显示了沿着X方向的局部剖面图、以字母“C”结尾的附图显示了沿着Y方向的局部剖面图。另外，图10至图16显示了沿着X方向的局部剖面图。另外，图2D还显示了工件200的不同片段的局部示意图。因为半导体装置将从工件200形成，所以根据内文需要，工件200可以被称为半导体装置200。尽管在附图中显示了包括MBC晶体管的实施例，但是本公开不限于此，并且可以应用于其他多栅极装置。如上面所述，MBC晶体管也可以被称为SGT、GAA晶体管、纳米片晶体管或纳米线晶体管。
参照图1和图2A至图2C，方法100包括操作102，其接收工件200。如图2A、图2B和图2C所示，工件200包括基板202和设置在基板202上的堆叠204。在一个实施例中，基板202可以是硅(Si)基板。在一些其他实施例中，基板202可以包括其他半导体，例如锗(Ge)、硅锗(SiGe)或三五(III-V)族半导体材料。示例III-V族半导体材料可以包括砷化镓(GaAs)、磷化铟(InP)、磷化镓(GaP)、氮化镓(GaN)、磷砷化镓(GaAsP)、砷化铝铟(AlInAs)、砷化铝镓(AlGaAs)、磷化镓铟(GaInP)和砷化铟镓(InGaAs)。基板202还可以包括绝缘层，例如氧化硅层，以具有绝缘体上硅(silicon-on-insulator；SOI)结构或绝缘体上锗(germanium-on-insulator；GOI)结构。在一些实施例中，基板202可以包括一或多个阱区(well region)，例如掺杂有N型掺杂物(即磷(P)或砷(As))的N型阱区或掺杂有P型掺杂物(即硼(B))的P型阱区，以用于形成不同类型的装置。可以使用离子注入或热扩散来形成N型阱和P型阱的掺杂。
仍参照图2A、图2B和图2C，堆叠204可以包括与多个牺牲层206交错(interleave)设置的多个通道层208。通道层208和牺牲层206可以具有不同的半导体组成。在一些实施例中，通道层208由硅(Si)形成，并且牺牲层206由硅锗(SiGe)形成。在这些实施例中，牺牲层206中的额外锗含量允许牺牲层206的选择性移除或凹陷，而大抵不损害通道层208。在一些实施例中，可以使用外延工艺来沉积牺牲层206和通道层208。可以使用化学气相沉积(Chemical Vapor Deposition；CVD)沉积技术(例如：气相外延(vapor-phase epitaxy；VPE)及/或超高真空CVD(ultra-high vacuum CVD；UHV-CVD))、分子束外延(molecularbeam epitaxy；MBE)及/或其他合适工艺来外延地沉积堆叠204。牺牲层206和通道层208交替地沉积，以形成堆叠204。值得注意的是，如图2A、图2B和图2C所示三(3)层的牺牲层206和三(3)层的沟道层208的被交替地和垂直地布置，其仅出于说明目的，并不具有限定意义。层的数量取决于半导体装置200所需的通道构件数量。在一些实施例中，通道层208的数量在2和10之间。为了图案化目的，工件200还可以在堆叠204上方包括硬掩膜层210。硬掩膜层210可以是单层或多层。在一个示例中，硬掩膜层210是多层的，并且包括第一层209和在第一层209上方的第二层211。在一些实施例中，第一层209由氮化硅形成，并且第二层211由氧化硅形成。在一些替代实施例中，第一层由硅锗(SiGe)形成，并且第二层由硅(Si)形成。
参照图1、图2A、图2B、图2C和图2D，方法100包括操作104，其形成鳍状结构212。如图2A、图2B和图2C所示，每一个鳍状结构212包括从基板202的一部分形成的基部212B和从堆叠204形成的堆叠部212S。堆叠部212S设置在基部212B上方。在一些实施例中，在操作104中，堆叠204和基板202被图案化，以形成鳍状结构212。鳍状结构212沿着Y方向纵向延伸，并且从基板202沿着Z方向垂直延伸。可以使用包括双重图案化或多重图案化工艺的合适工艺来图案化鳍状结构212。通常来说，双重图案化或多重图案化工艺将光刻和自我对准工艺结合，从而允许创建具有节距小于使用单一、直接光刻工艺可获得的间距的图案。举例来说，在一个实施例中，材料层形成在基板上方，并且使用光刻工艺被图案化。使用自我对准工艺在图案化的材料层旁边形成间隔物。接着移除材料层，并且接着可以使用剩余的间隔物或心轴藉由蚀刻堆叠204和基板202来图案化鳍状结构212。蚀刻工艺可以包括干式蚀刻、湿式蚀刻、反应离子蚀刻(reactive ion etching；RIE)及/或其他合适工艺。
在一些实施例中，鳍状结构212可以藉由鳍片切割工艺被分段(segment)以形成鳍片切割开口213，如图2D所示。每一个鳍状结构212具有暴露在鳍片切割开口213中的末端表面215。基板202的额外表面也可以在鳍片切割开口213中暴露。末端表面215也可以称为末端侧壁215。值得注意的是，除非使用掩膜，否则材料的后续顺应性(conformal)或毯式(blanket)沉积可能导致材料沉积在鳍片切割开口213中和末端表面215上方。
参照图1、图3A至图5A、图3B至图5B和图3C至图5C，方法100包括操作106，其形成隔离特征214。在形成鳍状结构212之后，在相邻的鳍状结构212之间形成在图5A和图5C所示的隔离特征214。隔离特征214也可以称为浅沟槽隔离(shallow trench isolation；STI)特征214。在示例工艺中，如图3A、图3B和图3C所示，首先在工件200上方沉积用于隔离特征214的介电材料，用介电材料填充鳍状结构212之间的沟槽。尽管没有明确说明，但是用于隔离特征214的介电材料也沉积在鳍片切割开口213(图2D所示)中。在一些实施例中，介电材料可以包括氧化硅、氮化硅、氮氧化硅、掺氟硅酸盐玻璃(FSG)、低k介电质、其组合及/或其他合适材料。在各种示例中，可以藉由CVD工艺、次大气压CVD(subatmospheric CVD；SACVD)工艺、流动式CVD(flowable CVD；FCVD)工艺、(Atomic Layer Deposition；ALD)工艺、旋涂及/或其他合适工艺来沉积介电材料。接着如图4A、图4B和图4C所示，使沉积的介电材料变薄并平坦化(例如藉由化学机械研磨(chemical mechanical polishing；CMP)工艺)，直到暴露硬掩膜层210的至少一部分。在所示的实施例中，执行平坦化直到暴露第一层209。在未明确显示的其他实施例中，可以执行平坦化直到暴露第二层211。接着参照图5A、图5B和图5C，藉由干式蚀刻工艺、湿式蚀刻工艺及/或其组合进一步使平坦化的介电材料凹陷，以形成隔离特征214。如图5A和图5C所示，鳍状结构212的堆叠部212S在隔离特征214上方升高，而基部212B被隔离特征214围绕。在一些实施例中，为了保护牺牲层206免受意外蚀刻，使用ALD或CVD在鳍状结构212上方顺应性地沉积硅衬垫2100。在一些实施例中，硅衬垫2100从鳍状结构212的表面外延成长。在那些实施例中，第一层209可以由硅锗形成，并且第二层211可以由硅形成。
参照图1和图6A至图6C，方法100包括操作108，其在鳍状结构212上形成包覆层216。在一些实施例中，包覆层216可以具有与牺牲层206的组成相似的组成。在一个示例中，与牺牲层206一样，包覆层216可以由硅锗(SiGe)形成。此共同的组成允许在后续的工艺中选择性地移除牺牲层206和包覆层216。在一些实施例中，可以使用气相外延(VPE)或分子束外延(MBE)来顺应性和外延地成长包覆层216。在一些替代实施例中，可以使用化学气相沉积(CVD)、原子层沉积(ALD)或其他合适沉积方法来沉积包覆层216。如图6A、图6B和图6C所示，包覆层216设置在鳍状结构212的侧壁上、末端侧壁215上(在图6A、图6B和图6C中未明确显示，但在图10中显示)以及第一层209的顶表面上。在一些实施例中，其包覆层216的沉积不是选择性的，在操作108的操作中可以包括回蚀工艺以移除在隔离特征214的顶表面上的包覆层216。示例性的回蚀工艺可以是干式蚀刻工艺，其包括使用溴化氢(HBr)、氧气(O2)、氯气(Cl2)或其混合物的电浆。在一些情况下，包覆层216可以具有在约5nm至约10nm之间的厚度。一些实施例中，在包覆层216的沉积是选择性的并且第一层209由硅锗形成，在操作108中可以省略前述的回蚀操作。在附图中未显示的一些替代实施例中，第一层209由氮化硅形成，并且在形成包覆层之前被完全移除。在那些替代实施例中，包覆层216是藉由外延成长沉积的，并且对半导体材料是选择性的。
参照图1和图7A至图7C，方法100包括操作110，其在包覆层216上方形成鳍片间隔物218。在一些实施例中，鳍片间隔物218由介电材料形成，以允许选择性地蚀刻包覆层216而大抵不损害鳍片间隔物218。鳍片间隔物218可以包括氮化硅、氮氧化硅、氮碳氧化硅或氮碳化硅。在一些实施例中，鳍片间隔物218可以使用CVD、ALD或其他合适沉积方法来沉积。如图7A至图7C所示，鳍片间隔物218设置在隔离特征214的顶表面上以及包覆层216的侧壁和顶表面上。鳍片间隔物218也沉积在设置在末端侧壁215上的包覆层216上方。尽管在图7A至图7C中未明确显示在末端侧壁215上的鳍片间隔物218，但在图10中显示了鳍片间隔物218。
参照图1和图8A至图8C，方法100包括操作112，其在工件200上方沉积填充层220。在一些实施例中，填充层220的组成可以与隔离特征214的组成相似。在这些实施例中，可以使用CVD工艺、SACVD工艺、FCVD工艺、ALD工艺、PVD工艺、旋涂及/或其他合适工艺来沉积填充层220。在一个示例中，如从第一层209或最顶的通道层208测量的(如果硬掩膜层210在较早的工艺中被完全移除)，可以使用FCVD工艺将填充层220沉积到约2000nm和约4500nm的厚度。
参照图1和图9A至图9C，方法100包括操作114，其工件200被平坦化。在一些实施例中，使用CMP工艺平坦化工件200，直到暴露第一层209的顶表面。在一些未明确显示的替代实施例中，第一层在较早的工艺中被移除或者在操作114中藉由平坦化被移除。在这些替代实施例中，最顶的通道层208可以暴露在顶表面中。
参照图1和图10，方法100包括操作116，其在鳍状结构212上方形成冗余栅极堆叠230。在一些实施例中，采用栅极替换工艺(或栅极后工艺(gate-last process))，其中冗余栅极堆叠230用作功能栅极结构的占位物(placeholder)。其他工艺和配置也是可能的。如图10所示，每一个冗余栅极堆叠230包括设置在冗余介电层224上方的冗余电极226。在冗余栅极堆叠230下方的鳍装置结构212的区域可以被称为通道区212C。鳍状结构212中的每一个通道区212C被夹设在两个源极/漏极区212SD之间以用于源极/漏极形成。在示例工艺中，藉由CVD将冗余介电层224毯覆地沉积(blanketly deposite)在工件200上方。为了将材料层图案化成冗余电极226，在材料层上方沉积栅极顶部硬掩膜(未显示)。栅极顶部硬掩膜可以是多层的，并且包括氮化硅硬罩层和在氮化硅硬罩层上方的氧化硅硬罩层。接着使用光刻工艺图案化用于冗余电极226的材料层，以形成冗余电极226。在一些实施例中，冗余介电层224可以包括氧化硅，并且冗余电极226可以包括多晶结晶硅(多晶硅)。在图10所示的一些实施例中，冗余电极226之一至少部分地形成在沿着鳍状结构212的末端侧壁215沉积的包覆层216上方。为了便于参考，可将包覆层216沿着末端侧壁215的部分称为末端包覆层2160。如图10所示，末端包覆层2160的顶表面直接接触冗余介电层224。尽管在图10中未明确显示，但是可以非等向性地蚀刻和移除冗余介电层224的未被冗余电极226保护的部分。结果，每一个冗余栅极堆叠包括冗余介电层224和在冗余介电层224上方的冗余电极226。
参照图1和图11，方法100包括操作118，其沿着冗余栅极堆叠230的侧壁形成至少一个栅极间隔物234。该至少一个栅极间隔物234可以包括两个或更多个栅极间隔物层。可以选择用于至少一个栅极间隔物234的介电材料，以允许选择性地移除冗余栅极堆叠230。合适的介电材料可以包括氮化硅、氮碳氧化硅、氮碳化硅、氧化硅、碳氧化硅、碳化硅、氮氧化硅及/或其组合。可以使用CVD，次大气压CVD(SACVD)或ALD在工件200上方顺应性地沉积至少一个栅极间隔物234。
参照图1和图11，方法100包括操作120，在其使源极/漏极区212SD凹陷以形成源极/漏极沟槽236。使用冗余栅极堆叠230和至少一个栅极间隔物234用作蚀刻掩膜，非等向性地蚀刻工件200，以在源极/漏极区212SD上方形成源极/漏极沟槽236。在图11所示的一些实施例中，在操作120中的操作可以大抵移除在源极/漏极区212SD中的鳍状结构212的堆叠部212S，并且源极/漏极沟槽236可以延伸到从基板202形成的基部212B中。在操作120的非等向性蚀刻可以包括干式蚀刻工艺或合适蚀刻工艺。举例来说，干式蚀刻工艺可以实施含氧气体、氢气、含氟气体(例如：四氟化碳(CF4)、六氟化硫(SF6)、二氟甲烷(CH2F2)、三氟甲烷(CHF3)及/或六氟乙烷(C2F6))、含氯气体(例如：氯气(Cl2)、氯仿(CHCl3)、四氯化碳(CCl4)及/或三氯化硼(BCl3))、含溴气体(例如：溴化氢(HBr)及/或三溴甲烷(CHBr3))、含碘气体、其他合适气体及/或电浆及/或其组合。
参照图1、图11和图12，方法100包括操作122，其形成内部间隔物特征242。参照图11，在操作122中，首先选择性地且部分地使在源极/漏极沟槽236中暴露的牺牲层206凹陷，以形成内部间隔物凹陷238，同时大抵未蚀刻暴露的通道层208。在通道层208本质上由硅(Si)组成并且牺牲层206本质上由硅锗(SiGe)组成的实施例中，牺牲层206的选择性和部分凹陷可以包括硅锗(SiGe)氧化工艺，接着移除硅锗(SiGe)氧化物。在那个实施例中，硅锗(SiGe)氧化工艺可以包括使用臭氧。在一些其他实施例中，选择性凹陷可以是选择性等向性蚀刻工艺(例如：选择性干式蚀刻工艺或选择性湿式蚀刻工艺)，并且牺牲层206凹陷的程度藉由蚀刻工艺的持续时间控制。选择性干式蚀刻工艺可以包括使用一或多种氟基蚀刻剂(fluorine-based etchant)，例如氟气或氢氟烃(hydrofluorocarbon)。选择性湿式蚀刻工艺可以包括氟化氢(HF)或氨水(NH4OH)蚀刻剂。因为包覆层216和牺牲层206共享相似的组成，所以在操作122中可以蚀刻包覆层216。然而，末端包覆层2160由冗余栅极堆叠230和在其上方的至少一个栅极间隔物234保护，并且未被蚀刻。接着使用CVD或ALD在工件200上方顺应性地沉积内部间隔物材料层，包括沉积在内部间隔物凹陷238上方和沉积到内部间隔物凹陷238中。内部间隔物材料可以包括氮化硅、氮碳氧化硅、氮碳化硅、氧化硅、碳氧化硅、碳化硅或氮氧化硅。在沉积内部间隔物材料层之后，回蚀内部间隔物材料层以形成内部间隔物特征242，如图12所示。在一些实施例中，内部间隔物材料可以沉积在源极/漏极沟槽236的底表面上，并且可以在回蚀工艺之后保留，从而留下底部特征240。由于底部特征240和内部间隔物特征242皆由相同的内部间隔物材料形成，因此它们自然具有相同的组成。
参照图1和图12，方法100包括操作124，其在源极/漏极沟槽236中形成源极/漏极特征245。在一些实施例中，每一个源极/漏极特征245可以包括外层246和内层248。为了形成源极/漏极特征245，首先在通道层208和基板202的暴露的半导体表面上选择性地且外延地沉积外层246，接着在外层246上选择性地且外延地沉积内层248。可以使用外延工艺沉积包括外层246和内层248的源极/漏极特征245，例如气相外延(VPE)、超高真空CVD(UHV-CVD))、分子束外延(MBE)及/或其他合适工艺。源极/漏极特征245可以是N型或P型。当源极/漏极特征245是N型时，外层246和内层248中的每一者可以包括硅(Si)，并且可以掺杂有N型掺杂物，例如磷(P)或砷(As)。当源极/漏极特征245是P型时，外层246和内层248中的每一者可以包括硅锗(SiGe)或锗(Ge)，并且可以掺杂有P型掺杂物，例如硼(B)或镓(Ga)。无论源极/漏极特征245的导电类型为何，内层248中的掺杂浓度可以大于外层246以减小接触电阻。在一些实施例中，内层248和外层246可以掺杂有相同的掺杂物种类(dopant species)。在一些替代实施例中，内层248和外层246可以掺杂有不同的掺杂物种类。外层246和内层248的掺杂可以在其沉积时原位(in situ w)执行，也可以使用注入工艺(例如接面注入工艺(junction implant process))来异位(situ)掺杂。
参照图12，尽管内层248的外延沉积选择性地形成在半导体表面上，但是内层248的过度成长可以在内部间隔物特征242上方合并。另外，由于选择性，外层246可能不沉积在底部特征240上方，留下空隙(void)241。如图12所示，空隙241设置在外层246的底部和底部特征240之间。
参照图1和图12，方法100包括操作126，其沉积接点蚀刻停止层(contact etchstop layer；CESL)243和层间介电(interlayer dielectric；ILD)层244。在示例工艺中，首先在工件200上方顺应性地沉积CESL 243，并且接着在CESL243上方毯覆地沉积ILD层244。CESL 243可以包括氮化硅、氧化硅、氮氧化硅及/或本技术领域中已知的其他材料。可以使用ALD、电浆辅助化学气相沉积(plasma-enhanced chemical vapor deposition；PECVD)工艺及/或其他合适沉积或氧化工工艺来沉积CESL 243。在一些实施例中，ILD层244包括材料，材料例如四乙氧基硅烷(tetraethylorthosilicate；TEOS)氧化物、未掺杂的硅酸盐玻璃或掺杂的氧化硅，例如硼磷硅酸盐玻璃(borophosphosilicate glass；BPSG)、熔融石英玻璃(fused silica glass；FSG)、磷硅酸盐玻璃(phosphosilicate glass；PSG)、硼掺杂硅玻璃(boron doped silicon glass；BSG)及/或其他合适介电材料。可以藉由旋涂、FCVD工艺或其他合适沉积技术来沉积ILD层244。在一些实施例中，在形成ILD层244之后，可以退火工件200以改善ILD层244的完整性(integrity)。为了移除多余的材料并暴露冗余栅极堆叠230的冗余电极226的顶表面，可以对工件200执行平坦化工艺(例如化学机械研磨(CMP)工艺)以提供平坦的顶表面，如图12所示。冗余电极226的顶表面在平坦的顶表面上暴露。
参照图1和图13，方法100包括操作128，其移除冗余栅极堆叠230，并且释放(release)通道构件2080。在操作128中，从工件200移除由于在操作126中的操作而暴露的冗余栅极堆叠230。冗余栅极堆叠230的移除导致在通道区212C上方的栅极沟槽250。冗余栅极堆叠230的移除可以包括对冗余栅极堆叠230中的材料具有选择性的一或多种蚀刻工艺。举例来说，可以使用选择性湿式蚀刻、选择性干式蚀刻或其组合来执行冗余栅极堆叠230的移除。在移除冗余栅极堆叠230之后，通道区212C中的通道层208和牺牲层206的侧壁在栅极沟槽250中暴露。通道区212C中的通道层208之间的暴露的牺牲层206可以被选择性地移除，以释放通道层208以形成通道构件2080。通道构件2080沿着Z方向垂直地堆叠。牺牲层206的选择性移除可以藉由选择性干式蚀刻、选择性湿式蚀刻或其他选择性蚀刻工艺来实现。在一些实施例中，选择性湿式蚀刻包括APM蚀刻(例如：氢氧化氨-过氧化氢-水混合物)。在一些替代实施例中，选择性移除包括硅锗氧化、接着是硅锗氧化物移除。举例来说，可以藉由臭氧清洁来提供氧化，并且接着藉由蚀刻剂(例如氨水(NH4OH))移除氧化硅锗。因为包覆层216和末端包覆层2160与牺牲层206具有相似的组成，所以它们在操作128中也被选择性地移除。如图13所示，移除末端包覆层2160形成末端沟槽252。鳍片间隔物218、内部间隔物特征242、隔离特征214、硅衬垫2100的侧壁在末端沟槽252中暴露。
参照图1、图13，方法100包括操作130，其在末端沟槽252被覆盖时，在栅极沟槽250中沉积界面层254和栅极介电层256。为了在栅极沟槽250中选择性地形成界面层254和栅极介电层256，而不是形成在端部沟槽252中，在末端沟槽252中和上方形成光阻特征253。在图14所示的示例工艺中，光阻层沉积在工件200上方，并且接着使用光刻工艺被图案化，以形成光阻特征253以保护末端沟槽252。如图15所示，接着依次沉积界面层254和栅极介电层256以围绕每一个通道构件2080。在一些实施例中，界面层254包括氧化硅并且可以作为预清洁工艺(pre-clean process)的结果而形成。示例性的预清洁工艺可以包括使用RCASC-1(氨、过氧化氢和水)及/或RCASC-2(盐酸、过氧化氢和水)。预清洁工艺氧化通道构件2080的暴露表面以形成界面层254。接着使用ALD、CVD及/或其他合适方法在界面层254上方沉积栅极介电层256。栅极介电层256可以由高k介电材料形成。如此处所使用的，高k介电材料包括具有高介电常数的介电材料，其介电常数大于热氧化硅的介电常数(～3.9)。栅极介电层256可以包括氧化铪。替代地，栅极介电层256可以包括其他高k电介质，例如二氧化钛(TiO2)、氧化铪锆(HfZrO)、五氧化二钽(Ta2O5)、硅酸铪(HfSiO4)、二氧化锆(ZrO2)、二氧化锆硅(ZrSiO2)、三氧化二镧(La2O3)、三氧化二铝(Al2O3)、一氧化锆(ZrO)、三氧化二钇(Y2O3)、钛酸锶(SrTiO3(STO))、钛酸钡(BaTiO3(BTO))、氧化钡锆(BaZrO)、氧化铪镧(HfLaO)、氧化镧硅(LaSiO)、氧化铝硅(AlSiO)、氧化铪钽(HfTaO)、氧化铪钛(HfTiO)、钛酸锶钡((Ba，Sr)TiO3(BST))、氮化硅(SiN)、其组合或其他合适材料。值得注意的是，因为在覆盖末端沟槽252的同时形成或沉积了界面层254和栅极介电层256，所以它们不形成或沉积在末端沟槽252的表面上。在形成或沉积界面层254和栅极介电层256之后，移除光阻特征253，从而暴露末端沟槽252(如图13所示)。
参照图14，沉积在鳍片切割开口213(图2D所示)上方的鳍片间隔物218和填充层220可以共同地构成设置在隔离特征214上方的隔离结构219。在隔离结构219中，填充层220设置在鳍片间隔物218的水平部分(沿着Y方向延伸)上方，并且鳍片间隔物218的垂直部分(沿着Z方向延伸)沿着填充层220的侧壁延伸。
参照图1和图15，方法100包括操作133，其沉积栅极电极层261。在暴露末端沟槽252的情况下，在栅极沟槽250和末端沟槽252中沉积栅极电极层261。栅极电极层261可以是包括至少一个功函数层258和金属填充层260的多层结构。举例来说，至少一个功函数层258可以包括包括氮化钛(TiN)、钛铝(TiAl)、氮化钛铝(TiAlN)、氮化钽(TaN)、钽铝(TaAl)、氮化钽铝(TaAlN)、碳化钽铝(TaAlC)、氮碳化钽(TaCN)或碳化钽(TaC)。金属填充层260可以包括铝(Al)、钨(W)、镍(Ni)、钛(Ti)、钌(Ru)、钴(Co)、铂(Pt)、氮化钽硅(TaSiN)、铜(Cu)、其他难熔金属(refractory metal)或其他合适金属材料或其组合。在各种实施例中，可以藉由ALD，PVD，CVD，电子束蒸镀或其他合适工艺来形成栅极电极层261。在各种实施例中，可以执行平坦化工艺(例如CMP工艺)以移除多余的材料以提供栅极结构的大抵平坦的顶表面。
参照图15，在操作130和132中的操作形成栅极结构270以围绕在通道区212C中的通道构件2080和与相邻的源极/漏极特征245接触的栅极延伸结构280。在图15所示的一些实施例中，每一个栅极结构270包括界面层254、栅极介电层256、至少一个功函数层258和金属填充层260。每一个栅极结构270围绕通道构件2080。栅极延伸结构280仅包括至少一个功函数层258和金属填充层260，并且被允许通过直接接触电性耦接至相邻的源极/漏极特征245。栅极延伸结构280设置在相邻的源极/漏极特征245和隔离结构219之间。栅极延伸结构280还直接接触与相邻的源极/漏极特征245接触的内部间隔物特征242。在这方面，栅极延伸结构280的多个部分设置在内部间隔物特征242和鳍片间隔物218的垂直部分之间。因为在沉积金属填充层260之前沉积了至少一个功函数层258，所以至少一个功函数层258接触源极/漏极特征245的外层246、内部间隔物特征242以及鳍片间隔物218的垂直部分、至少一个栅极间隔物234以及填充层220，而金属填充层260与它们间隔。在一些实施例中，栅极延伸结构280的至少一个功函数层258与源极/漏极特征245的内层248间隔。
栅极延伸结构280可以是沿着X方向与栅极延伸结构280对准的连接栅极结构的延伸。连接栅极结构包括界面层(如界面层254)、栅极介电层(如栅极介电层256)、至少一个功函数层258和金属填充层260。由于光阻特征253的实施，仅连接栅极结构的至少一个功函数层258和金属填充层260继续进入末端沟槽252中以形成栅极延伸结构280。换句话说，栅极延伸结构280与连接栅极结构是一体的，并且允许连接栅极结构电性耦接至源极/漏极特征245。
参照图16，在操作132中的操作结束时，可以执行进一步的工艺以完成半导体装置200的制造。这样进一步的工艺可以包括沉积栅极覆盖层262、形成栅极自我对准接点(self-aligned-contact；SAC)介电层264、形成硅化物层266以及形成源极/漏极接点268。在一些实施例中，栅极覆盖层262可以包括镍(Ni)、钛(Ti)或钴(Co)。栅极SAC介电层264可以包括氮化硅、氮氧化硅、氮碳氧化硅或氮碳化硅。硅化物层266可以包括硅化钛(TiSi)、氮硅化钛(TiSiN)、硅化钽(TaSi)、硅化钨(WSi)、硅化钴(CoSi)或硅化镍(NiSi)。源极/漏极接点268可以包括阻挡层和金属插塞(metal plug)。阻挡层可以包括氮化钛、氮化钽、氮化钴、氮化镍或其他金属氮化物，并且金属插塞可以包括铝(Al)、钨(W)、镍(Ni)、钛(Ti)、钌(Ru)、钴(Co)、铂(Pt)或铜(Cu)。
藉由使用栅极延伸结构280电性耦接至图15或图16所示的源极/漏极特征245，本公开的实施例可以应用于将一个晶体管的栅极结构连接至另一个晶体管的源极/漏极特征。下面结合图17、图18和图19描述这种应用的示例。
在图17中示出了示例的SRAM单元300。SRAM单元300包括第一传输栅晶体管(PG1)305和第二传输栅晶体管(PG2)306、第一上拉晶体管(PU1)303和第二上拉晶体管(PU2)304以及第一下拉晶体管(PD1)301和第二下拉晶体管(PD2)302。在SRAM单元300中，传输栅晶体管、上拉晶体管和下拉晶体管中的每一者可以是多栅极晶体管，例如MBC晶体管。第一传输栅晶体管(PG1)305和第二传输栅晶体管(PG2)306的栅极电性耦接至字元线(word line；WL)，字元线(WL)确定是否选择/激活(activate)了SRAM单元300。在SRAM单元300中，存储器位元由第一上拉晶体管(PU1)303、第二上拉晶体管(PU2)304、第一下拉晶体管(PD1)301和第二下拉晶体管(PD2)302形成，以储存一位元的数据。该位元的互补值(complementaryvalue)储存在第一储存节点QB和第二储存节点Q中。可以通过位元线(Bit-line；BL)和位元线棒(Bit-Line Bar；BLB)将储存的位元写入SRAM单元300或从SRAM单元300读取。在这种布置中，BL和BLB可以携带互补的位元线信号。SRAM单元300通过具有正电源电压(Vdd)的电压汇流排(voltage bus)供电，并且还连接至以在接地电位(Vss)的接地电位汇流排。SRAM单元300包括六(6)个晶体管，并且可以被称为6T SRAM单元。
SRAM单元300包括由第一上拉(PU1)晶体管303和第一下拉晶体管(PDl)301形成的第一反相器308，以及由第二上拉晶体管(PU2)304和第二下拉晶体管(PD2)302形成的第二反相器310。第一反相器308和第二反相器310耦接在正电源电压(Vdd)和接地电位(Vss)之间。如图17所示，第一反相器308和第二反相器310交叉耦合。意即，第一反相器308的输入耦接至第二反相器310的输出。同样地，第二反相器310的输入耦接至第一反相器308的输出。第一反相器308的输出是第一储存节点QB。同样地，第二反相器310的输出是第二储存节点Q。在正常操作模式下，第一储存节点QB在与第二储存节点Q相反的逻辑状态。藉由采用两个交叉耦合的反相器，SRAM单元300可以使用锁存结构(latched structure)来保持数据，使得只要通过Vdd来供电，在不施加刷新周期(refresh cycle)的情况下，所储存的数据就不会丢失。
参照图18，可以使用布局400来实现SRAM单元300。在布局400中，第二上拉晶体管(PU2)304和第二下拉晶体管(PD2)302共享第一栅极结构402。第一上拉晶体管(PU1)303和第一下拉晶体管(PD1)301共享第二栅极结构404。为了使SRAM单元300正常工作，第一上拉晶体管(PU1)303的第一漏极406电性耦接至第一栅极结构402，并且第二上拉晶体管(PU2)304的第二漏极408电性耦接至第二栅极结构404。常规地，可以在第一漏极406和第一栅极结构402上方形成对接接点以将其连接，并且可以在第二漏极408和第二栅极结构404上方形成对接接点以将其连接。当实现本公开的实施例，例如图15和图16所示的实施例时，不需要这样的对接接点。如图18所示，第一栅极结构402可以具有第一栅极延伸结构410。第一栅极延伸结构410和第一栅极结构402共享相同的功函数层和金属填充层，但是第一栅极延伸结构410不包括任何界面层或栅极介电层。如此一来，第一栅极延伸结构410直接接触构成第一漏极406的源极/漏极特征。相似地，第二栅极结构404可以具有第二栅极延伸结构420。第二栅极延伸结构420和第二栅极结构404共享相同的功函数层和金属填充层，但是第二栅极延伸结构420不包括任何界面层或栅极介电层。如此一来，第二栅极延伸结构420直接接触构成第二漏极408的源极/漏极特征。
在一些实施例中，第一上拉晶体管(PU1)303和第二上拉晶体管(PU2)304是形成在N阱10中的P型MBC晶体管；第一下拉晶体管(PD1)301和第一传输栅晶体管(PG1)305是形成在第一P阱20中的N型MBC晶体管；以及第二下拉晶体管(PD2)302和第二传输栅晶体管(PG2)306是形成在第二P阱22中的N型MBC晶体管。N阱10设置在第一P阱20和第二P阱22之间。在其他实施例中，布局400中的所有晶体管都是形成在一个P型阱中的N型MBC晶体管。
现在参照图19。可以在布局400中的特征上方形成第一金属线层，以将不同的节点电性连接至字元线(WL)、正电源电压(Vdd)、接地电位(Vss)、位元线(BL)和位元线棒(BLB)。举例来说，形成电源轨403以将第一上拉晶体管(PU1)303和第二上拉晶体管(PU2)304的源极耦接至正电源电压(Vdd)。由于使用了第一栅极延伸结构410和第二栅极延伸结构420，因此电源轨430不会碰到对接接点。因此，电源轨430可以在第一漏极406和第二漏极408上方延伸。电源轨403的增加的宽度可以改善在布局400中实现的SRAM单元300的效能。
在一个示例性方面，本公开针对一种半导体装置。半导体装置包括栅极延伸结构、第一源极/漏极特征和第二源极/漏极特征、沿着一个方向在第一源极/漏极特征和第二源极/漏极特征之间延伸的多个通道构件的垂直堆叠以及围绕通道构件的垂直堆叠的每一者的栅极结构。栅极延伸结构直接接触第一源极/漏极特征。
在一些实施例中，栅极延伸结构沿着该方向部分地延伸到第一源极/漏极特征中。在一些实施例中，半导体装置可进一步包括设置在第一源极/漏极特征的多个表面上的多个内部间隔物特征。在一些实施例中，栅极延伸结构直接接触内部间隔物特征。在一些实施例中，第一源极/漏极特征包括内层和外层，栅极延伸结构直接接触外层，并且栅极延伸结构藉由外层和内部间隔物特征与内层间隔。在一些情况下，半导体装置可以进一步包括沿着栅极延伸结构的侧壁延伸的隔离结构。隔离结构包括鳍片间隔物层和设置在鳍片间隔物层上方的介电特征，并且鳍片间隔物层的一部分沿着介电特征的侧壁延伸。在一些实施例中，栅极延伸结构设置在第一源极/漏极特征与隔离结构之间。在一些实施例中，鳍片间隔物层包括氮化硅、氮氧化硅、氮碳氧化硅或氮碳化硅，并且介电特征包括氧化硅。在一些实施例中，栅极延伸结构接触鳍片间隔物层，并且栅极延伸结构与介电特征间隔。
在另一个示例性方面，本公开针对一种静态随机存取存储器(SRAM)单元。静态随机存取存储器单元包括耦接在一起以形成第一反相器的第一上拉多桥通道(MBC)晶体管和第一下拉多桥通道晶体管、耦接在一起以形成第二反相器的第二上拉多桥通道晶体管和第二下拉多桥通道晶体管、耦接至第一反相器的输出和第二反相器的输入的第一传输栅多桥通道晶体管以及耦接至第二反相器的输出和第一反相器的输入的第二传输栅多桥通道晶体管。第一下拉多桥通道晶体管的第一栅极电极直接接触第二上拉多桥通道晶体管的第一源极/漏极特征。第二下拉多桥通道晶体管的第二栅极电极直接接触第一上拉多桥通道晶体管的第二源极/漏极特征。
在一些实施例中，第一下拉多桥通道晶体管的第一栅极电极部分地延伸到第二上拉多桥通道晶体管的第一源极/漏极特征中。在一些实施例中，第二上拉多桥通道晶体管还包括多个内部间隔物特征，内部间隔物特征设置在第二上拉多桥通道晶体管的第一源极/漏极特征的多个表面上。在一些实施例中，第一下拉多桥通道晶体管的第一栅极电极直接接触内部间隔物特征。在一些情况下，第二上拉多桥通道晶体管的第一源极/漏极特征包括内层和外层，第一下拉多桥通道晶体管的第一栅极电极直接接触外层，并且第一下拉多桥通道晶体管的第一栅极电极藉由外层和内部间隔物特征与内层间隔。在一些实施例中，静态随机存取存储器单元可以进一步包括沿着第一栅极电极的侧壁延伸的隔离结构。第一栅极电极设置在第一源极/漏极特征和隔离结构之间。
在又一个示例性方面，本公开针对一种半导体装置的制造方法。半导体装置的制造方法包括接收工件，工件包括沿着第一方向纵向延伸的鳍状结构。鳍状结构在末端表面纵向终止，并且包括基部和在基部上方的堆叠部，并且堆叠部包括多个通道层，通道层与多个牺牲层交错设置。半导体装置的制造方法进一步包括形成沿着基部和末端表面的下部的多个侧壁延伸的隔离特征、在堆叠部上方沉积包覆层，其中包覆层包括沿着末端表面的上部延伸的端部、在包覆层和隔离特征上方沉积鳍片间隔物层、在沉积鳍片间隔物层之后，在工件上方沉积介电层、使鳍状结构的源极/漏极区凹陷，以形成源极/漏极凹陷、在源极/漏极凹陷中沉积源极/漏极特征、选择性地移除包覆层的端部，以通过末端表面的上部暴露源极/漏极特征以及在末端表面的上部上方沉积栅极电极层，以直接接触源极/漏极特征。
在一些实施例中，包覆层包括硅锗，片间隔物层包括氮化硅、氮氧化硅、氮碳氧化硅或氮碳化硅，并且沉积介电层的操作包括使用流动式化学气相沉积(FCVD)来沉积氧化硅层。在一些实施例中，半导体装置的制造方法可以进一步包括在沉积介电层之后，平坦化工件以暴露包覆层的端部的顶表面、在覆盖层的端部的顶表面上方沉积第一冗余栅极堆叠以及在鳍状结构的通道区上方沉积第二冗余栅极堆叠，通道区与源极/漏极区相邻。在一些实施例中，半导体装置的制造方法可以进一步包括使暴露在源极/漏极凹陷中的牺牲层选择性地和部分地凹陷，以形成多个内部间隔物凹陷、在内部间隔物凹陷中形成多个内部间隔物特征、移除第一冗余栅极堆叠和第二冗余栅极堆叠，以个别形成末端构槽和栅极沟槽以及选择性地移除暴露在末端沟槽和栅极沟槽中的牺牲层。在一些情况下，半导体装置的制造方法可以进一步包括在选择性地移除牺牲层之后，在末端沟槽上方选择性地沉积光阻层、在选择性地沉积光阻层之后，但在沉积栅极电极层之前，在栅极沟槽中沉积界面层和栅极介电层以及在沉积界面层和栅极介电层之后，移除光阻层。
前述内文概述了许多实施例的特征，使本技术领域中普通技术人员可以从各个方面更佳地了解本公开。本技术领域中普通技术人员应可理解，且可轻易地以本公开为基础来设计或修饰其他工艺及结构，并以此达到相同的目的及/或达到与在此介绍的实施例等相同的优点。本技术领域中普通技术人员也应了解这些相等的结构并未背离本公开的发明精神与范围。在不背离本公开的发明精神与范围的前提下，可对本公开进行各种改变、置换或修改。

Claims (1)

1.一种半导体装置，包括：
一栅极延伸结构；
一第一源极/漏极特征和一第二源极/漏极特征；
多个通道构件的一垂直堆叠，上述通道构件沿着一方向在上述第一源极/漏极特征和上述第二源极/漏极特征之间延伸；以及
一栅极结构，围绕上述通道构件的上述垂直堆叠的每一个，
其中上述栅极延伸结构直接接触上述第一源极/漏极特征。
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Publication number Priority date Publication date Assignee Title
US10910273B2 (en) * 2019-02-25 2021-02-02 International Business Machines Corporation Forming shallow trench isolation regions for nanosheet field-effect transistor devices using sacrificial epitaxial layer
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Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013048524A1 (en) * 2011-10-01 2013-04-04 Intel Corporation Source/drain contacts for non-planar transistors
US10199502B2 (en) 2014-08-15 2019-02-05 Taiwan Semiconductor Manufacturing Company, Ltd. Structure of S/D contact and method of making same
US9818872B2 (en) 2015-06-30 2017-11-14 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate device and method of fabrication thereof
US9899387B2 (en) 2015-11-16 2018-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate device and method of fabrication thereof
US10032627B2 (en) 2015-11-16 2018-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming stacked nanowire transistors
US9754840B2 (en) 2015-11-16 2017-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. Horizontal gate-all-around device having wrapped-around source and drain
US9887269B2 (en) 2015-11-30 2018-02-06 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate device and method of fabrication thereof
US9899269B2 (en) 2015-12-30 2018-02-20 Taiwan Semiconductor Manufacturing Company, Ltd Multi-gate device and method of fabrication thereof
US10217817B2 (en) * 2016-01-27 2019-02-26 International Business Machines Corporation Sacrificial layer for channel surface retention and inner spacer formation in stacked-channel FETs
US9899398B1 (en) 2016-07-26 2018-02-20 Taiwan Semiconductor Manufacturing Co., Ltd. Non-volatile memory device having nanocrystal floating gate and method of fabricating same
US9997598B2 (en) * 2016-08-08 2018-06-12 Tokyo Electron Limited Three-dimensional semiconductor device and method of fabrication
US10290546B2 (en) 2016-11-29 2019-05-14 Taiwan Semiconductor Manufacturing Co., Ltd. Threshold voltage adjustment for a gate-all-around semiconductor structure
US10475902B2 (en) 2017-05-26 2019-11-12 Taiwan Semiconductor Manufacturing Co. Ltd. Spacers for nanowire-based integrated circuit device and method of fabricating same
US10516064B1 (en) * 2018-08-14 2019-12-24 International Business Machines Corporation Multiple width nanosheet devices
US10608083B2 (en) * 2018-08-31 2020-03-31 International Business Machines Corporation Non-planar field effect transistor devices with low-resistance metallic gate structures
US10840146B1 (en) * 2019-06-17 2020-11-17 Globalfoundries Inc. Structures and SRAM bit cells with a buried cross-couple interconnect
CN114556546A (zh) * 2019-10-22 2022-05-27 应用材料公司 通过选择性外延再生长的环绕式栅极输入/输出的形成方法

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