CN113764273A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN113764273A
CN113764273A CN202010486404.1A CN202010486404A CN113764273A CN 113764273 A CN113764273 A CN 113764273A CN 202010486404 A CN202010486404 A CN 202010486404A CN 113764273 A CN113764273 A CN 113764273A
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forming
region
opening
layer
substrate
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金吉松
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor structure and a method of forming the same, comprising: providing a substrate, wherein the substrate is provided with a fin part; forming a plurality of epitaxial doping layers in the fin part; forming a diffusion region in the fin portion, wherein the diffusion region surrounds the epitaxial doping layer; forming a dielectric layer on the substrate, wherein the dielectric layer is provided with a first opening; and forming a second opening in the fin part, wherein the etching rate of the etching process to the fin part is greater than that to the diffusion region. The etching process has different etching rates on the diffusion region and the fin part, so that the etching process can be used for less etching damage to the diffusion region when the fin part is etched, the epitaxial doping layer is surrounded by the diffusion region, the etching damage to the epitaxial doping layer can be avoided when the fin part is etched, the appearance of the epitaxial doping layer is complete, and the performance of a finally formed semiconductor structure is improved.

Description

Semiconductor structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the same.
Background
With the increase of the integration level of semiconductor devices, the critical dimensions of transistors are continuously shrinking. However, with the rapid decrease of the transistor size, the thickness of the gate dielectric layer and the operating voltage cannot be changed correspondingly, so that the difficulty of suppressing the short channel effect is increased, and the channel leakage current of the transistor is increased.
The gate of a Fin-Field-Effect Transistor (FinFET) is a fork-shaped 3D structure similar to a Fin. A fin part is formed by the protrusion of the channel of the FinFET out of the surface of the substrate, and the grid electrode covers the top surface and the side wall of the fin part, so that an inversion layer is formed on each side of the channel, and the connection and disconnection of circuits can be controlled on two sides of the fin part. The design can increase the control of the gate to the channel region, thereby well inhibiting the short-channel effect of the transistor. However, the short channel effect still exists in the fin field effect transistor.
In addition, in order to further reduce the influence of the short channel effect on the semiconductor device, the channel leakage current is reduced. The technical field of semiconductors introduces a strained silicon technology, and the method of the strained silicon technology comprises the following steps: forming grooves in the fin parts on two sides of the grid structure; and forming a source drain doping layer in the groove by an epitaxial growth process.
In order to prevent the source-drain doped layers of different transistors from being connected with each other, an isolation layer needs to be formed in the fin portion, and meanwhile, in order to reduce the area of the isolation layer, the integration level of the formed semiconductor structure is improved. The prior art has introduced sdb (single Diffusion break) technology.
However, the SDB technology introduced in the prior art results in a semiconductor structure with poor performance.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which can effectively improve the performance of the finally formed semiconductor structure.
To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein the substrate is provided with a fin part, the fin part extends along a first direction, the fin part comprises a plurality of first regions and second regions positioned between the adjacent first regions, and the first regions and the second regions are arranged along the first direction; forming a plurality of epitaxial doping layers in the first region, wherein two sides of the second region are respectively adjacent to one epitaxial doping layer; forming a diffusion region in the fin portion, wherein the diffusion region surrounds the epitaxial doping layer; forming a dielectric layer on the substrate, wherein a first opening is formed in the dielectric layer on the second region, the first opening extends along a second direction, and the first direction is perpendicular to the second direction; etching the second region exposed by the first opening, and forming a second opening in the second region, wherein the etching rate of the etching process to the second region is greater than that to the diffusion region; and forming an isolation structure in the second opening.
Optionally, the isolation structure includes a third region and a fourth region located on the third region, a bottom of the fourth region is flush with a bottom of the epitaxial doped layer, in a direction parallel to the substrate surface, the third region has a first size, the fourth region has a second size, and the first size is greater than the second size.
Optionally, the sidewall of the second opening exposes the diffusion region.
Optionally, the bottom of the second opening is lower than the bottom of the epitaxial doping layer.
Optionally, the method for forming the diffusion region includes: and annealing the epitaxial doped layer to form the diffusion region.
Optionally, the parameters of the annealing treatment include: the annealing temperature is 800-1200 ℃; the annealing time is 0.5 ms-3 min.
Optionally, the diffusion region has dopant ions therein, and the dopant ions include one or more combinations of P-type ions or N-type ions.
Optionally, the concentration of the dopant ions in the diffusion region gradually decreases toward a direction away from the epitaxial doping layer.
Optionally, the process of etching the second region exposed by the first opening includes one or more combinations of an anisotropic wet etching process and an anisotropic dry etching process.
Optionally, the etching solution of the wet etching process includes an alkaline etching solution.
Optionally, the alkaline etching solution includes ammonia water or a tetramethylammonium hydroxide solution.
Optionally, before forming the epitaxial doping layer, the method further includes: and forming a first dummy gate structure and a second dummy gate structure on the substrate, wherein the first dummy gate structure crosses the first region, and the second dummy gate structure crosses the second region.
Optionally, the method for forming the epitaxial doped layer and the dielectric layer includes: etching the fin part by using the first pseudo gate structure and the second pseudo gate structure as masks, and forming a plurality of epitaxial openings in the fin part; forming the epitaxial doping layer in the epitaxial opening or the epitaxial opening and the fin part; forming an initial dielectric layer on the substrate, wherein the initial dielectric layer covers the first pseudo gate structure and the second pseudo gate structure; and carrying out planarization treatment on the initial dielectric layer until the top surfaces of the first pseudo gate structure and the second pseudo gate structure are exposed, so as to form the dielectric layer.
Optionally, the method for forming the first opening includes: and removing the second pseudo gate structure to form the first opening.
Optionally, the process of removing the second dummy gate structure includes one or more of a wet etching process and a dry etching process.
Optionally, after the forming the dielectric layer, the method further includes: removing the first dummy gate structure and the second dummy gate structure, and forming a first dummy gate opening and a second dummy gate opening in the dielectric layer; forming a first metal gate structure in the first dummy gate opening; and forming a second metal gate structure in the second dummy gate opening.
Optionally, the method for forming the first opening includes: and removing the second metal gate structure to form the first opening.
Optionally, the process of removing the second metal gate structure includes one or more of a wet etching process and a dry etching process.
Optionally, the material of the fin portion includes germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the fin portion has second ions therein, where the second ions include P-type ions or N-type ions.
Optionally, the isolation structure is further located in the first opening, and a void is provided in the isolation structure.
Optionally, the process for forming the isolation structure includes: one or more combinations of a physical vapor deposition process, a chemical vapor deposition process, and an atomic layer deposition process.
Optionally, the material of the isolation structure includes one or more of silicon nitride, germanium oxide, silicon oxynitride, silicon carbonitride, silicon oxycarbide, aluminum oxide, and aluminum nitride.
Optionally, the method further includes: and forming an isolation layer on the substrate, wherein the isolation layer covers part of the side wall of the fin part, and the top surface of the isolation layer is lower than that of the fin part.
Correspondingly, the invention also provides a semiconductor structure, which comprises: the semiconductor device comprises a substrate, a plurality of first regions and a plurality of second regions, wherein the substrate is provided with a fin part, the fin part extends along a first direction, the fin part comprises a plurality of first regions and second regions positioned between the adjacent first regions, and the first regions and the second regions are arranged along the first direction; the epitaxial doping layer is positioned in the first region, and part of the epitaxial doping layer is positioned on two sides of the second region; a diffusion region within the substrate, the diffusion region surrounding the epitaxial doping layer; a dielectric layer on the substrate, wherein a first opening is formed in the dielectric layer on the second region, the first opening extends along a second direction, and the first direction is perpendicular to the second direction; a second opening in the second region, the first opening exposing the second opening; and the isolation structure is positioned in the second opening and comprises a third region and a fourth region positioned on the third region, the bottom of the fourth region is flush with the bottom of the epitaxial doped layer, the third region has a first size in the direction parallel to the surface of the substrate, the fourth region has a second size, and the first size is larger than the second size.
Optionally, the diffusion region has dopant ions therein, and the dopant ions include one or more combinations of P-type ions or N-type ions.
Optionally, the method further includes: a first metal gate structure on the substrate, the first metal gate structure spanning the first region.
Optionally, the material of the fin portion includes germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the fin portion has second ions therein, where the second ions include P-type ions or N-type ions.
Optionally, the isolation structure is further located in the first opening, and a void is provided in the isolation structure.
Optionally, the material of the isolation structure includes one or more of silicon nitride, germanium oxide, silicon oxynitride, silicon carbonitride, silicon oxycarbide, aluminum oxide, and aluminum nitride.
Optionally, the method further includes: the isolation layer is located on the substrate and covers partial side walls of the fin portion, and the top surface of the isolation layer is lower than the top surface of the fin portion.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the forming method of the technical scheme, the isolation structure is formed in the second opening, so that the epitaxial doping layers in different device structures are prevented from being connected with each other by using the isolation structure, the isolation area is reduced, and the integration level of the formed semiconductor structure is improved.
In addition, the etching speed of the etching process to the second area is higher than that to the diffusion area. The etching process has different etching rates on the diffusion region and the second region, so that the etching process can less cause etching damage to the diffusion region when the second region is etched, the diffusion region surrounds the epitaxial doping layer, the etching damage to the epitaxial doping layer can be avoided when the second region is etched, the appearance integrity of the epitaxial doping layer is ensured, and the performance of a finally formed semiconductor structure is improved.
Further, annealing treatment is carried out on the epitaxial doped layer to form the diffusion region. Since the necessary annealing treatment is required after the formation of the epitaxial doped layer, the purpose is to actively diffuse the dopant ions in the epitaxial doped layer. The diffusion region is formed after the epitaxial doping layer is annealed, and is not required to be formed separately by extra steps, so that the diffusion region is formed through annealing, the processing steps are reduced, and the production efficiency is improved.
Further, the isolation structure is also located in the first opening, and a gap is formed in the isolation structure. The dielectric constant of the isolation structure with the gap is low, so that the capacitance between the device structures at two sides of the isolation structure can be reduced, and the performance of the finally formed semiconductor structure is improved.
In the structure formed by the technical scheme of the invention, the isolation structure is also positioned in the first opening, and a gap is formed in the isolation structure. The isolation structure is utilized to prevent epitaxial doped layers in different device structures from being connected with each other, simultaneously reduce the isolation area and improve the integration level of the formed semiconductor structure.
In addition, the dielectric constant of the isolation structure with the gap is low, so that the capacitance between the device structures on two sides of the isolation structure can be reduced, and the performance of the finally formed semiconductor structure is improved.
Drawings
FIGS. 1-4 are schematic structural diagrams of a semiconductor structure;
fig. 5 to 16 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Fig. 17 to 20 are schematic structural diagrams of steps of another embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
As mentioned in the background, the SDB technology introduced in the prior art results in a semiconductor structure with poor performance. The following detailed description will be made in conjunction with the accompanying drawings.
Referring to fig. 1 and fig. 2, fig. 2 is a schematic cross-sectional view taken along a direction a-a in fig. 1, a substrate 100 is provided, the substrate 100 has a fin 101, the fin 101 extends along a first direction X, the fin 101 includes a plurality of first regions I and at least one second region II, the second region II is located between two adjacent first regions I, and the first regions I and the second regions II are arranged along the first direction X.
Referring to fig. 3, the view directions of fig. 3 and fig. 2 are the same, a first gate structure 102 crossing the fin 101 and an epitaxial doping layer 103 in the fin 101 on two sides of the first gate structure 102 are respectively formed on the first region I, and the first gate structure 102 covers part of the sidewall and the top surface of the fin 101; forming a dielectric layer 104 on the substrate 100, wherein the dielectric layer 104 covers the sidewall of the first gate structure 102, and the dielectric layer 104 exposes the top surface of the first gate structure 102; a first opening 105 is formed in the dielectric layer 104 on the second region II, the first opening 105 extends along a second direction Y, and the first direction X is perpendicular to the second direction Y.
Referring to fig. 4, the second region II exposed by the first opening 105 is etched by a dry etching process, and a second opening (not labeled) is formed in the second region II; an isolation structure 106 is formed within the first opening 105 and the second opening.
In this embodiment, the isolation structure 106 is used to prevent the epitaxial doped layers 103 in each first region I from being connected to each other, thereby achieving an isolation effect. However, the dry etching process is adopted when the second region II exposed by the first opening 105 is etched, and since the epitaxial doped layer 103 and the second region II are made of silicon materials, even if the ion doping concentrations in the epitaxial doped layer 103 and the second region II are different, the dry etching process has no etching selectivity to the silicon materials with different ion doping concentrations, so that when the second region II is etched, the dry etching process may also cause a certain etching damage to the epitaxial doped layer 103, thereby affecting the electrical performance of the finally formed semiconductor structure.
On the basis, the invention provides a method for forming a semiconductor structure, which comprises the steps of forming a diffusion region in a substrate, wherein the diffusion region surrounds an epitaxial doping layer, and the etching rate of an etching process to the second region is higher than that to the diffusion region, so that the etching process can be ensured to have less etching damage to the diffusion region when the etching process etches the second region.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 5 to 16 are schematic structural diagrams illustrating a process of forming a semiconductor structure according to an embodiment of the invention.
Referring to fig. 5 and 6, fig. 6 is a schematic cross-sectional view taken along a direction B-B in fig. 5, providing a substrate 200, where the substrate 200 has a fin 201, the fin 201 extends along a first direction X, the fin 201 includes a plurality of first regions I and second regions II located between adjacent first regions I, and the first regions I and the second regions II are arranged along the first direction X.
In this embodiment, the method for forming the substrate 200 and the fin 201 includes: providing an initial substrate (not shown) having a mask layer (not shown) thereon, the mask layer exposing a portion of a top surface of the initial substrate; and etching the initial substrate by taking the mask layer as a mask to form the substrate 200 and the fin part 201 on the substrate 200.
In this embodiment, the substrate 200 is made of silicon; in other embodiments, the substrate may also be germanium, silicon carbide, gallium arsenide, or indium gallium.
In this embodiment, the fin 201 is made of silicon; in other embodiments, the material of the fin portion may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
The fin portion has second ions therein, and the second ions include P-type ions or N-type ions. In this embodiment, the second ions are P-type ions.
With reference to fig. 6, an isolation layer 202 is formed on the substrate 200, wherein the isolation layer 202 covers a portion of the sidewall of the fin 201, and a top surface of the isolation layer 202 is lower than a top surface of the fin 201.
In this embodiment, the method for forming the isolation layer 202 includes: forming an initial isolation layer (not shown) on the substrate 200; and etching to remove part of the initial isolation layer to form the isolation layer 202, wherein the top surface of the isolation layer 202 is lower than that of the fin 201.
The isolation layer 202 is made of an insulating material, and the insulating material comprises silicon oxide or silicon oxynitride; in this embodiment, the material of the isolation layer 202 is silicon oxide.
In this embodiment, after forming the isolation layer 202, the method further includes: and forming a plurality of epitaxial doped layers in the first region I, wherein two sides of the second region II are respectively adjacent to one epitaxial doped layer. Please refer to fig. 7 to 8 for a specific forming process.
Referring to fig. 7 and 8, the view directions of fig. 8 and 6 are the same, and a first dummy gate structure and a second dummy gate structure are formed on the substrate 200, where the first dummy gate structure crosses the first region I, and the second dummy gate structure crosses the second region II.
In this embodiment, the method for forming the first dummy gate structure includes: forming a first gate dielectric layer 203 on the isolation layer 202; forming a first dummy gate layer 204 on the first gate dielectric layer 203; and forming a first side wall 205 on the side walls of the first dummy gate layer 204 and the first gate dielectric layer 203.
In this embodiment, the first gate dielectric layer 203 is made of silicon oxide; in other embodiments, the first gate dielectric layer material may also be silicon oxynitride.
In this embodiment, the material of the first dummy gate layer 204 is polysilicon.
In this embodiment, the method for forming the second dummy gate structure includes: forming a second gate dielectric layer 206 on the isolation layer 202; forming a second dummy gate layer 207 on the second gate dielectric layer 206; and forming a second sidewall 208 on the sidewalls of the second dummy gate layer 207 and the second gate dielectric layer 203.
In this embodiment, the material of the second gate dielectric layer 206 is the same as the material of the first gate dielectric layer 203, and the material of the second dummy gate layer 207 is the same as the material of the first dummy gate layer 204.
In this embodiment, the second dummy gate layer 207 and the first dummy gate layer 204 are formed at the same time, and the first dummy gate layer 204 and the second dummy gate layer 207 are formed at the same time through a global process, so that the production efficiency can be effectively improved.
Referring to fig. 9 and 10, the fin 201 is etched by using the first dummy gate structure and the second dummy gate structure as masks, and a plurality of epitaxial openings (not labeled) are formed in the fin; the epitaxial doped layer 209 is formed within the epitaxial opening.
In this embodiment, the method for forming the epitaxial doping layer 209 in the epitaxial opening includes: forming an epitaxial layer (not labeled) within the epitaxial opening; after the epitaxial layer is formed, an ion implantation process is performed to form an ion implantation region (not shown), and the ion implantation region and the epitaxial layer jointly form the epitaxial doping layer 209. .
In other embodiments, the epitaxial doping layer may also be located within the epitaxial opening and the fin. The method for forming the epitaxial doped layer comprises the following steps: after the epitaxial opening is formed, performing ion implantation to form an ion implantation region, wherein the ion implantation region extends into the fin portion, an epitaxial layer is formed in the epitaxial opening after the ion implantation region is formed, and the ion implantation region and the epitaxial layer jointly form the epitaxial doping layer; in other embodiments, the ion implantation process may also be performed both before and after the epitaxial layer is formed.
Referring to fig. 11 and 12, a diffusion region 210 is formed in the fin 201, and the diffusion region 210 surrounds the epitaxial doping layer 209.
In this embodiment, the method for forming the diffusion region 210 includes: and annealing the epitaxial doped layer 209 to form the diffusion region 210.
Since a necessary annealing process is required after the formation of the epitaxial doping layer 209, the purpose is to actively diffuse the dopant ions in the epitaxial doping layer 209. The diffusion region 210 is formed after the epitaxial doping layer 209 is annealed, and is not separately formed by an additional step, so that the diffusion region 210 is formed by annealing, the process steps are reduced, and the production efficiency is improved.
In this embodiment, the parameters of the annealing process include: the annealing temperature is 800-1200 ℃; the annealing time is 0.5 ms-3 min.
The diffusion region 210 has dopant ions therein, and the dopant ions include one or more combinations of P-type ions or N-type ions. In the embodiment, the doping ions are N-type ions, the concentration of the doping ions in the diffusion region 210 gradually decreases towards the direction away from the epitaxial doping layer 209, and the concentration of the doping ions in the diffusion region 210 is 1E15atm/cm3～1E21atm/cm3。
In this embodiment, the doping ions in the diffusion region 210 are ions diffused after the epitaxial doping layer 209 is annealed.
In this embodiment, after forming the diffusion region 210, the method further includes: forming a dielectric layer on the substrate 200, wherein a first opening is formed in the dielectric layer on the second region II, the first opening extends along a second direction Y, and the first direction X is perpendicular to the second direction Y. Please refer to fig. 13 to 14 for a specific forming process.
Referring to fig. 13, an initial dielectric layer (not shown) is formed on the substrate 200, and the initial dielectric layer covers the first dummy gate structure and the second dummy gate structure; and performing planarization treatment on the initial dielectric layer until the top surfaces of the first dummy gate structure and the second dummy gate structure are exposed, so as to form the dielectric layer 211.
In this embodiment, the dielectric layer 211 is made of silicon oxide; in other embodiments, the material of the dielectric layer may also be a low-k dielectric material (referring to a dielectric material with a relative dielectric constant lower than 3.9) or an ultra-low-k dielectric material (referring to a dielectric material with a relative dielectric constant lower than 2.5).
Referring to fig. 14, after the dielectric layer 211 is formed, the second dummy gate structure is removed, and the first opening 212 is formed.
In this embodiment, the first opening 212 exposes a surface of the second region II.
In this embodiment, what is specifically removed is the second dummy gate layer 207 and the second gate dielectric layer 206 of the second dummy gate structure.
The process for removing the second pseudo gate structure comprises one or more of a wet etching process and a dry etching process. In this embodiment, the process of removing the second dummy gate structure adopts a wet etching process.
Referring to fig. 15, the second region II exposed by the first opening 212 is etched by an etching process, and a second opening 213 is formed in the second region II, where an etching rate of the etching process to the second region II is greater than an etching rate to the diffusion region 210.
By subsequently forming an isolation structure in the second opening 213, the isolation structure is utilized to prevent the epitaxial doped layers 209 in different device structures from being connected with each other, and simultaneously, the isolation area is also reduced, and the integration level of the formed semiconductor structure is improved.
In addition, the etching rate of the etching process to the second region II is greater than the etching rate to the diffusion region 210. Because the etching process has different etching rates to the diffusion region 210 and the second region II, the etching process can have less etching damage to the diffusion region 210 when etching the second region II, and because the diffusion region 210 surrounds the epitaxial doping layer 209, the etching damage to the epitaxial doping layer 209 can be avoided when etching the second region II, so that the complete appearance of the epitaxial doping layer 209 is ensured, and the performance of the finally formed semiconductor structure is improved.
The process for etching the second region II exposed by the first opening 212 includes one or more combinations of an anisotropic wet etching process and an anisotropic dry etching process; in this embodiment, the process of etching the second region II exposed by the first opening 212 is the wet etching process.
The etching solution of the wet etching process comprises an alkaline etching solution; the alkaline etching solution comprises ammonia water or a tetramethylammonium hydroxide solution. In this embodiment, the alkaline etching solution is ammonia.
In this embodiment, the concentration of the ammonia water may be adjusted according to the difference between the doping ion concentration and the second ion concentration, so that the final wet etching stops at the diffusion region 210 without damaging the epitaxial doping layer 209.
In the present embodiment, the sidewall of the second opening 213 exposes the diffusion region 210, and the bottom of the second opening 213 is lower than the bottom of the epitaxial doping layer 209.
Referring to fig. 16, an isolation structure 214 is formed in the second opening 213.
In this embodiment, the isolation structure 214 is further located in the first opening 212, and the isolation structure 214 has a void therein; in other embodiments, the isolation structure may also be a solid structure without voids.
The dielectric constant of the isolation structure 214 with the void is low, which can reduce the capacitance between the device structures on both sides of the isolation structure 214, thereby improving the performance of the finally formed semiconductor structure.
In the present embodiment, the isolation structure 214 includes a third region III and a fourth region II located on the third region III, a bottom of the fourth region IIII is flush with a bottom of the epitaxial doped layer 209, the third region III has a first dimension CD1 in a direction parallel to the surface of the substrate 200, the fourth region IIII has a second dimension CD2, and the first dimension CD1 is greater than the second dimension CD 2.
In the present embodiment, the process of forming the isolation structure 214 is a physical vapor deposition process; in other embodiments, the process of forming the isolation structure may also be a chemical vapor deposition process or an atomic layer deposition process.
The material of the isolation structure 214 includes one or more of silicon nitride, germanium oxide, silicon oxynitride, silicon carbonitride, silicon oxycarbide, aluminum oxide, and aluminum nitride. In this embodiment, the isolation structure 214 is made of silicon oxide.
Fig. 17 to 20 are schematic structural views illustrating a semiconductor structure forming process according to another embodiment of the present invention.
In this embodiment, a method for forming a semiconductor structure is described in the following embodiments, and the difference between this embodiment and the above embodiments is: after the dielectric layer 211 is formed (as shown in fig. 10), a first metal gate structure and a second metal gate structure are also formed, and the first opening 212 is formed by removing the second metal gate structure. The following detailed description will be made in conjunction with the accompanying drawings.
Referring to fig. 17, after the dielectric layer 211 is formed, the first dummy gate structure and the second dummy gate structure are removed, and a first dummy gate opening and a second dummy gate opening (not shown) are formed in the dielectric layer 211; forming a first metal gate structure in the first dummy gate opening; and forming a second metal gate structure in the second dummy gate opening.
In this embodiment, specifically, the first dummy gate layer 204 of the first dummy gate structure is removed, and the second dummy gate layer 207 of the second dummy gate structure is removed.
In the present embodiment, the first metal gate structure includes a first metal gate layer 215 and a first high-K dielectric layer (not shown); the second metal gate structure includes a second metal gate layer 216 and a second high-K dielectric layer (not labeled).
The material of the first metal gate layer 215 and the second metal gate layer 216 comprises a metal comprising: tungsten, aluminum, copper, titanium, silver, gold, lead, or nickel. In this embodiment, the material of the first metal gate layer 215 and the second metal gate layer 216 is tungsten.
Referring to fig. 18, the second metal gate structure is removed to form the first opening 212.
In this embodiment, the removing the second metal gate structure further includes removing the second gate dielectric layer 206.
The process for removing the second metal gate structure comprises one or more of a wet etching process and a dry etching process. In this embodiment, the process of removing the second metal gate structure adopts a wet etching process.
Referring to fig. 19, the second region II exposed by the first opening 212 is etched by an etching process, and a second opening 213 is formed in the second region II, where an etching rate of the etching process to the second region II is greater than an etching rate to the diffusion region 210.
The parameters and effects of the etching process are described with specific reference to the related description of fig. 12.
Referring to fig. 20, an isolation structure 214 is formed in the second opening 213.
The formation process, effect and material of the isolation structure 214 are described with reference to the related description of fig. 13.
Accordingly, an embodiment of the present invention further provides a semiconductor structure, please continue to refer to fig. 20, including: the semiconductor device comprises a substrate 200, wherein a fin portion 201 is arranged on the substrate 200, the fin portion 201 extends along a first direction X, the fin portion 201 comprises a plurality of first regions I and second regions II located between the adjacent first regions I, and the first regions I and the second regions II are arranged along the first direction X; the epitaxial doping layer 209 is positioned in the first region I, and part of the epitaxial doping layer 209 is positioned at two sides of the second region II; a diffusion region 210 located within the substrate 200, the diffusion region 210 surrounding the epitaxially doped layer 209; a dielectric layer 211 located on the substrate 200, wherein a first opening 212 is formed in the dielectric layer 211 located on the second region II, the first opening 212 extends along a second direction Y, and the first direction X is perpendicular to the second direction Y; a second opening 213 located in the second region II, wherein the second opening 213 is exposed by the first opening 212; an isolation structure 214 located within the second opening 213, the isolation structure 214 comprising a third region III and a fourth region II located on the third region III, a bottom of the fourth region IIII being flush with a bottom of the epitaxially doped layer 209, the third region III having a first dimension CD1 in a direction parallel to the surface of the substrate 200, the fourth region IIII having a second dimension CD2, the first dimension CD1 being greater than the second dimension CD 2.
In this embodiment, the diffusion region 210 has doped ions therein, and the doped ions are N-type ions; in other embodiments, the doping ions may also be P-type ions.
In the present embodiment, the concentration of the dopant ions in the diffusion region 210 is 1E15atm/cm3～1E21atm/cm3。
In this embodiment, the method further includes: a first metal gate structure on the substrate 200, the first metal gate structure crossing the first region I.
In this embodiment, the fin portion 201 is made of silicon, and the fin portion has second ions therein, where the second ions are P-type ions; in other embodiments, the material of the fin portion may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the dopant ions may also be N-type ions.
In the present embodiment, the isolation structure 214 is also located in the first opening 212, and the isolation structure 214 has a void therein. In other embodiments, the isolation structure may also be a solid structure without voids.
The material of the isolation structure 214 includes one or more of silicon nitride, germanium oxide, silicon oxynitride, silicon carbonitride, silicon oxycarbide, aluminum oxide, and aluminum nitride. In this embodiment, the isolation structure 214 is made of silicon nitride.
In this embodiment, the method further includes: an isolation layer 202 located on the substrate 200, wherein the isolation layer 202 covers a portion of the sidewall of the fin 201, and a top surface of the isolation layer 202 is lower than a top surface of the fin 201.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (30)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate is provided with a fin part, the fin part extends along a first direction, the fin part comprises a plurality of first regions and second regions positioned between the adjacent first regions, and the first regions and the second regions are arranged along the first direction;
forming a plurality of epitaxial doping layers in the first region, wherein two sides of the second region are respectively adjacent to one epitaxial doping layer;
forming a diffusion region in the fin portion, wherein the diffusion region surrounds the epitaxial doping layer;
forming a dielectric layer on the substrate, wherein a first opening is formed in the dielectric layer on the second region, the first opening extends along a second direction, and the first direction is perpendicular to the second direction;
etching the second area exposed by the first opening by adopting an etching process, and forming a second opening in the second area, wherein the etching rate of the etching process to the second area is greater than that to the diffusion area;
and forming an isolation structure in the second opening.
2. The method of claim 1, wherein the isolation structure comprises a third region and a fourth region located above the third region, a bottom of the fourth region being flush with a bottom of the epitaxial doped layer, the third region having a first dimension and the fourth region having a second dimension, the first dimension being greater than the second dimension, in a direction parallel to the surface of the substrate.
3. The method of claim 1, wherein sidewalls of the second opening expose the diffusion region.
4. The method of claim 1, wherein a bottom of the second opening is lower than a bottom of the epitaxially doped layer.
5. The method of forming a semiconductor structure of claim 1, wherein the method of forming the diffusion region comprises: and annealing the epitaxial doped layer to form the diffusion region.
6. The method of claim 5, wherein the parameters of the annealing process comprise: the annealing temperature is 800-1200 ℃; the annealing time is 0.5 ms-3 min.
7. The method of claim 1, wherein the diffusion region has dopant ions therein, the dopant ions comprising one or more combinations of P-type ions or N-type ions.
8. The method of claim 7, wherein a concentration of dopant ions within said diffusion region decreases in a direction away from said epitaxially doped layer.
9. The method for forming a semiconductor structure according to claim 1, wherein the process for etching the second region exposed by the first opening comprises one or more of a combination of an anisotropic wet etching process and an anisotropic dry etching process.
10. The method for forming a semiconductor structure of claim 9, wherein the etching solution of the wet etching process comprises an alkaline etching solution.
11. The method of claim 10, wherein the alkaline etching solution comprises ammonia or a tetramethylammonium hydroxide solution.
12. The method of forming a semiconductor structure of claim 1, further comprising, prior to forming the epitaxially doped layer: and forming a first dummy gate structure and a second dummy gate structure on the substrate, wherein the first dummy gate structure crosses the first region, and the second dummy gate structure crosses the second region.
13. The method of forming a semiconductor structure of claim 12, wherein the method of forming the epitaxial doping layer and the dielectric layer comprises: etching the fin part by using the first pseudo gate structure and the second pseudo gate structure as masks, and forming a plurality of epitaxial openings in the fin part; forming the epitaxial doping layer in the epitaxial opening or in the epitaxial opening and the fin part; forming an initial dielectric layer on the substrate, wherein the initial dielectric layer covers the first pseudo gate structure and the second pseudo gate structure; and carrying out planarization treatment on the initial dielectric layer until the top surfaces of the first pseudo gate structure and the second pseudo gate structure are exposed, so as to form the dielectric layer.
14. The method for forming a semiconductor structure according to claim 12, wherein the method for forming the first opening comprises: and removing the second pseudo gate structure to form the first opening.
15. The method for forming a semiconductor structure according to claim 14, wherein the process for removing the second dummy gate structure comprises one or more of a wet etching process and a dry etching process.
16. The method for forming a semiconductor structure of claim 13, further comprising, after forming the dielectric layer: removing the first dummy gate structure and the second dummy gate structure, and forming a first dummy gate opening and a second dummy gate opening in the dielectric layer; forming a first metal gate structure in the first dummy gate opening; and forming a second metal gate structure in the second dummy gate opening.
17. The method of forming a semiconductor structure of claim 16, wherein the method of forming the first opening comprises: and removing the second metal gate structure to form the first opening.
18. The method for forming a semiconductor structure of claim 17, wherein the process for removing the second metal gate structure comprises one or more of a wet etch process and a dry etch process.
19. The method of claim 1, wherein the fin comprises a material comprising silicon, germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and wherein the fin has second ions therein, the second ions comprising P-type ions or N-type ions.
20. The method of claim 1, wherein the isolation structure is further located within the first opening, the isolation structure having a void therein.
21. The method of claim 1, wherein the process of forming the isolation structure comprises: one or more combinations of a physical vapor deposition process, a chemical vapor deposition process, and an atomic layer deposition process.
22. The method of claim 1, wherein the isolation structure comprises a material selected from the group consisting of silicon nitride, germanium oxide, silicon oxynitride, silicon carbonitride, silicon oxycarbide, aluminum oxide, and aluminum nitride.
23. The method of semiconductor structure formation of claim 1, further comprising: and forming an isolation layer on the substrate, wherein the isolation layer covers part of the side wall of the fin part, and the top surface of the isolation layer is lower than that of the fin part.
24. A semiconductor structure, comprising:
the semiconductor device comprises a substrate, a plurality of first regions and a plurality of second regions, wherein the substrate is provided with a fin part, the fin part extends along a first direction, the fin part comprises a plurality of first regions and second regions positioned between the adjacent first regions, and the first regions and the second regions are arranged along the first direction;
the epitaxial doping layer is positioned in the first region, and part of the epitaxial doping layer is positioned on two sides of the second region;
a diffusion region within the substrate, the diffusion region surrounding the epitaxial doping layer;
a dielectric layer on the substrate, wherein a first opening is formed in the dielectric layer on the second region, the first opening extends along a second direction, and the first direction is perpendicular to the second direction;
a second opening in the second region, the first opening exposing the second opening;
and the isolation structure is positioned in the second opening and comprises a third region and a fourth region positioned on the third region, the bottom of the fourth region is flush with the bottom of the epitaxial doped layer, the third region has a first size in the direction parallel to the surface of the substrate, the fourth region has a second size, and the first size is larger than the second size.
25. The semiconductor structure of claim 24, wherein the diffusion region has dopant ions therein, the dopant ions comprising one or more combinations of P-type ions or N-type ions.
26. The semiconductor structure of claim 24, further comprising: a first metal gate structure on the substrate, the first metal gate structure spanning the first region.
27. The semiconductor structure of claim 24, wherein the fin comprises a material comprising silicon, germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, the fin having a second ion therein, the second ion comprising a P-type ion or an N-type ion.
28. The semiconductor structure of claim 24, wherein the isolation structure is further located within the first opening, the isolation structure having a void therein.
29. The semiconductor structure of claim 24, wherein the isolation structure comprises a material selected from the group consisting of silicon nitride, germanium oxide, silicon oxynitride, silicon carbonitride, silicon oxycarbide, aluminum oxide, and aluminum nitride.
30. The semiconductor structure of claim 24, further comprising: the isolation layer is located on the substrate and covers partial side walls of the fin portion, and the top surface of the isolation layer is lower than the top surface of the fin portion.
CN202010486404.1A 2020-06-01 2020-06-01 Semiconductor structure and forming method thereof Pending CN113764273A (en)

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