CN113746540A

CN113746540A - QSFP-based variable power consumption high-speed loop test module

Info

Publication number: CN113746540A
Application number: CN202111052089.2A
Authority: CN
Inventors: 李刚
Original assignee: Maisi Technology Shanghai Co ltd
Current assignee: Maisi Technology Shanghai Co ltd
Priority date: 2021-09-08
Filing date: 2021-09-08
Publication date: 2021-12-03

Abstract

The invention provides a QSFP-based variable power consumption high-speed loop test module, and relates to the technical field of interface test. The optical module interface is connected with the main control module; the main control module is connected with a load loop group; the optical module interface is also connected with an AC coupling loop circuit; the power consumption of the modules can be set according to requirements, so that energy is saved, different power consumption requirements can be realized by using one product, and the modules do not need to be replaced in the test process; meanwhile, each functional pin can be tested to detect whether the pin is open-circuited or short-circuited, and the result can be read and judged by an upper computer through a register to form a full-coverage test; the input voltage on the optical module interface can be detected through the main control module; and need not the high price and short-lived optic fibre, the inside design of this module has passive high-speed signal to return the ring, just can realize the test of the high-speed data signal link of switch, router through this.

Description

QSFP-based variable power consumption high-speed loop test module

Technical Field

The invention relates to the technical field of interface testing, in particular to a QSFP-based variable power consumption high-speed loop testing module.

Background

At present, the types of switches and routers are gradually increased, functions of the switches and the routers, which need to interact with a cloud server, are more and more, and in order to ensure the stability of functions of final products, a functional interface of the switches and the routers needs to be comprehensively tested in advance.

The current interface test system for switches and routers has the following problems in use:

1. at present, a high-speed loop module is used in the field of port testing of switches and routers, the rated power consumption of the high-speed loop module is high, energy waste is caused when a large number of tests are carried out, and the high-speed loop module does not accord with the current energy-saving and environment-friendly theme;

2. the rated power consumption of the high-speed loop module used in the field of port testing of switches and routers is fixed at present, so that the verification requirements of other power consumption of different levels cannot be met at one time;

3. at present, a high-speed loop module used in the field of port testing of switches and routers cannot test each functional pin of a product to be tested one by one, and judges whether the interface connector of the product to be tested is open-circuited or short-circuited in a welding way, so that the testing coverage is incomplete;

4. if the optical module interface and the optical fiber are used for testing, the price is high, the service life of the optical module interface is prolonged when the optical module interface is plugged and pulled for about 200 times, and the optical module interface needs to be scrapped, so that resources are wasted, and the cost is high.

In order to solve the above problems, how to design a variable power consumption high-speed loop test module based on a QSFP is an urgent need at present.

Disclosure of Invention

The invention aims to provide a variable power consumption high-speed loop test module based on QSFP, which solves the problems in the prior art.

The embodiment of the invention is realized by the following steps:

the embodiment of the application provides a QSFP-based variable power consumption high-speed loop test module, which comprises a main control module and an optical module interface connected with the main control module; the main control module is connected with a load loop group; the optical module interface is also connected with an AC coupling loop circuit;

the load loop group is used for connecting an interface power supply of the switch or the router and controlling the power consumption through the main control module;

the AC-coupled loopback circuit is used to form a passive high-speed signal loopback inside the optical module interface.

In some embodiments of the present invention, the main control module includes a controller U1, a filter FB1, and a resistor R4;

the 5 th pin of the controller U1 is connected with the 1 st pin of the filter FB1, the 2 nd pin of the filter FB1 and the 1 st pin and the 17 th pin of the controller U1 are both connected with a VCC end;

the 31 st pin of the controller U1 is connected with one end of the resistor R4, and the other end of the resistor R4 and the 0 th pin of the controller U1 are both connected with the GND terminal.

In some embodiments of the present invention, the optical module interface includes a connector J1, and the pin 1, the pin 4, the pin 7, the pin 13, the pin 16, the pin 19, the pin 20, the pin 23, the pin 26, the pin 32, the pin 35 and the pin 38 of the connector J1 are all connected to a GND terminal; the optical module interface further comprises a resistor R1, a resistor R2, a resistor R3 and a capacitor C13;

one ends of the resistor R1, the resistor R2 and the resistor R3 are respectively connected with the 8 th pin, the 31 th pin and the 9 th pin of the connector J1 and the 24 th pin, the 25 th pin and the 4 th pin of the controller U1; the other ends of the resistor R1, the resistor R2 and the resistor R3 are connected with a VCC end; the 9 th pin of the connector J1 and the 4 th pin of the controller U1 are also connected to one end of a capacitor C13, and the other end of the capacitor C13 is connected to the GND terminal.

In some embodiments of the present invention, the AC coupling loop circuit includes a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C8, a capacitor C9, a capacitor C10, a capacitor C11, and a capacitor C12;

two ends of the capacitor C1 are respectively connected with the 36 th pin and the 17 th pin of the connector J1;

two ends of the capacitor C2 are respectively connected with the 37 th pin and the 18 th pin of the connector J1;

two ends of the capacitor C3 are respectively connected with the No. 3 pin and the No. 22 pin of the connector J1;

two ends of the capacitor C8 are respectively connected with the No. 2 pin and the No. 21 pin of the connector J1;

two ends of the capacitor C9 are respectively connected with the 33 rd pin and the 14 th pin of the connector J1;

two ends of the capacitor C10 are respectively connected with the 34 th pin and the 15 th pin of the connector J1;

two ends of the capacitor C11 are respectively connected with the 5 th pin and the 25 th pin of the connector J1;

the two ends of the capacitor C12 are respectively connected with the 5 th pin and the 24 th pin of the connector J1.

In some embodiments of the present invention, the load loop group includes a first load circuit, a second load circuit, a third load circuit and a fourth load circuit;

the first load circuit comprises a resistor R14, a resistor R15, a resistor R16 and a field-effect transistor Q2;

one end of the resistor R14 is connected with a VCC end, and the other end is connected with the 3 rd pin of the field effect transistor Q2; the 1 st pin of the field effect transistor Q2 is respectively connected with one end of a resistor R15 and one end of a resistor R16; the other end of the resistor R15 is connected with the 26 th pin of the controller U1; the other end of the resistor R16 is connected with the No. 2 pin of the field effect transistor Q2 and connected with the GND terminal.

In some embodiments of the present invention, the second load circuit includes a resistor R6, a resistor R8, a resistor R10, a resistor R11, a resistor R12, a resistor R13, and a field-effect transistor Q1;

one ends of the resistor R6, the resistor R8, the resistor R10 and the resistor R11 are all connected with a power supply VCC _ TX, and the other ends of the resistors R6, the resistor R8, the resistor R10 and the resistor R11 are all connected with a No. 3 pin of a field effect transistor Q1; a 1 st pin of the field effect transistor Q1 is respectively connected with one ends of a resistor R12 and a resistor R13, and the other end of the resistor R12 is connected with a 28 th pin of a controller U1; the other end of the resistor R13 is connected with the No. 2 pin of the field effect transistor Q1 and is connected with the GND terminal.

In some embodiments of the present invention, the third load circuit includes a resistor R25, a resistor R27, a resistor R29, a resistor R30, and a field effect transistor Q4;

one ends of the resistor R25 and the resistor R27 are both connected with a VCC end, and the other ends are connected with the 3 rd pin of the field effect transistor Q4; the 1 st pin of the field effect transistor Q4 is respectively connected with one end of a resistor R29 and one end of a resistor R30; the other end of the resistor R29 is connected with the 14 th pin of the controller U1; the other end of the resistor R30 is connected with the No. 2 pin of the field effect transistor Q4 and connected with the GND terminal.

In some embodiments of the present invention, the fourth load circuit includes a resistor R17, a resistor R18, a resistor R19, a resistor R20, a resistor R21, a resistor R22, a resistor R23, a resistor R24, a resistor R26, a resistor R28, and a fet Q3;

one ends of the resistor R17, the resistor R18, the resistor R19 and the resistor R20 are all connected with a power supply VCC _ TX; one ends of the resistor R21 and the resistor R22 are connected with a VCC end; one ends of the resistor R23 and the resistor R24 are both connected with a power supply VCC _ RX; the other ends of the resistor R17, the resistor R18, the resistor R19, the resistor R20, the resistor R21, the resistor R22, the resistor R23 and the resistor R24 are connected with the 3 rd pin of the field effect transistor Q3; the 1 st pin of the field effect transistor Q3 is respectively connected with one ends of a resistor R26 and a resistor R28, and the other end of the resistor R26 is connected with the 32 nd pin of the controller U1; the other end of the resistor R28 is connected with the No. 2 pin of the field effect transistor Q3 and connected with the GND terminal.

In some embodiments of the present invention, the above further includes a prompt circuit, and the prompt circuit includes a light emitting diode D1, a light emitting diode D2, a resistor R31, and a resistor R32;

one ends of the light emitting diode D1 and the light emitting diode D2 are both connected with a VCC end, the other ends of the light emitting diode D1 and the light emitting diode D2 are respectively connected with one ends of a resistor R31 and a resistor R32, and the other end of the resistor R31 is connected with a 27 th pin of the controller U1; the other end of the resistor R32 is connected to pin 9 of the controller U1.

In some embodiments of the present invention, the above further includes a fixed load circuit, and the fixed load circuit includes a resistor R5, a resistor R7, and a resistor R9;

one ends of the resistor R5, the resistor R7 and the resistor R9 are all connected with VCC _ RX, and the other ends of the resistor R5, the resistor R7 and the resistor R9 are connected with a GND end.

Compared with the prior art, the embodiment of the invention has at least the following advantages or beneficial effects: through the arranged main control module and the load loop group, the power consumption, the demand and the set quantity of the module can be respectively set through the to-be-tested setting according to the customer demands, namely different power consumption demands of customers are met, unnecessary waste is saved, and energy is saved; each functional pin of the switch and the router to be detected can be tested, so that whether the switch and the router are open-circuited or short-circuited is detected, and the result can be read and judged by the upper computer through the register to form a full-coverage test;

and through the optical module interface and the AC coupling loop circuit, a passive high-speed signal loop is formed inside the optical module interface, so that the test of a high-speed data signal link of a switch and a router is achieved, and the device does not need to be connected with an external optical fiber.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.

FIG. 1 is a schematic diagram of the connection of a controller U1 according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of the connection of connector J1 in an embodiment of the present invention;

FIG. 3 is a schematic diagram of the connection of a fixed load circuit according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a first load circuit according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a second load circuit according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a third load circuit according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of a fourth load circuit according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of a connection of a hint circuit in an embodiment of the present invention;

fig. 9 is a schematic diagram of the controller U1 controlling the power consumption output according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

In the description of the present application, it should be noted that the terms "upper", "lower", "inner", "outer", and the like indicate orientations or positional relationships based on orientations or positional relationships shown in the drawings or orientations or positional relationships conventionally found in use of products of the application, and are used only for convenience in describing the present application and for simplification of description, but do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present application.

In the description of the present application, it is also to be noted that, unless otherwise explicitly specified or limited, the terms "disposed" and "connected" are to be interpreted broadly, e.g., as being either fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.

Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and the individual features of the embodiments can be combined with one another without conflict.

Examples

Referring to fig. 1-9, fig. 1 is a schematic connection diagram of a controller U1 according to an embodiment of the present invention; FIG. 2 is a schematic diagram of the connection of connector J1 in an embodiment of the present invention; FIG. 3 is a schematic diagram of the connection of a fixed load circuit according to an embodiment of the present invention; FIG. 4 is a schematic diagram of a first load circuit according to an embodiment of the present invention; FIG. 5 is a schematic diagram of a second load circuit according to an embodiment of the present invention; FIG. 6 is a schematic diagram of a third load circuit according to an embodiment of the present invention; FIG. 7 is a schematic diagram of a fourth load circuit according to an embodiment of the present invention; FIG. 8 is a schematic diagram of a connection of a hint circuit in an embodiment of the present invention; fig. 9 is a schematic diagram of the controller U1 controlling the power consumption output according to an embodiment of the present invention.

the load loop group is used for connecting the interfaces of the switch or the router and controlling the load loop group through the main control module;

The controller is a micro programmable controller, and can realize communication and interface control with a product to be tested through a software programming method, and control of power consumption grading setting, voltage detection, temperature detection and a status indicator lamp in the controller.

As shown in fig. 9, the whole module is designed with four power consumption load circuits, that is, a load loop group, and the product to be tested sends a command to the programmable controller through the communication link to control the on/off of the four power consumption load circuits by controlling 4 control signals, so as to implement each required power consumption level.

The design of the whole module is that a programmable controller is added on the basis of the basic functions of the existing test module in the current market, and the detection of input and output signals is realized through software programming:

for the input signal, the register value is used internally to mark the input signal (reset signal, high and low power consumption control signal, module enable signal), so that the tested product can read the marked value through the communication link to judge whether the signal is open-circuited or short-circuited.

For the output signal (interrupt signal), the tested product controls the interrupt signal output of the designed product to be high or low through the communication link, and the tested product end detects whether the interrupt signal is matched with the expected level to judge whether the signal is open-circuited or short-circuited.

By the two methods, each functional pin can be tested, whether the pin is open-circuited or short-circuited is detected, and the result can be read and judged by the upper computer through the register to form a full-coverage test.

The high-speed differential signal of the tested product is processed by the AC coupling loop-back circuit and then sent to the output interface by the module design, so that the passive high-speed signal loop-back is realized.

Thus, the device has the following advantages:

1. other products on the market at present have fixed power consumption and higher rated power consumption, and the controller designed in the product can set the power consumption of the module according to the requirements, the number of the requirements is large, the number of the settings is large, the energy is saved, different power consumption requirements can be realized by one product, and the module does not need to be replaced in the test process.

2. Other products in the market can not respectively test each functional pin one by one at present, and whether the welding of an interface connector of a product to be tested is open or short-circuited is judged, so that the test coverage is incomplete; and each functional pin of the switch and the router which need to be detected can be tested, so that whether the switch and the router are open-circuited or not is detected, and the result can be read and judged by the upper computer through the register, and a full coverage test is formed.

3. Optical fiber is needed in the current market for testing the interfaces of the optical modules, so that the price is high, the service life is short, a passive high-speed signal loop is formed in the module, and the test of high-speed data signal links of a switch and a router can be realized only by the module.

In this embodiment, the main control module includes a controller U1, a filter FB1, and a resistor R4;

as shown in fig. 1, the 5 th pin of the controller U1 is connected to the 1 st pin of the filter FB1, the 2 nd pin of the filter FB1 and the 1 st and 17 th pins of the controller U1 are connected to the VCC terminal;

Pins

6, 7 and 8 of the controller U1 are respectively connected to three input voltages of the optical module interface.

In this embodiment, the optical module interface includes a connector J1, and the 1 st pin, the 4 th pin, the 7 th pin, the 13 th pin, the 16 th pin, the 19 th pin, the 20 th pin, the 23 rd pin, the 26 th pin, the 32 th pin, the 35 th pin and the 38 th pin of the connector J1 are all connected to a GND terminal; the optical module interface further comprises a resistor R1, a resistor R2, a resistor R3 and a capacitor C13;

as shown in fig. 2, one ends of the resistor R1, the resistor R2 and the resistor R3 are connected to the 8 th pin, the 31 th pin and the 9 th pin of the connector J1 and the 24 th pin, the 25 th pin and the 4 th pin of the controller U1, respectively; the other ends of the resistor R1, the resistor R2 and the resistor R3 are connected with a VCC end; the 9 th pin of the connector J1 and the 4 th pin of the controller U1 are also connected to one end of a capacitor C13, and the other end of the capacitor C13 is connected to the GND terminal.

In this embodiment, the AC coupling loop circuit includes a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C8, a capacitor C9, a capacitor C10, a capacitor C11, and a capacitor C12;

as shown in fig. 2, two ends of the capacitor C1 are respectively connected with the 36 th pin and the 17 th pin of the connector J1; two ends of the capacitor C2 are respectively connected with the 37 th pin and the 18 th pin of the connector J1; two ends of the capacitor C3 are respectively connected with the No. 3 pin and the No. 22 pin of the connector J1; two ends of the capacitor C8 are respectively connected with the No. 2 pin and the No. 21 pin of the connector J1; two ends of the capacitor C9 are respectively connected with the 33 rd pin and the 14 th pin of the connector J1; two ends of the capacitor C10 are respectively connected with the 34 th pin and the 15 th pin of the connector J1; two ends of the capacitor C11 are respectively connected with the 5 th pin and the 25 th pin of the connector J1; the two ends of the capacitor C12 are respectively connected with the 5 th pin and the 24 th pin of the connector J1.

In this embodiment, the load circuit group includes a first load circuit, a second load circuit, a third load circuit, and a fourth load circuit;

as shown in fig. 4, one end of the resistor R14 is connected to the VCC terminal, and the other end is connected to the 3 rd pin of the fet Q2; the 1 st pin of the field effect transistor Q2 is respectively connected with one end of a resistor R15 and one end of a resistor R16; the other end of the resistor R15 is connected with the 26 th pin of the controller U1; the other end of the resistor R16 is connected with the No. 2 pin of the field effect transistor Q2 and connected with the GND terminal.

In this embodiment, the second load circuit includes a resistor R6, a resistor R8, a resistor R10, a resistor R11, a resistor R12, a resistor R13, and a field-effect transistor Q1;

as shown in fig. 5, one end of each of the resistor R6, the resistor R8, the resistor R10 and the resistor R11 is connected to the power source VCC _ TX, and the other end is connected to the 3 rd pin of the fet Q1; a 1 st pin of the field effect transistor Q1 is respectively connected with one ends of a resistor R12 and a resistor R13, and the other end of the resistor R12 is connected with a 28 th pin of a controller U1; the other end of the resistor R13 is connected with the No. 2 pin of the field effect transistor Q1 and is connected with the GND terminal.

In this embodiment, the third load circuit includes a resistor R25, a resistor R27, a resistor R29, a resistor R30, and a field-effect transistor Q4;

as shown in fig. 6, one end of each of the resistor R25 and the resistor R27 is connected to the VCC terminal, and the other end is connected to the 3 rd pin of the fet Q4; the 1 st pin of the field effect transistor Q4 is respectively connected with one end of a resistor R29 and one end of a resistor R30; the other end of the resistor R29 is connected with the 14 th pin of the controller U1; the other end of the resistor R30 is connected with the No. 2 pin of the field effect transistor Q4 and connected with the GND terminal.

In this embodiment, the fourth load circuit includes a resistor R17, a resistor R18, a resistor R19, a resistor R20, a resistor R21, a resistor R22, a resistor R23, a resistor R24, a resistor R26, a resistor R28, and a field-effect transistor Q3;

as shown in fig. 7, one end of each of the resistor R17, the resistor R18, the resistor R19, and the resistor R20 is connected to VCC _ TX; one ends of the resistor R21 and the resistor R22 are connected with a VCC end; one ends of the resistor R23 and the resistor R24 are connected with VCC _ RX; the other ends of the resistor R17, the resistor R18, the resistor R19, the resistor R20, the resistor R21, the resistor R22, the resistor R23 and the resistor R24 are connected with the 3 rd pin of the field effect transistor Q3; the 1 st pin of the field effect transistor Q3 is respectively connected with one ends of a resistor R26 and a resistor R28, and the other end of the resistor R26 is connected with the 32 nd pin of the controller U1; the other end of the resistor R28 is connected with the No. 2 pin of the field effect transistor Q3 and connected with the GND terminal.

In this embodiment, the above further includes a prompt circuit, where the prompt circuit includes a light emitting diode D1, a light emitting diode D2, a resistor R31, and a resistor R32;

as shown in fig. 8, one end of each of the light emitting diodes D1 and D2 is connected to the VCC terminal, the other end of each of the light emitting diodes D1 and D2 is connected to one end of the resistor R31 and one end of the resistor R32, and the other end of the resistor R31 is connected to the 27 th pin of the controller U1; the other end of the resistor R32 is connected to pin 9 of the controller U1.

In this embodiment, the above further includes a fixed load circuit, and the fixed load circuit includes a resistor R5, a resistor R7, and a resistor R9;

as shown in fig. 3, one end of each of the resistor R5, the resistor R7, and the resistor R9 is connected to the 7 th pin of the controller U1, and the other end of each of the resistor R5, the resistor R7, and the resistor R9 is connected to the GND terminal.

In this embodiment, the method further includes the step that the main control module detects the input voltage of the optical module interface, the three voltages of the optical module interface are connected to

pins

6, 7 and 8 of the U1, the sizes of the three voltages of the optical module interface are obtained based on a software algorithm by using an ADC function inside the U1, and the obtained voltages are recorded in a register inside the U1.

The register is also a Memory, and the Memory may be, but not limited to, a Random Access Memory (RAM), a Read Only Memory (ROM), a Programmable Read-Only Memory (PROM), an Erasable Read-Only Memory (EPROM), an electrically Erasable Read-Only Memory (EEPROM), and the like.

The controller is also a processor, which may be an integrated circuit chip having signal processing capabilities. The Processor may be a general-purpose Processor including a Central Processing Unit (CPU), a Network Processor (NP), etc.; but also Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components.

It will be appreciated that the configurations shown in fig. 1-7 are merely illustrative and may include more or fewer components than shown in fig. 1-7 or have different configurations than shown in fig. 1-7. The components shown in fig. 1-7 may be implemented in hardware, software, or a combination thereof.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The apparatus embodiments described above are merely illustrative, and for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

In addition, functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

It will be evident to those skilled in the art that the present application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Claims

1. A QSFP-based variable power consumption high-speed loop test module is characterized by comprising a main control module and an optical module interface connected with the main control module; the main control module is connected with a load loop group; the optical module interface is also connected with an AC coupling loop circuit;

the load loop group is used for connecting an interface of a switch or a router and controlling the load loop group through a main control module;

2. The QSFP-based variable power consumption high speed loopback test module according to claim 1, wherein the master control module comprises a controller U1, a filter FB1 and a resistor R4;

the 5 th pin of the controller U1 is connected with the 1 st pin of the filter FB1, and the 2 nd pin of the filter FB1 and the 1 st pin and the 17 th pin of the controller U1 are both connected with a VCC end;

the 31 st pin of the controller U1 is connected with one end of a resistor R4, and the other end of the resistor R4 and the 0 th pin of the controller U1 are both connected with a GND terminal.

3. The QSFP-based variable power consumption high speed loopback test module according to claim 2, wherein the optical module interface comprises a connector J1, and the 1 st pin, the 4 th pin, the 7 th pin, the 13 th pin, the 16 th pin, the 19 th pin, the 20 th pin, the 23 rd pin, the 26 th pin, the 32 nd pin, the 35 th pin and the 38 th pin of the connector J1 are all connected to a GND terminal; the light module interface further comprises a resistor R1, a resistor R2, a resistor R3 and a capacitor C13;

one ends of the resistor R1, the resistor R2 and the resistor R3 are respectively connected with the 8 th pin, the 31 th pin and the 9 th pin of the connector J1 and the 24 th pin, the 25 th pin and the 4 th pin of the controller U1; the other ends of the resistor R1, the resistor R2 and the resistor R3 are connected with a VCC end; the 9 th pin of the connector J1 and the 4 th pin of the controller U1 are also connected with one end of a capacitor C13, and the other end of the capacitor C13 is connected with a GND terminal.

4. The QSFP-based variable power high speed loopback test module according to claim 1, wherein the AC-coupled loopback circuit comprises a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C8, a capacitor C9, a capacitor C10, a capacitor C11 and a capacitor C12;

two ends of the capacitor C12 are respectively connected with the 5 th pin and the 24 th pin of the connector J1.

5. The QSFP-based variable power consumption high speed loopback test module according to claim 1, wherein the load loop group comprises a first load circuit, a second load circuit, a third load circuit and a fourth load circuit;

one end of the resistor R14 is connected with a VCC end, and the other end of the resistor R14 is connected with the 3 rd pin of the field effect transistor Q2; the 1 st pin of the field effect transistor Q2 is respectively connected with one end of a resistor R15 and one end of a resistor R16; the other end of the resistor R15 is connected with the 26 th pin of the controller U1; the other end of the resistor R16 is connected with the No. 2 pin of the field effect transistor Q2 and is connected with a GND end.

6. The QSFP-based variable power consumption high-speed loopback test module according to claim 5, wherein the second load circuit comprises a resistor R6, a resistor R8, a resistor R10, a resistor R11, a resistor R12, a resistor R13 and a field effect transistor Q1;

one ends of the resistor R6, the resistor R8, the resistor R10 and the resistor R11 are all connected with VCC _ TX, and the other ends of the resistors R6, the resistor R8, the resistor R10 and the resistor R11 are all connected with the 3 rd pin of the field effect transistor Q1; the 1 st pin of the field effect transistor Q1 is respectively connected with one ends of a resistor R12 and a resistor R13, and the other end of the resistor R12 is connected with the 28 th pin of a controller U1; the other end of the resistor R13 is connected with the No. 2 pin of the field effect transistor Q1 and is connected with a GND end.

7. The QSFP-based variable power consumption high-speed loopback test module according to claim 6, wherein the third load circuit comprises a resistor R25, a resistor R27, a resistor R29, a resistor R30 and a field effect transistor Q4;

one ends of the resistor R25 and the resistor R27 are both connected with a VCC end, and the other ends of the resistors R25 and the resistor R27 are connected with the 3 rd pin of the field effect transistor Q4; the 1 st pin of the field effect transistor Q4 is respectively connected with one end of a resistor R29 and one end of a resistor R30; the other end of the resistor R29 is connected with the 14 th pin of the controller U1; the other end of the resistor R30 is connected with the No. 2 pin of the field effect transistor Q4 and is connected with a GND end.

8. The QSFP-based variable power consumption high-speed loopback test module according to claim 7, wherein the fourth load circuit comprises a resistor R17, a resistor R18, a resistor R19, a resistor R20, a resistor R21, a resistor R22, a resistor R23, a resistor R24, a resistor R26, a resistor R28 and a field effect transistor Q3;

one ends of the resistor R17, the resistor R18, the resistor R19 and the resistor R20 are all connected with VCC _ TX; one ends of the resistor R21 and the resistor R22 are both connected with a VCC end; one ends of the resistor R23 and the resistor R24 are both connected with VCC _ RX; the other ends of the resistor R17, the resistor R18, the resistor R19, the resistor R20, the resistor R21, the resistor R22, the resistor R23 and the resistor R24 are connected with the 3 rd pin of the field effect transistor Q3; the 1 st pin of the field effect transistor Q3 is respectively connected with one ends of a resistor R26 and a resistor R28, and the other end of the resistor R26 is connected with the 32 nd pin of a controller U1; the other end of the resistor R28 is connected with the No. 2 pin of the field effect transistor Q3 and is connected with a GND end.

9. The QSFP-based variable power consumption high-speed loopback test module according to claim 1, further comprising a prompt circuit, the prompt circuit comprising a light emitting diode D1, a light emitting diode D2, a resistor R31 and a resistor R32;

one ends of the light emitting diode D1 and the light emitting diode D2 are both connected with a VCC end, the other ends of the light emitting diode D1 and the light emitting diode D2 are respectively connected with one ends of a resistor R31 and a resistor R32, and the other end of the resistor R31 is connected with a 27 th pin of a controller U1; the other end of the resistor R32 is connected with the 9 th pin of the controller U1.

10. The QSFP-based variable power consumption high speed loopback test module according to claim 1, further comprising a fixed load circuit comprising a resistor R5, a resistor R7 and a resistor R9;