CN113745345A - Thin film transistor substrate, manufacturing method thereof and display device - Google Patents

Thin film transistor substrate, manufacturing method thereof and display device Download PDF

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Publication number
CN113745345A
CN113745345A CN202110988157.XA CN202110988157A CN113745345A CN 113745345 A CN113745345 A CN 113745345A CN 202110988157 A CN202110988157 A CN 202110988157A CN 113745345 A CN113745345 A CN 113745345A
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electrode
layer
substrate
insulating layer
active layer
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王晓春
吴卫华
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]

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Abstract

A thin film transistor substrate comprises a substrate, a first electrode, a spacing layer, an active layer, a grid insulation layer, a grid and a second electrode which are sequentially arranged in a stacking mode. The spacing layer is provided with at least one inclined plane, the active layer is arranged on the inclined plane, the grid insulating layer is arranged on the active layer, the grid electrode is arranged on the grid insulating layer, the grid insulating layer and the grid electrode are arranged on the inclined plane corresponding to the active layer, and an inclined angle is formed between the spacing layer and the substrate, so that the vertical thin film transistor effectively reduces the transverse size, and the high resolution (PPI) of pixels in a display area is improved. The invention also provides a manufacturing method of the thin film transistor substrate and a display device.

Description

Thin film transistor substrate, manufacturing method thereof and display device
Technical Field
The present invention relates to the field of display technologies, and in particular, to a thin film transistor substrate, a method for manufacturing the same, and a display device.
Background
In the field of display applications, reducing the lateral size of pixels to increase the total number of pixels per unit area in the display region is a common solution for achieving high-resolution (high PPI) display. In particular, in the current drive type display, it is necessary to employ a pixel drive circuit including at least 3T1C, which requires a plurality of types of devices to be arranged in a pixel. Specifically, an OLED (Organic Light-Emitting Diode) is a current-driven display device, the brightness of which is proportional to the current, each pixel needs to be provided with a Thin Film Transistor (TFT) for controlling the on/off of the TFT, and also serves as a provider of a driving current for the pixel to emit Light, and a charge storage capacitor is provided to provide a continuous current, and the pixels are relatively independent. Under the TFT drive, each pixel has a memory effect, can be driven continuously and is not limited by the number of scanning electrodes, so that the limit size of the display is increased, and high brightness and high resolution are easy to realize because the single pixel can be controlled. Therefore, realizing high-resolution display puts higher demands on lateral size control of the TFT.
As shown in fig. 1, which is a cross-sectional view of a prior art double gate thin film transistor (DG TFT) device. As shown in the figure, the dual gate thin film transistor 1 includes a substrate 11, a first metal layer 12, a buffer layer 13, an active layer 14, a gate insulating layer 15, a second metal layer 16, an interlayer insulating layer 17, and a source/drain electrode 18/19 disposed on the interlayer insulating layer 17. The source/drain electrodes 18/19 are respectively opened on the interlayer insulating layer 17 to electrically connect the active layer 14 and the first metal layer 12. The conventional tft 1 structure has a large lateral dimension of the pixel, which is not easy to increase the total number of pixels in a unit area of the display region, and thus high-resolution (high PPI) display cannot be achieved.
Disclosure of Invention
An object of the present invention is to provide a thin film transistor substrate, in which at least one inclined plane is pre-disposed, and a thin film transistor is disposed on the inclined plane, so as to fully utilize a vertical space of a display region, effectively reduce a lateral dimension of the thin film transistor, and achieve an improvement in a high resolution (PPI) of a pixel of the display region.
In order to achieve the above objects, the present invention provides a thin film transistor substrate including a substrate, a first electrode, a spacer layer, an active layer, a gate insulating layer, a gate electrode, and a second electrode. The spacing layer is provided with at least one inclined plane, the active layer is arranged on the inclined plane, the grid insulating layer is arranged on the active layer, the grid is arranged on the grid insulating layer, the grid insulating layer and the grid are arranged on the inclined plane corresponding to the active layer, and an inclined angle is formed between the spacing layer and the substrate.
Preferably, two sides of the active layer partially extend to the plane of the first electrode and the spacer layer along the inclined plane, a projected area of the gate insulating layer and the gate electrode on the substrate is equal to or smaller than a projected area of the active layer on the substrate, and a projected area of the first electrode on the substrate is larger than a projected area of the active layer on the substrate.
Preferably, the organic light emitting diode further comprises an interlayer insulating layer, the interlayer insulating layer is disposed on the gate, the spacer layer and the substrate, the second electrode is disposed on the active layer through the interlayer insulating layer, the first electrode is a source electrode or a drain electrode, and the second electrode is a drain electrode or a source electrode.
Preferably, the display device further comprises a passivation layer, a planarization layer, a pixel defining layer and a pixel electrode disposed on the planarization layer, wherein the pixel electrode penetrates through the planarization layer and the passivation layer to electrically connect the second electrode, and the angle of the inclination angle is 45 degrees to 80 degrees.
The invention also provides a manufacturing method of the thin film transistor substrate, which comprises the following steps:
providing a substrate;
forming a first electrode on the substrate;
forming a spacing layer on the first electrode, wherein one side of the spacing layer forms at least one inclined plane;
forming an active layer on the slope;
forming a gate insulating layer on the active layer;
forming a gate electrode on the gate insulating layer; and
and forming a second electrode on the active layer and corresponding to the plane of the spacing layer, wherein the gate insulating layer and the gate are formed on the inclined plane corresponding to the active layer, and an inclined angle is formed between the spacing layer and the substrate.
Preferably, in the step of forming the spacer layer on the first electrode, the spacer layer is an insulating layer deposited in an inorganic, organic or multilayer structure, and is deposited on the inclined plane on one side of the insulating layer in a patterned manner, a thickness of the spacer layer includes 5000 to 30000 angstroms, and an angle of the inclination angle includes 45 to 80 degrees.
Preferably, in the step of forming the gate insulating layer and the gate electrode on the inclined plane corresponding to the active layer, the gate electrode is patterned by using a mask, and then the patterned gate electrode is used as the mask to pattern and etch the gate insulating layer formed below to expose the active layer; before the step of forming the second electrode on the active layer corresponding to the plane, the method further comprises the step of carrying out whole-surface plasma treatment on the grid electrode, so that the resistance of the grid electrode is reduced, and an N + conductor layer is formed, wherein the active layer below the grid electrode insulating layer keeps the metal oxide semiconductor characteristic and is used as a thin film transistor substrate channel.
Preferably, the method further includes forming an interlayer insulating layer, a passivation layer, a planarization layer, a pixel defining layer and a pixel electrode disposed on the planarization layer, wherein the interlayer insulating layer is formed on the gate electrode, the spacer layer and the substrate, the second electrode passes through the interlayer insulating layer and is electrically connected to the active layer, the pixel electrode passes through the planarization layer and the passivation layer and is electrically connected to the second electrode, the first electrode is a source electrode or a drain electrode, and the second electrode is a drain electrode or a source electrode.
Preferably, the first electrode and the second electrode are made of molybdenum, chromium, aluminum, copper, titanium or a combination thereof, the active layer has a thickness of 100 to 1000 angstroms, the gate insulating layer has a thickness of 1000 to 3000 angstroms, the interlayer insulating layer is made of silicon oxide, silicon nitride or a combination thereof and has a thickness of 3000 to 5000 angstroms, and the passivation layer PV is made of silicon oxide, silicon nitride or a combination thereof and has a thickness of 1000 to 5000 angstroms.
Furthermore, the present invention also provides a display device, such as the thin film transistor substrate according to the above embodiments.
The invention also has the following effect that two sides of the active layer partially extend to the planes of the first electrode and the spacing layer along the inclined plane, so that the projection areas of the gate insulating layer and the gate on the substrate are equal to or smaller than the projection area of the active layer on the substrate, and the projection area of the first electrode on the substrate is larger than the projection area of the active layer on the substrate. That is, the invention sets at least one inclined plane, and sets the thin film transistor on the inclined plane, thereby fully utilizing the vertical space of the display area, effectively reducing the transverse size of the thin film transistor, and realizing the improvement of the high resolution of the pixel in the display area. Furthermore, when the height of the spacer layer is 0.42 μm to 2 μm, the length is 6.5 μm, and the tilt angle is 45 degrees to 60 degrees, the maximum high resolution can be achieved, effectively reducing the lateral dimension of the TFT by about 70%. Since the gate electrode takes advantage of the slope, the lateral dimension of the TFT of this embodiment is significantly optimized, and two fewer through holes can be formed. Therefore, the thin film transistor substrate with the vertical structure of the embodiment can effectively improve the lateral occupation ratio of the TFT, thereby improving the resolution of the pixel.
Drawings
In order to illustrate the embodiments or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the invention, and it is obvious for a person skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a cross-sectional view of a prior art double gate thin film transistor (DG TFT) device;
FIG. 2 is a schematic cross-sectional view of a thin film transistor substrate according to the present invention;
FIG. 3 is another schematic cross-sectional view of a TFT substrate according to the present invention; and
fig. 4 to 8 are schematic cross-sectional views illustrating a method for fabricating a thin film transistor substrate according to the present invention.
Detailed Description
Reference in the detailed description to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the same phrases in various places in the specification are not necessarily limited to the same embodiment, but are to be construed as independent or alternative embodiments to other embodiments. In light of the disclosure of the embodiments provided by the present invention, it should be understood by those skilled in the art that the embodiments described in the present invention can have other combinations or variations consistent with the concept of the present invention.
Fig. 2 is a schematic cross-sectional view of a thin film transistor substrate 100 according to the present invention. As shown in the figure, the present invention provides a thin film transistor substrate 100 including a substrate 110, a first electrode 120, a Spacer 130(Spacer), an active layer 140, a gate insulating layer 150(GI), a gate 160, and a second electrode 170. The first electrode 120 is disposed on the substrate 110, the spacer layer 130 is disposed on the first electrode 120, and the spacer layer 130 has at least one inclined surface 132. The active layer 140 is disposed on the inclined surface 132, the gate insulating layer 150 is disposed on the active layer 140, and the gate electrode 160 is disposed on the gate insulating layer 150. The gate insulating layer 150 and the gate electrode 160 are disposed on the inclined plane 132 corresponding to the active layer 140, and an inclined angle θ is formed between the spacer layer 130 and the substrate 110, so that a vertical Thin Film Transistor (TFT) is effectively reduced in lateral size, thereby improving a high resolution (PPI) of pixels in a display region.
In this embodiment, two sides of the active layer 140 partially extend to the plane 134 of the first electrode 120 and the spacer layer 130 along the inclined plane 132, so that the projected areas of the gate insulating layer 150 and the gate electrode 160 on the substrate 110 are equal to or smaller than the projected area of the active layer 140 on the substrate 110, and the projected area of the first electrode 120 on the substrate 110 is larger than the projected area of the active layer 140 on the substrate 110. That is, in the present embodiment, at least one inclined plane 132 is disposed, and the thin film transistor is disposed on the inclined plane 132, so that the vertical space of the display region is fully utilized, the lateral size of the thin film transistor is effectively reduced, and the improvement of the high resolution (PPI) of the pixel in the display region is realized.
In the embodiment shown in fig. 1, an interlayer insulating layer 180(ILD) is further included. The interlayer insulating layer 180 is disposed on the gate electrode 160, the spacer layer 130 and the substrate 110, and the second electrode 170 is disposed on the active layer 140 through the interlayer insulating layer 180 by passing through the first through hole 172. The first electrode 120 is a source or a drain, and the second electrode 170 is a drain or a source. That is, when the first electrode 120 is a source, the second electrode 170 is a drain. When the first electrode 120 is a drain, the second electrode 170 is a source. The first electrode 120 disposed parallel to the substrate 110 may be used as an electrode of a TFT, a light shielding Layer (LS), data, scanning lines, and the like.
Referring to fig. 3, the present embodiment further includes a passivation layer 190, a planarization layer 200, a pixel defining layer 220 and a pixel electrode 210 disposed on the planarization layer 200, wherein the pixel electrode 210 passes through the planarization layer 200 and the passivation layer 190 through a second through hole 212 to electrically connect to the second electrode 170, so as to complete the tft substrate 100. The thin film transistor substrate 100 of the present embodiment can be used as a driving back plate of a submillimeter light emitting diode (Mini LED), a Micro LED or an Organic Light Emitting Diode (OLED) as required.
Note that the angle of the inclination angle θ includes 45 degrees to 80 degrees, which can improve the high resolution of the pixels in the display region. Specifically, when the height H of the spacer layer 130 is preferably 0.42 μm to 2 μm, the length L is preferably 6.5 μm, and the angle of the tilt angle θ is preferably 45 degrees to 60 degrees, the maximum high resolution can be achieved, effectively reducing the lateral dimension of the TFT by about 70% (the ratio between the vertical structure of the present embodiment and the DG TFT shown in fig. 1). In comparison with fig. 1, the lateral dimension of the TFT of this embodiment is significantly optimized because the gate electrode 160 utilizes the advantage of the slope 132, and two through holes can be omitted. Therefore, compared with the structure shown in fig. 1, the TFT substrate 100 with the vertical structure of the present embodiment can effectively increase the lateral ratio of the TFT, thereby improving the resolution of the pixel.
Referring to fig. 4 to 8, the present invention further provides a method for manufacturing a thin film transistor substrate 100, including the following steps: step S10, providing a substrate 110; step S20, forming a first electrode 120 on the substrate 110; step S30, forming a spacer layer 130 on the first electrode 120, wherein at least one inclined plane 132 is formed on one side of the spacer layer 130; step S40, forming an active layer 140 on the inclined surface 132; step S50, forming a gate insulating layer 150 on the active layer 140; step S60, forming a gate 160 on the gate insulating layer 150; and step S70, forming a second electrode 170 on the active layer 140 and corresponding to the plane 134 of the spacer layer 130, wherein the gate insulating layer 150 and the gate 160 are formed on the inclined plane 132 corresponding to the active layer 140, and the spacer layer 130 and the substrate 110 have an inclined angle θ therebetween.
In step S10, the substrate 110, such as a glass substrate, a flexible substrate or other suitable substrate, is cleaned, and a layer of 2000 angstroms is deposited
Figure BDA0003231513090000071
To
Figure BDA0003231513090000072
A first electrode 120 of thickness. In step S30, the spacer layer 130 is an insulating layer deposited with an inorganic, organic or multilayer structure, and is deposited on the inclined plane 132 on one side of the insulating layer by patterning, and the thickness of the spacer layer 130 is 5000 to 30000 angstroms.
In step S40, a layer of metal Oxide semiconductor (Oxide) is deposited as a semiconductor layer, and the Oxide layer is patterned to cover the semiconductor layerIn a region on the inclined surface 132, the metal oxide semiconductor material may be Indium Gallium Zinc Oxide (IGZO), IZTO, IGZTO, or the like, and the active layer 140 has a thickness of 100 to 1000 angstroms. In step S50, a layer of silicon oxide (SiO) is depositedx) Or silicon nitride (SiN)x) Or a multi-layer structure of a combination thereof, as the gate insulating layer 150(GI), has a thickness of 1000 to 3000 angstroms.
In step S60, a metal or alloy layer with a thickness of 3000 to 5000 angstroms is deposited and patterned as the gate 160, and a portion of the gate insulating layer 150 is etched by using the gate 160 pattern as a self-aligned pattern, so that only under the gate 160 pattern, the gate insulating layer 150 exists, and the gate insulating layer 150 is etched away, thereby exposing a portion of the active layer 140. Specifically, in the step of forming the gate insulating layer 150 and the gate electrode 160 on the inclined surface 132 corresponding to the active layer 140, the gate electrode 160 is patterned by using a mask, and then the patterned gate electrode 160 is used as the mask to pattern and etch the gate insulating layer 150 formed below to expose the active layer 140. The material of the first electrode 120 and the second electrode 170 includes molybdenum (Mo), chromium (Cr), aluminum (Al), copper (Cu), titanium (Ti), or a combination thereof.
Referring to fig. 7 and 8, before step S70, the method further includes performing a plasma treatment on the entire surface of the gate electrode 160 to reduce the resistance of the gate electrode 160 and form an N + conductor layer, wherein the active layer 140 under the gate insulating layer 150 maintains the characteristics of a metal Oxide semiconductor (Oxide) as a channel of the thin film transistor substrate 100. After step S70, an interlayer insulating layer 180(ILD), a passivation layer 190(PV), a planarization layer 200(PLN), a pixel definition layer 220(PDL), and a pixel electrode 210 disposed on the planarization layer 200 are further included. The interlayer insulating layer 180 is formed on the gate electrode 160, the spacer layer 130 and the substrate 110, and the second electrode 170 is electrically connected to the active layer 140 through the interlayer insulating layer 180 by a first through hole 172. The pixel electrode 210 is electrically connected to the second electrode 170 through the planarization layer 200 and the passivation layer 190 via a second through hole 212.
In step S70, the second electrode 170 is another electrode deposited to a thickness of 2000 to 8000 a, and electrically connected to the exposed active layer 140, and then a pattern is defined. In the embodiment shown in fig. 4 to 8, the first electrode 120 is preferably a source electrode, and the second electrode 170 is a drain electrode. In other alternative embodiments, however, the first electrode 120 is a drain and the second electrode 170 is a source. The first electrode 120 disposed parallel to the substrate 110 may be used as an electrode of a TFT, a light shielding layer, data, scanning lines, and the like.
Specifically, the interlayer insulating layer 180 and the passivation layer 190 are also deposited with a layer of silicon oxide (SiO)x) Or silicon nitride (SiN)x) Or a multi-layer film structure of a combination thereof. The interlayer insulating layer 180 is patterned such that the active layer 140 exposed with respect to the first electrode 120 and the other side is in contact with the substrate 110, and has a thickness of 3000 to 5000 angstroms. The thickness of the passivation layer 190 is 1000 to 5000 angstroms. Then, the planarization layer 200 is formed as required, and an opening is formed in a region where the pixel electrode 210 is connected to form a second through hole 212. Finally, the pixel electrode 210 is manufactured and patterned, and the pixel definition layer 220 can be continuously manufactured as required, so as to complete the manufacturing of the thin film transistor substrate 100, so that the present embodiment can be manufactured as a driving back plate of a submillimeter light emitting diode (Mini LED), a Micro LED (Micro LED) or an Organic Light Emitting Diode (OLED).
It should be noted that the angle of the tilt angle θ includes 45 degrees to 80 degrees, which can improve the high resolution of the pixels in the display area. Specifically, when the height H of the spacer layer 130 ranges from 0.42 μm to 2 μm, the length L is 6.5 μm, and the angle of the tilt angle θ ranges from 45 degrees to 60 degrees, the maximum high resolution can be achieved, so that the lateral dimension of the TFT can be effectively reduced by about 70% (the ratio between the vertical structure of the present embodiment and the DG TFT shown in fig. 1). In comparison with fig. 1 of the prior art, the lateral dimension of the TFT of this embodiment is significantly optimized because the gate 160 utilizes the advantage of the inclined surface 132, and two fewer through holes can be formed without additional masks, so as to meet the requirement of manufacturing the TFT substrate 100. Therefore, compared with the structure shown in fig. 1, the TFT substrate 100 with the vertical structure of the present embodiment can effectively increase the lateral ratio of the TFT, thereby improving the resolution of the pixel.
Furthermore, the present embodiment further provides a display device, which includes the thin film transistor substrate 100 disclosed in the foregoing embodiments. For details of the structure, the function and the manufacturing method of the tft substrate 100, please refer to the above embodiments, which are not described herein again.
In view of the foregoing, while the present invention has been described in conjunction with specific embodiments thereof, it is to be understood that many alternatives, modifications, and variations will be apparent to those skilled in the art. Accordingly, it is intended to embrace all such alternatives, modifications, and variations that fall within the scope of the included claims.

Claims (10)

1. A thin film transistor substrate, comprising:
a substrate;
a first electrode disposed on the substrate;
the spacing layer is arranged on the first electrode and provided with at least one inclined plane;
an active layer disposed on the inclined plane;
a gate insulating layer disposed on the active layer;
a gate electrode disposed on the gate insulating layer; and
the second electrode is arranged on the active layer and corresponds to the plane of the spacing layer, the gate insulating layer and the gate are arranged on the inclined plane corresponding to the active layer, and an inclined angle is formed between the spacing layer and the substrate.
2. The thin film transistor substrate of claim 1, wherein both sides of the active layer partially extend along the slopes to the plane of the first electrode and the spacer layer, a projected area of the gate insulating layer and the gate electrode on the substrate is equal to or smaller than a projected area of the active layer on the substrate, and a projected area of the first electrode on the substrate is larger than a projected area of the active layer on the substrate.
3. The thin film transistor substrate of claim 1, further comprising an interlayer insulating layer disposed on the gate electrode, the spacer layer, and the substrate, wherein the second electrode is disposed on the active layer through the interlayer insulating layer, wherein the first electrode is a source electrode or a drain electrode, and wherein the second electrode is a drain electrode or a source electrode.
4. The thin film transistor substrate of claim 1, further comprising a passivation layer, a planarization layer, a pixel defining layer, and a pixel electrode disposed on the planarization layer in a stacked manner, wherein the pixel electrode penetrates the planarization layer and the passivation layer to electrically connect the second electrode, and the angle of the tilt angle comprises 45 degrees to 80 degrees.
5. A manufacturing method of a thin film transistor substrate comprises the following steps:
providing a substrate;
forming a first electrode on the substrate;
forming a spacing layer on the first electrode, wherein one side of the spacing layer forms at least one inclined plane;
forming an active layer on the slope;
forming a gate insulating layer on the active layer;
forming a gate electrode on the gate insulating layer; and
and forming a second electrode on the active layer and corresponding to the plane of the spacing layer, wherein the gate insulating layer and the gate are formed on the inclined plane corresponding to the active layer, and an inclined angle is formed between the spacing layer and the substrate.
6. The method of manufacturing the thin film transistor substrate according to claim 5, wherein in the step of forming the spacer layer on the first electrode, the spacer layer is an insulating layer deposited in an inorganic, organic, or multilayer structure, and is deposited on the inclined surface on one side of the insulating layer in a patterned manner, a thickness of the spacer layer includes 5000 to 30000 angstroms, and an angle of the inclination angle includes 45 to 80 degrees.
7. The method of manufacturing the thin film transistor substrate according to claim 5, wherein in the step of forming the gate insulating layer and the gate electrode on the inclined surface corresponding to the active layer, the gate electrode is patterned using a mask, and then the patterned gate electrode is used as the mask to pattern and etch the gate insulating layer formed therebelow to expose the active layer; before the step of forming the second electrode on the active layer corresponding to the plane, the method further comprises the step of carrying out whole-surface plasma treatment on the grid electrode, so that the resistance of the grid electrode is reduced, and an N + conductor layer is formed, wherein the active layer below the grid electrode insulating layer keeps the metal oxide semiconductor characteristic and is used as a thin film transistor substrate channel.
8. The method of claim 5, further comprising forming an interlayer insulating layer formed on the gate electrode, the spacer layer, and the substrate, a passivation layer, a planarization layer, a pixel defining layer, and a pixel electrode disposed on the planarization layer, wherein the second electrode is electrically connected to the active layer through the interlayer insulating layer, and the pixel electrode is electrically connected to the second electrode through the planarization layer and the passivation layer, wherein the first electrode is a source electrode or a drain electrode, and the second electrode is a drain electrode or a source electrode.
9. The method of claim 8, wherein the first electrode and the second electrode are made of mo, cr, al, cu, ti, or combinations thereof, the active layer has a thickness of 100 to 1000 angstroms, the gate insulating layer has a thickness of 1000 to 3000 angstroms, the interlayer insulating layer is made of si oxide, si nitride, or combinations thereof and has a thickness of 3000 to 5000 angstroms, and the passivation layer PV is made of si oxide, si nitride, or combinations thereof and has a thickness of 1000 to 5000 angstroms.
10. A display device, the thin film transistor substrate according to any one of claims 1 to 4.
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