CN111554695A - Display substrate, manufacturing method thereof and display device - Google Patents
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
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Abstract
The application discloses a display substrate, a manufacturing method thereof and a display device. The display substrate includes a substrate, a light-shielding layer and a planarization layer on the substrate, a buffer layer covering the planarization layer and the light-shielding layer, and an active layer on the buffer layer. The light shielding layer comprises a light shielding layer polar plate, and the active layer comprises an active layer first polar plate. The display substrate is provided with a storage capacitor formed by connecting at least two capacitors in parallel. The active layer first polar plate, the shading layer polar plate and the buffer layer positioned between the active layer polar plate and the shading layer polar plate form a capacitor of the storage capacitor. The buffer layer covers on the planarization layer and the shading layer, so that the thickness of the buffer layer can be reduced, the retention time of the buffer layer in the CVD chamber is short, the number of buffer layer particles is reduced, and the problem of high light spot is solved. In addition, the reduction of the thickness of the buffer layer also increases the capacitance value of the storage capacitor, and meets the requirements of high resolution and high refresh rate display.
Description
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to a display substrate, a manufacturing method thereof, and a display device.
Background
The OLED display panel (for example, the OLED display panel of 8K) has the advantages of high resolution and high refresh frequency, and is the focus of current research and development. The display substrate of the OLED display panel comprises a thin film transistor and a storage capacitor connected with the thin film transistor. The prior OLED display panel has the technical problem of high light point emission. Furthermore, in order to meet the requirements of high resolution and high refresh rate, the skilled person is faced with the technical problem of increasing the capacitance value of the storage capacitor.
Disclosure of Invention
To overcome some or all of the problems of the related art, the present application provides a display substrate. The display substrate comprises a substrate, a light shielding layer and a planarization layer which are positioned on the substrate, a buffer layer which covers the planarization layer and the light shielding layer, and an active layer which is positioned on the buffer layer; the light shielding layer comprises a light shielding layer polar plate, and the active layer comprises an active layer first polar plate. The display substrate is provided with a storage capacitor formed by connecting at least two capacitors in parallel, and the active layer first polar plate, the shading layer polar plate and a buffer layer between the active layer first polar plate and the shading layer polar plate form one capacitor of the storage capacitor.
In another aspect, the present application discloses a display device. The display device comprises the display polar plate.
In another aspect, the present application discloses a method of manufacturing a display substrate. The display substrate comprises a storage capacitor formed by connecting at least two capacitors in parallel, and the manufacturing method comprises the following steps:
forming a shading layer and a planarization layer on a substrate, wherein the shading layer comprises a shading layer polar plate;
forming a buffer layer covering the planarization layer and the light-shielding layer;
and forming an active layer on the buffer layer, wherein the active layer comprises an active layer first polar plate, and the active layer first polar plate, the shading layer polar plate and the buffer layer between the active layer first polar plate and the shading layer polar plate form one capacitor of the storage capacitor.
The technical scheme provided by the embodiment of the application at least has the following beneficial effects:
because the display substrate includes the light shield layer and the planarization layer that are located on this basement, cover the planarization layer with the buffer layer of light shield layer and be located on the buffer layer and including the active layer of active layer first polar plate, the light shield layer includes the light shield layer polar plate, active layer first polar plate, light shield layer polar plate and active layer first polar plate and the buffer layer between the light shield layer polar plate constitutes storage capacitor's a electric capacity, like this, the buffer layer covers and makes the thickness of buffer layer can reduce at planarization layer and light shield layer to, the buffer layer is short in the time of CVD cavity dwell, has reduced the quantity of buffer layer granule (buffer), has improved the problem that the bright spot is high, and moreover, the thickness of buffer layer reduces and has also increased storage capacitor's capacitance value, satisfies 8k high resolution and high refresh rate display's demand.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application.
FIG. 1 is a schematic diagram of a storage capacitor of an OLED display substrate;
FIG. 2 is a schematic diagram of a structure of a storage capacitor of another OLED display substrate;
FIG. 3 is a schematic diagram of forming a light-shielding layer of an OLED display substrate;
FIG. 4 is a schematic view of forming a planarization layer;
FIG. 5 is a schematic view of forming a buffer layer;
fig. 6 is a schematic view of forming an active layer;
FIG. 7 is a schematic illustration of forming a gate insulating layer and a gate electrode;
FIG. 8 is a schematic diagram of forming an interlevel dielectric layer;
FIG. 9 is a schematic illustration of the patterning of an interlevel dielectric layer;
FIG. 10 is a schematic illustration of forming a source drain layer;
FIG. 11 is a schematic illustration of the formation of a passivation layer;
FIG. 12 is a schematic view of another planarization layer being formed;
FIG. 13 is a schematic illustration of forming a reflective anode;
fig. 14 is a schematic view of a light emitting layer;
fig. 15 is a schematic view of forming a transparent cathode.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be understood that the terms "first," "second," and the like as used in the description and in the claims, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Similarly, the use of the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one; "plurality" means two or more than two. Unless otherwise indicated, "front", "rear", "lower" and/or "upper" and the like are for convenience of description and are not limited to one position or one spatial orientation. The word "comprising" or "comprises", and the like, means that the element or item listed as preceding "comprising" or "includes" covers the element or item listed as following "comprising" or "includes" and its equivalents, and does not exclude other elements or items.
Exemplary embodiments of the present application will be described in detail below with reference to the accompanying drawings. In the following embodiments, features of the embodiments can be supplemented with each other or combined with each other without conflict.
Referring to fig. 1, a storage capacitor of an OLED display substrate includes a first capacitor and a second capacitor. The first capacitor and the second capacitor are connected in parallel. The first capacitor includes a light shield plate 2a formed on a substrate 1, a buffer layer 3a on the light shield plate 2a, and an active layer first plate 4a on the buffer layer 3 a. The light shield electrode plate 2a and the active layer first electrode plate 4a serve as two electrode plates of the first capacitor. The second capacitor comprises the active layer first electrode plate 4a, an interlayer dielectric layer 5 and a source drain electrode layer electrode plate 6. The active layer first polar plate 4a and the source drain polar plate 6 are used as two polar plates of the second capacitor. The active layer first plate 4a belongs to a portion of the active layer, which also includes a channel region of the thin film transistor. The source drain layer plate 6 is part of a source drain layer that also includes the source and drain of the thin film transistor. Of course, the OLED display substrate further includes a passivation layer 7 on the source and drain electrode layers, a planarization layer 8 on the passivation layer 7, and a reflective anode 9 for the entire OLED display substrate.
The OLED display substrate has the problem of high bright spots. The inventor analyzes and finds that, since the buffer layer 3a is manufactured by a PECVD (Plasma Enhanced Chemical Vapor Deposition) process and needs to cover the step formed by the light shield layer plate 2a and the substrate 1, the buffer layer 3a is made thicker, for example, 4000 angstroms thick, and then the buffer layer 3a needs to be deposited under the Deposition conditions of high power and high air pressure ratio, the Deposition speed is slow, and the two factors of slow Deposition speed and thick thickness cause the retention time of the buffer layer 3a in the CVD chamber to be too long, which further causes the buffer layer particles (buffer particles) to be highly emitted, and the OLED display substrate has a problem of high emission. In addition, in the OLED display substrate, as the resolution and the refresh rate are improved, the capacitance of the storage capacitor needs to be increased continuously, and the buffer layer 3a is too thick to meet the requirement of increasing the capacitance of the storage capacitor. One way to increase the capacitance of the storage capacitor is to increase the area of the plate, but the metal routing of the OLED display substrate (e.g., 8k OLED display substrate) is dense and cannot meet the requirement of increasing the area, and therefore, how to increase the capacitance of the storage capacitor is also a problem for the skilled person.
In order to improve the high light emission and solve the problem of how to increase the capacitance of the storage capacitor, the inventor of the present application obtains a mode of reducing the thickness of the buffer layer through analysis and experiments, the reduction of the thickness of the buffer layer reduces the retention time of the buffer layer in the CVD chamber to reduce the number of buffer layer particles (buffer particles), thereby effectively improving the high light emission, and moreover, the reduction of the thickness of the buffer layer reduces the distance between two electrode plates (the light shielding layer electrode plate 2a and the active layer first electrode plate 4a) of the capacitor, thereby increasing the capacitance, and satisfying the requirements of high resolution and high refresh rate display such as 8 k.
Based on such technical concept, as shown in fig. 2, the OLED display substrate disclosed in the present application includes an active layer first electrode plate 4a, an interlayer dielectric layer 5, a source drain electrode layer 6, and the like of the OLED display substrate shown in fig. 1, and the OLED display substrate is different from the OLED display substrate in that the OLED display substrate includes a substrate 1, a light shielding layer electrode plate 2a located on the substrate 1, a planarization layer 10 located on the substrate 1 and disposed on the same layer as the light shielding layer electrode plate 2a, and a buffer layer 3b covering the planarization layer 10 and the light shielding layer electrode plate 2 a. Fig. 2 shows only one light shield plate 2a, but actually, there are a plurality of light shield plates 2a, and the plurality of light shield plates 2a are provided in the same layer with a gap provided therebetween. The plurality of light shield plates 2a distributed in the same layer may be regarded as light shield layers. The planarization layer 10 is provided in the space between the adjacent light shield electrode plates 2 a. In some embodiments, the planarization layer 10 is provided only in the space between the adjacent light shield plates 2 a.
In the OLED display substrate with the structure, the light shielding layer polar plate 2a, the active layer first polar plate 4a, the buffer layer 3b between the light shielding layer polar plate 2a and the active layer first polar plate 4a form a first capacitor of the storage capacitor, the active layer first polar plate 4a, the source drain polar plate 6 and the interlayer dielectric layer 5 between the active layer first polar plate 4a and the source drain polar plate 6 form a second capacitor of the storage capacitor, and the source drain polar plate is electrically connected with the light shielding layer polar plate.
In the above OLED substrate, the first capacitor and the second capacitor share the active layer first electrode plate 4 a. The active layer comprises an active layer second polar plate, the active layer second polar plate, a source drain polar plate and an interlayer dielectric layer between the active layer second substrate and the source drain polar plate form another capacitor of the storage capacitor, the source drain polar plate is electrically connected with the shading layer polar plate, and the active layer second polar plate is electrically connected with the active layer first polar plate.
Although fig. 2 illustrates a schematic structural diagram of a storage capacitor of an OLED display substrate, since the light shielding plate 2a and the planarization layer 10 are both located on the substrate 1 and covered by the buffer layer 3b, and then other film layers constituting a thin film transistor and other parts of the storage capacitor are formed on the buffer layer 3b, a skilled person can obtain at least two technical suggestions as follows: 1) the light shield layer polar plate 2a and the planarization layer 10 are both located on the substrate 1 and covered by the buffer layer 3b, and further, the technical concept of improving the high light emission and increasing the capacitance can be applied to other display substrates, such as a TFT display substrate in an LCD display panel; 2) the structure of the storage capacitor of the display substrate is different from that of the storage capacitor shown in fig. 2, as long as the display substrate forms the light shielding layer and the planarization layer on the substrate, and the light shielding layer and the planarization layer are covered by the buffer layer, and one capacitor of the storage capacitor includes the active layer first electrode plate, the light shielding layer electrode plate and the buffer layer therebetween.
Next, a method of manufacturing an OLED display substrate is described.
As shown in fig. 3, a metal thin film (e.g., Mo, Al, etc.) is deposited on the substrate 1 using a Sputter (magnetron sputtering) process, and the deposited metal thin film is patterned using a patterning process (e.g., Mask process) to form a light shield layer (a plurality of light shield plates 2 a). The light-shielding layer includes a light-shielding portion 2b which functions as a light-shielding but does not function as a capacitor plate, in addition to the light-shielding plate 2 a. In some embodiments, the light shielding portion 2b may not be included.
The inventors found that too large thickness of the light shielding layer makes the thickness of the planarization layer 10 too thick in the subsequent steps and makes the thickness of the display panel too thick, which is costly, and that too small thickness of the light shielding layer makes the resistance of the routing region of the light shielding layer larger, and the light shielding effect is deteriorated. Based on this, in some embodiments, the light-shielding layer has a thickness of 1000 to 1500 angstroms, such as 1000 angstroms, 1050 angstroms, 1100 angstroms, 1120 angstroms, 1150 angstroms, 1200 angstroms, 1250 angstroms, 1300 angstroms, 1310 angstroms, 1350 angstroms, 1380 angstroms, 1400 angstroms, 1420 angstroms, 1450 angstroms, 1470 angstroms, or 1500 angstroms. The thickness of the light-shielding layer is within the above range, so that the resistance is not too large, the entire thickness of the OLED display panel is not too thick, and the planarization layer is not too thick.
As shown in fig. 4, the light shield layer is planarized (i.e., the space between adjacent light shield plates 2a is filled) to form a planarized layer 10 on the substrate 1. In some embodiments, the planarization layer 10 may be formed using a Coating process (Coating process). The thickness of the planarization layer 10 may be smaller than, equal to, or larger than the thickness of the light-shielding layer (light-shielding layer plate 2 a). However, the inventor found that the fact that the thickness of the planarization layer 10 is greater than the thickness of the light-shielding layer (compared to the case that the thickness of the planarization layer 10 is equal to the thickness of the light-shielding layer) leads to a reduction in capacitance, because the coating process is usually full-surface coating, which causes the dielectric between the plates of the first capacitor including the buffer layer 3b and the planarization layer 10, corresponding to an increase in the distance between the two plates, and the fact that the planarization layer 10 is too low compared to the light-shielding layer (or the light-shielding layer plate 2a) causes a step between the planarization layer 10 and the light-shielding layer plate 2a, and further, the thickness of the buffer layer 3b is greater, which leads to a smaller capacitance value of the first capacitor, and also increases the possibility of generating a bright-spot high-incidence problem, based on which the planarization layer 10 is flush with the light-shielding layer, or flush with the light-shielding layer plate 2a, or the planarization, such as 10 angstroms, 20 angstroms, 50 angstroms, 70 angstroms, 100 angstroms, 110 angstroms, 140 angstroms, 180 angstroms, 200 angstroms, 220 angstroms, 250 angstroms, or 300 angstroms.
In addition to the above, the planarization layer 10 and the light-shielding layer may be formed as follows: depositing a whole metal film (such as Mo, Al and the like) on the substrate 1 by adopting a Sputter (magnetron sputtering) process, then, covering the metal film by using a mask plate comprising a shading layer pattern, oxidizing the region of the metal film corresponding to the planarization layer 10, and forming an insulated planarization layer 10 after oxidation; the regions that are not oxidized serve as light-shielding layers (light-shielding electrode plates 2a and/or light-shielding portions 2 b).
As shown in fig. 5, an insulating thin film (e.g., silicon oxide, silicon nitride, etc.) is deposited as a buffer layer 3b, and the buffer layer 3b covers the light-shielding layer (the light-shielding plate 2a and the light-shielding portion 2b) and the planarization layer 10. The inventor finds that: the buffer layer 3b is too thick, and more buffer particles (buffer particles) are easily generated, so that the bright spot phenomenon is more serious, and the capacitance value is smaller, therefore, in some embodiments, the buffer layer 3b has a thickness of 1000 to 2000 angstroms, such as 1000 angstroms, 1050 angstroms, 1100 angstroms, 1160 angstroms, 1200 angstroms, 1250 angstroms, 1300 angstroms, 1340 angstroms, 1400 angstroms, 1420 angstroms, 1460 angstroms, 1500 angstroms, 1550 angstroms, 1600 angstroms, 1620 angstroms, 1650 angstroms, 1680 angstroms, 1700 angstroms, 1750 angstroms, 1800 angstroms, 1920 angstroms, 1950 angstroms, 1970 angstroms, or 2000 angstroms. When the thickness of the buffer layer 3b is within the above range, the problem of high luminance points is improved, and a large capacitance value can be advantageously maintained. In some embodiments, the process conditions for depositing the buffer layer 3b are: power: 15-20 kw, nitrous oxide/silane: 60/1-90/1, deposition time: 90s to 200 s.
As shown in fig. 6, an oxide semiconductor thin film (e.g., IGZO, ITZO, etc.) is deposited as an Active layer (Active) on the buffer layer 3b, and the Active layer is patterned, whereby the Active layer includes a channel region 4b of the thin film transistor and the Active layer first electrode plate 4 a. The active layer first electrode plate 4a is positioned above the light shielding layer electrode plate 2a, and the channel region 4b is positioned above the light shielding portion 2 b. The active layer is too thin and easily becomes a conductor, but the risk of the bright spot being generated due to the burst by the buffer layer particles on the buffer layer 3b is increased; too thick an active layer may make it difficult to make a conductor, and may cause too large an operating voltage of the OLED display panel. Therefore, in some embodiments, the thickness of the active layer is 200 a to 800 a, and in this range, the risk of bright spots occurring due to the active layer being broken by the buffer layer particles on the buffer layer 3b can be reduced, the conduction is easier, and the operating voltage is not too large. The thickness of the active layer is, for example, 200 angstroms, 250 angstroms, 300 angstroms, 310 angstroms, 360 angstroms, 400 angstroms, 450 angstroms, 500 angstroms, 510 angstroms, 550 angstroms, 600 angstroms, 660 angstroms, 700 angstroms, 720 angstroms, 750 angstroms, 780 angstroms, or 800 angstroms.
As shown in fig. 7, an insulating film (e.g., silicon oxide, silicon nitride, etc.) is deposited on the active layer as a Gate insulating layer (GI)11 using a PECVD process, then a metal film (e.g., Cu, Al, etc.) is deposited on the Gate insulating layer 11 using a Sputter (magnetron sputtering) process and patterned as a Gate electrode (Gate)12, and then the Gate insulating layer 11 is patterned using a dry etching process, and then the active layer is conducted to a conductor (doped with N-type or P-type conductive impurities) so that the active layers at both sides of the channel region 4b become a source region and a drain region of the thin film transistor. Too thick the gate insulating layer 11 may cause too large a turn-on voltage of the thin film transistor, and too thin the gate insulating layer 11 may be broken by the buffer layer particles to cause a problem of high luminance. In some embodiments, the gate insulating layer 11 has a thickness of 1000 to 2000 angstroms, such as 1000 angstroms, 1050 angstroms, 1100 angstroms, 1120 angstroms, 1150 angstroms, 1180 angstroms, 1200 angstroms, 1250 angstroms, 1280 angstroms, 1300 angstroms, 1310 angstroms, 1360 angstroms, 1400 angstroms, 1450 angstroms, 1500 angstroms, 1520 angstroms, 1550 angstroms, 1570 angstroms, 1600 angstroms, 1650 angstroms, 1700 angstroms, 1720 angstroms, 1740 angstroms, 1770 angstroms, 1800 angstroms, 1810 angstroms, 1850 angstroms, 1900 angstroms, 1920 angstroms, 1950 angstroms, 1980 angstroms or 2000 angstroms. The thickness of the gate insulating layer 11 in the above range reduces the possibility that the gate insulating layer 11 is broken by the buffer layer particles, can improve the problem of high luminance, and can prevent the on-voltage of the thin film transistor from being too large.
As shown in fig. 8, an insulating film (e.g., silicon oxide, silicon nitride, etc.) is deposited as an Interlayer dielectric layer 5 by a PECVD process.
As shown in fig. 9, a plurality of via holes 52 are formed in the interlayer dielectric layer 5 to expose at least a partial region of the active layer first plate 4a and at least partial regions of the source and drain regions of the thin film transistor. In some embodiments, the via 52 may be formed using a partial etching process.
As shown in fig. 10, a metal film (e.g., Cu, Al, etc.) is deposited as a source/drain layer on top of the interlayer dielectric layer 5, and the source/drain layer is patterned to form a source/drain and source/drain layer electrode plate 6 of the thin film transistor. In the process of manufacturing the source/drain layer, part of the metal is filled in the through hole 52, so as to communicate the source with the source region of the underlying thin film transistor, and communicate the drain with the drain region of the underlying thin film transistor. In some embodiments, the source and drain layers may be formed by a magnetron sputtering process.
At this step, the thin film transistors and the storage capacitors of the OLED substrate are manufactured, as shown in fig. 10, 3 thin film transistors T1, T2, and T3 are illustrated, the first capacitor includes a light shielding layer electrode plate 2a, an active layer first electrode plate 4a, and a buffer layer 3b therebetween, and the second capacitor includes an active layer first electrode plate 4a, a source drain electrode layer electrode plate 6, and an interlayer dielectric layer 5 therebetween. The first capacitor and the second capacitor are connected in parallel by a connection portion 61 for connecting the light shield layer plate 2a and the source drain layer plate 6. The source/drain electrode layer 6 is not only a plate of a capacitor in the present embodiment, but both ends thereof are a source and a drain, respectively, and as shown in fig. 10, the left end of the source/drain electrode layer substrate 6 is a drain of the thin film transistor T2, and the right end thereof is a source of the thin film transistor T3.
As shown in fig. 11, an insulating film (e.g., silicon oxide, silicon nitride, etc.) is formed as a passivation layer (PVX)7 above the source/drain layer 6. In some embodiments, the passivation layer 7 may be formed using a PECVD process.
As shown in fig. 12, a planarization layer 8 is deposited over the passivation layer 7, and then a patterning (e.g., partial etching) process is used to sequentially form an opening 81 in the planarization layer 8 and an opening in the passivation layer 7 (see fig. 13).
As shown in fig. 13, a thin metal film (e.g., Mo/Al/ITO) is deposited on the planarization layer 8 as a reflective anode 9 by a Sputter (magnetron sputtering) process. During the formation of the reflective anode 9, a portion of the metal material may fill the opening 81 of the planarization layer 8 and the opening of the passivation layer 7 to connect the reflective anode 9 and the source drain layer plate 6.
As shown in fig. 14, a light-Emitting Layer (EL)13 is vapor-deposited on the reflective anode 9 by a vapor deposition process.
As shown in fig. 15, a metal thin film (e.g., ITO) is deposited as a transparent cathode 14 on the light Emitting Layer (EL)13 by a Sputter (magnetron sputtering) process, and then an encapsulation layer 15 is formed over the transparent cathode 14 to form a top emission OLED display panel. The encapsulation layer 15 may be a stacked structure of an inorganic material layer-an organic material layer-an inorganic material layer.
Although the above embodiment has been described by taking an OLED substrate and a storage capacitor including two capacitors as an example, it can be understood by those skilled in the art that the process steps after forming the buffer layer 3b in the above steps are mainly related to the formation of the thin film transistor and the storage capacitor, and based on the technical teaching, the skilled in the art can understand that there may be other process steps for forming the thin film transistor and the storage capacitor after forming the buffer layer 3b according to the structure of the display substrate, the thin film transistor and the storage capacitor, and the process steps are not limited by the above embodiment, and based on this, such embodiment includes:
a manufacturing method of a display substrate, the display substrate comprises a storage capacitor formed by connecting at least two capacitors in parallel, the manufacturing method comprises the following steps:
forming a shading layer and a planarization layer on a substrate, wherein the shading layer comprises a shading layer polar plate;
forming a buffer layer covering the planarization layer and the light-shielding layer;
and forming an active layer on the buffer layer, wherein the active layer comprises an active layer first polar plate, and the active layer first polar plate, the shading layer polar plate and the buffer layer between the active layer first polar plate and the shading layer polar plate form one capacitor of the storage capacitor.
In some embodiments, the storage capacitor is formed by connecting two capacitors in parallel, and correspondingly, an interlayer dielectric layer and a source drain electrode layer may be further sequentially formed on the active layer, the source drain electrode layer includes a source drain electrode layer polar plate, the active layer first polar plate, the source drain electrode layer polar plate and the interlayer dielectric layer therebetween form another capacitor of the storage capacitor, and the source drain electrode layer polar plate is electrically connected with the light shielding layer polar plate, so that the two capacitors are connected in parallel.
In other embodiments, the storage capacitor is formed by connecting two capacitors in parallel, the formed active layer further includes an active layer second electrode plate, and further sequentially forms an interlayer dielectric layer and a source drain layer including a source drain electrode layer electrode plate on the active layer, and the active layer second electrode plate, the source drain electrode layer electrode plate, and the interlayer dielectric layer located between the active layer second electrode plate and the source drain electrode layer electrode plate form another capacitor of the storage capacitor. The second active layer electrode plate is electrically connected with the first active layer electrode plate, and the source drain electrode layer electrode plate is electrically connected with the shading layer electrode plate, so that the two capacitors are connected in parallel.
Although the present application has been described with reference to a preferred embodiment, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the application, and all changes, substitutions and alterations that fall within the spirit and scope of the application are to be understood as being covered by the following claims.
Claims (11)
1. A display substrate includes a base, a light-shielding layer and a planarization layer on the base, a buffer layer covering the planarization layer and the light-shielding layer, and an active layer on the buffer layer; the light shielding layer comprises a light shielding layer polar plate, and the active layer comprises an active layer first polar plate;
the display substrate is provided with a storage capacitor formed by connecting at least two capacitors in parallel, and the active layer first polar plate, the shading layer polar plate and a buffer layer between the active layer first polar plate and the shading layer polar plate form one capacitor of the storage capacitor.
2. The display substrate according to claim 1, wherein the storage capacitor is formed by connecting two capacitors in parallel, the display substrate comprises an interlayer dielectric layer and a source drain layer which are laminated on the active layer, the source drain layer comprises a source drain layer polar plate, the active layer first polar plate, the source drain layer polar plate and the interlayer dielectric layer positioned between the active layer first polar plate and the source drain layer polar plate form another capacitor of the storage capacitor, and the source drain layer polar plate is electrically connected with the light shield layer polar plate;
or, the storage capacitor is formed by connecting two capacitors in parallel, the active layer further comprises an active layer second polar plate, the display substrate further comprises an interlayer dielectric layer and a source drain polar layer which are stacked on the active layer, the source drain polar layer comprises a source drain polar plate, the active layer second polar plate, the source drain polar plate and the interlayer dielectric layer between the active layer second polar plate and the source drain polar plate form the other capacitor of the storage capacitor, the source drain polar plate is electrically connected with the shading layer polar plate, and the active layer second polar plate is electrically connected with the active layer first polar plate.
3. The display substrate according to claim 1, wherein the light-shielding layer has a thickness of 1000 to 1500 angstroms.
4. The display substrate according to claim 1, wherein the planarization layer is flush with the light-shielding layer or is lower than the light-shielding layer by a height difference of not more than 300 angstroms.
5. The display substrate of claim 1, wherein the buffer layer has a thickness of 1000 to 2000 angstroms.
6. The display substrate of claim 1, wherein the active layer has a thickness of 200 to 800 angstroms.
7. The display substrate according to claim 1 or 6, further comprising a gate insulating layer on the active layer, wherein the gate insulating layer has a thickness of 1000 to 2000 angstroms.
8. A display device, characterized in that the display device comprises a display substrate according to any one of claims 1 to 7.
9. A manufacturing method of a display substrate is characterized in that the display substrate comprises a storage capacitor formed by connecting at least two capacitors in parallel, and the manufacturing method comprises the following steps:
forming a shading layer and a planarization layer on a substrate, wherein the shading layer comprises a shading layer polar plate;
forming a buffer layer covering the planarization layer and the light-shielding layer;
and forming an active layer on the buffer layer, wherein the active layer comprises an active layer first polar plate, and the active layer first polar plate, the shading layer polar plate and the buffer layer between the active layer first polar plate and the shading layer polar plate form one capacitor of the storage capacitor.
10. The method for manufacturing a display substrate according to claim 9, further comprising:
sequentially forming an interlayer dielectric layer and a source drain layer on the active layer, wherein the source drain layer comprises a source drain layer polar plate;
the active layer first polar plate, the source drain polar plate and the interlayer dielectric layer positioned between the active layer first polar plate and the source drain polar plate form another capacitor of the storage capacitor; or the active layer further comprises an active layer second polar plate, and the active layer second polar plate, the source drain polar plate and the interlayer dielectric layer positioned between the active layer second polar plate and the source drain polar plate form the other capacitor of the storage capacitor.
11. The method of manufacturing a display substrate according to claim 9, wherein forming the light-shielding layer and the planarization layer on the base includes: depositing a layer of metal film on a substrate by adopting a magnetron sputtering process, patterning the deposited metal film by adopting a patterning process to form a light shielding layer, and coating a planarization material between adjacent light shielding layer polar plates by adopting a coating process to form a planarization layer;
or depositing a whole metal film on the substrate by adopting a magnetron sputtering process, covering the metal film by using a mask plate comprising a shading layer pattern, oxidizing the region of the metal film corresponding to the planarization layer, and forming an insulated planarization layer after oxidation; the non-oxidized region serves as a light-shielding layer.
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