KR20210004356A - Display device having an oxide semiconductor pattern - Google Patents

Abstract

The present invention relates to a display device in which a source region, a drain region, and a channel region of a thin film transistor are made of an oxide semiconductor. The source region, the drain region, and the channel region can be covered by a gate insulating layer. A gate electrode disposed on the gate insulating layer can include a hydrogen barrier material. The source region and the drain region can be made conductive by doping with hydrogen. Accordingly, in the display device according to the technical idea of the present invention, a change in characteristics of the thin film transistor due to a patterning process of the gate insulating layer can be prevented.

Description

Display device including an oxide semiconductor pattern TECHNICAL FIELD

The present invention relates to a display device in which a source region, a drain region, and a channel region of a thin film transistor are made of an oxide semiconductor.

In general, electronic devices such as monitors, TVs, notebook computers, and digital cameras include display devices that implement images. For example, the display device may include a liquid crystal display device including a liquid crystal and an organic light emitting display device including an organic emission layer.

The display device may include a plurality of pixels. Each pixel can represent a specific color. A driving circuit for generating a driving current according to a gate signal and a data signal may be positioned in each pixel. For example, the driving circuit may include at least one thin film transistor.

The thin film transistor may include a semiconductor pattern, a gate insulating layer, a gate electrode, a source electrode, and a drain electrode. The semiconductor pattern may include a channel region positioned between a source region and a drain region. The semiconductor pattern may include an oxide semiconductor. For example, the source region, the drain region, and the channel region of the thin film transistor may be formed of an oxide semiconductor.

The process of forming the thin film transistor may include a process of making the source region and the drain region conductive in order to lower the resistance of the source region and the drain region. For example, the source region and the drain region may be conductive by a process of patterning the gate insulating layer formed on the semiconductor pattern using the gate electrode. However, in the display device, characteristics of the thin film transistor may be degraded due to ion migration occurring in the patterning process of the gate insulating layer.

An object to be solved by the present invention is to provide a display device capable of preventing a decrease in characteristics of a thin film transistor due to a patterning process of a gate insulating layer, and a manufacturing method thereof.

Another problem to be solved by the present invention is to provide a display device capable of minimizing a change in characteristics of a channel region due to a conductive process of a source region and a drain region, and a method of manufacturing the same.

The problems to be solved by the present invention are not limited to the aforementioned problems. Tasks not mentioned herein will be clearly understood by those skilled in the art from the following description.

The display device according to the technical idea of the present invention for achieving the problem to be solved includes an oxide semiconductor pattern positioned on an element substrate. The oxide semiconductor pattern includes a channel region positioned between a source region and a drain region. A gate electrode is positioned on the channel region of the oxide semiconductor pattern. The gate electrode includes a hydrogen barrier material. A gate insulating layer is positioned between the oxide semiconductor pattern and the gate electrode. The gate insulating film extends over the source region and the drain region of the oxide semiconductor pattern. The resistance of the source region and the resistance of the drain region are lower than that of the channel region. The hydrogen content of the source region and the hydrogen content of the drain region are higher than that of the channel region.

The source region and the drain region may be formed of the same oxide semiconductor as the channel region.

The gate electrode may include a first region overlapping the channel region and a second region extending along a surface of the oxide semiconductor pattern from the first region. The thickness of the second region may be smaller than the thickness of the first region.

The first region and the second region of the gate electrode may contact the gate insulating layer.

The oxide semiconductor pattern may further include a source buffer region positioned between the source region and the channel region, and a drain buffer region positioned between the channel region and the drain region. The second region of the gate electrode may overlap the source buffer region and the drain buffer region of the oxide semiconductor pattern.

The hydrogen content of the source buffer region may be higher than the hydrogen content of the channel region and lower than the hydrogen content of the source region. The hydrogen content of the drain buffer region may be higher than the hydrogen content of the channel region and lower than the hydrogen content of the drain buffer region.

The hydrogen content ratio of the source buffer region and the source region and the hydrogen content ratio of the drain buffer region and the drain region may be in inverse proportion to the thickness of the second region.

The hydrogen barrier material may include titanium (Ti).

The gate electrode may include a first gate layer and a second gate layer sequentially stacked on the gate insulating layer. The horizontal width of the second gate layer may be smaller than the horizontal width of the first gate layer.

The horizontal width of the first gate layer may be greater than the horizontal width of the channel region.

The second gate layer may include a different material from the first gate layer.

The first gate layer may include a hydrogen barrier material. The electrical conductivity of the second gate layer may be higher than that of the first gate layer.

A display device according to the inventive concept includes a source region, a drain region, and a channel region in which a thin film transistor is made of an oxide semiconductor, and the source region and the drain region may be conductive by hydrogen doping. Accordingly, in the display device according to the technical idea of the present invention, a partial region of the oxide semiconductor pattern may be conductive without the patterning process of the gate insulating layer. Accordingly, in the display device according to the technical idea of the present invention, the reliability of the thin film transistor may be improved.

1 is a schematic diagram of a display device according to an exemplary embodiment of the present invention.
FIG. 2 is an enlarged view of area P of FIG. 1.
3 to 7 are views sequentially illustrating a method of manufacturing a display device according to an exemplary embodiment of the present invention.
8 and 9 are diagrams each illustrating a partial area of a display device according to another exemplary embodiment of the present invention.

Details of the object, technical configuration, and operational effects of the present invention will be more clearly understood by the following detailed description with reference to the drawings showing an embodiment of the present invention. Here, since the embodiments of the present invention are provided to sufficiently convey the technical idea of the present invention to those skilled in the art, the present invention may be embodied in other forms so as not to be limited to the embodiments described below.

In addition, throughout the specification, portions denoted by the same reference numerals denote the same components, and in the drawings, the length and thickness of a layer or region may be exaggerated for convenience. In addition, when it is described that the first component is "on" the second component, not only the first component is located on the upper side in direct contact with the second component, but also the first component and the It includes a case where a third component is positioned between the second component.

Here, the terms “first” and “second” are used to describe various constituent elements, and are used to distinguish one constituent element from other constituent elements. However, within the scope not departing from the technical idea of the present invention, the first component and the second component may be arbitrarily named for convenience of those skilled in the art.

Terms used in the specification of the present invention are used only to describe specific embodiments, and are not intended to limit the present invention. For example, a component expressed in the singular includes a plurality of components unless the context clearly means only the singular. In addition, in the specification of the present invention, terms such as "comprise" or "have" are intended to designate the presence of features, numbers, steps, actions, components, parts, or a combination thereof described in the specification, one or It is to be understood that no further features or possibilities of the presence or addition of numbers, steps, actions, components, parts, or combinations thereof are precluded.

In addition, unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by a person of ordinary skill in the art to which the present invention belongs. Terms as defined in a commonly used dictionary should be interpreted as having a meaning consistent with the meaning in the context of the related technology, and in an ideal or excessively formal meaning unless explicitly defined in the specification of the present invention. It is not interpreted.

(Example)

1 is a schematic diagram of a display device according to an exemplary embodiment of the present invention. FIG. 2 is an enlarged view of area P of FIG. 1.

1 and 2, a display device according to an embodiment of the present invention may include an element substrate 100. The device substrate 100 may include an insulating material. For example, the device substrate 100 may include glass or plastic.

A buffer insulating layer 110 may be positioned on the device substrate 100. The buffer insulating layer 110 may prevent contamination by the device substrate 100 in a subsequent process. The buffer insulating layer 110 may include an insulating material. For example, the buffer insulating layer 110 may include a silicon oxide (SiOx) material and/or a silicon nitride (SiNx) material. For example, silicon dioxide (SiO ₂ ) may be included as a silicon oxide-based (SiOx) material. The buffer insulating layer 110 may have a multilayer structure.

A thin film transistor 200 may be positioned on the buffer insulating layer 110. The thin film transistor 200 may generate a driving current according to a gate signal and a data signal. For example, the thin film transistor 200 includes an oxide semiconductor pattern 210, a gate insulating layer 220, a gate electrode 230, an interlayer insulating layer 240, a source electrode 250, and a drain electrode 260. can do.

The oxide semiconductor pattern 210 may be located close to the device substrate 100. For example, the oxide semiconductor pattern 210 may directly contact the buffer insulating layer 110. The oxide semiconductor pattern 210 may be formed of an oxide semiconductor. For example, the oxide semiconductor pattern 210 may include a metal oxide such as IGZO.

The oxide semiconductor pattern 210 may include a source region 210S, a drain region 210D, and a channel region 210C. Resistance of the source region 210S and the resistance of the drain region 210D may be lower than that of the channel region 210C. For example, the source region 210S and the drain region 210D may be conductive. The source region 210S and the drain region 210D may be conductive by doping with hydrogen. For example, the source region 210S and the drain region 210D may have a hydrogen content higher than that of the channel region 210C.

The gate insulating layer 220 may be positioned on the oxide semiconductor pattern 210. The gate insulating layer 220 may extend outside the oxide semiconductor pattern 210. For example, a side surface of the oxide semiconductor pattern 210 may be covered by the gate insulating layer 220. The source region 210S, the drain region 210D, and the channel region 210C of the oxide semiconductor pattern 210 may be covered by the gate insulating layer 220.

The gate insulating layer 220 may include an insulating material. For example, the gate insulating layer 220 may include a silicon oxide (SiOx) material and/or a gate nitride (SiNx) material. The gate insulating layer 220 may include a material having a high dielectric constant (High-K material). For example, the gate insulating layer 220 may include a hafnium oxide (HfOx) material or a titanium oxide (TiOx) material. For example, the hafnium oxide-based (HfOx) material may include hafnium dioxide (HfO ₂ ). The gate insulating layer 220 may have a multilayer structure.

The gate electrode 230 may be positioned on the gate insulating layer 220. The gate electrode 230 may overlap the channel region 210C of the oxide semiconductor pattern 210. For example, the gate electrode 230 may be insulated from the oxide semiconductor pattern 210 by the gate insulating layer 220.

The gate electrode 230 may include a conductive material. The gate electrode 230 may include a hydrogen barrier material. The hydrogen barrier material may include a hydrogen storage material and a hydrogen barrier material. For example, the gate electrode 230 may include titanium (Ti) or tantalum (Ta).

The interlayer insulating layer 240 may be positioned on the gate insulating layer 220 and the gate electrode 230. The interlayer insulating layer 240 may include an insulating material. For example, the interlayer insulating layer 134 may include a silicon oxide-based material.

The source electrode 250 may be positioned on the interlayer insulating layer 240. The source electrode 250 may be electrically connected to the source region 210S of the oxide semiconductor pattern 210. For example, the interlayer insulating layer 240 may include a source contact hole 241h exposing a partial region of the source region 210S of the oxide semiconductor pattern 210. The source electrode 250 may include a region overlapping the source region 210S of the oxide semiconductor pattern 210.

The source electrode 250 may include a conductive material. For example, the source electrode 250 may include metals such as aluminum (Al), chromium (Cr), molybdenum (Mo), tungsten (W), and copper (Cu).

The drain electrode 260 may be positioned on the interlayer insulating layer 240. The drain electrode 260 may be spaced apart from the source electrode 250. The drain electrode 260 may be electrically connected to the drain region 210D of the oxide semiconductor pattern 210. For example, the interlayer insulating layer 240 may include a drain contact hole 242h exposing a partial region of the drain region 210D of the oxide semiconductor pattern 210. The drain electrode 260 may include a region overlapping the drain region 210D of the oxide semiconductor pattern 210.

The drain electrode 260 may include a conductive material. For example, the drain electrode 260 may include a metal such as aluminum (Al), chromium (Cr), molybdenum (Mo), tungsten (W), and copper (Cu). The drain electrode 260 may include the same material as the source electrode 250.

A lower passivation layer 120 may be positioned on the thin film transistor 200. The lower protective layer 120 may prevent damage to the thin film transistor 200 due to external impact and moisture. The lower passivation layer 120 may extend to the outside of the source electrode 250 and the drain electrode 260. The thin film transistor 200 may be completely covered by the lower protective layer 120. The lower passivation layer 120 may include an insulating material. For example, the lower passivation layer 120 may include silicon nitride.

An overcoat layer 130 may be positioned on the lower passivation layer 120. The overcoat layer 130 may remove a step difference generated by the thin film transistor 200. For example, a surface of the overcoat layer 130 facing the device substrate 100 may be a flat plane. The overcoat layer 130 may extend along the lower passivation layer 120 to completely cover the thin film transistor 200.

The overcoat layer 130 may include an insulating material. The overcoat layer 130 may include a material different from the lower passivation layer 120. The overcoat layer 130 may include a material having relatively high fluidity. For example, the overcoat layer 130 may include an organic insulating material.

A light emitting device 300 may be positioned on the overcoat layer 130. The light-emitting device 300 may emit light having a specific color. For example, the light-emitting element 300 may include a first electrode 310, a light-emitting layer 320, and a second electrode 330 stacked in order.

The first electrode 310 may include a conductive material. The first electrode 310 may include a metal having a relatively high reflectivity. The first electrode 310 may have a multilayer structure. For example, the first electrode 310 may have a structure in which a reflective electrode formed of a metal such as aluminum (Al) and silver (Ag) is positioned between transparent electrodes formed of a transparent conductive material such as ITO and IZO. .

The first electrode 310 may be electrically connected to the thin film transistor 200. For example, the lower passivation layer 120 and the overcoat layer 130 may include a pixel contact hole 130h partially exposing the drain electrode 260 of the thin film transistor 200. The first electrode 310 may include a region overlapping the drain electrode 260. Accordingly, in the display device according to the exemplary embodiment of the present invention, the driving current generated by the thin film transistor 200 may be supplied to the light emitting element 300. Accordingly, in the display device according to the exemplary embodiment of the present invention, the light emitting element 300 may be controlled by the thin film transistor 200.

The emission layer 320 may generate light having a luminance corresponding to a voltage difference between the first electrode 310 and the second electrode 330. For example, the light-emitting layer 320 may include a light-emitting material layer EML containing a light-emitting material. The light-emitting material may include an organic material, an inorganic material, or a hybrid material. For example, the display device according to the technical idea of the present invention may be an organic light emitting display device including an emission layer 320 formed of an organic material.

The emission layer 320 may have a multilayer structure in order to increase luminous efficiency. For example, the emission layer 320 may further include at least one of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL).

The second electrode 330 may include a conductive material. The second electrode 330 may include a material different from that of the first electrode 310. For example, the second electrode 330 may be a transparent electrode formed of a transparent conductive material such as ITO and IZO. Accordingly, in the display device according to the exemplary embodiment of the present invention, light generated by the emission layer 320 may be emitted to the outside through the second electrode 330.

A bank insulating layer 140 may be positioned on the overcoat layer 130. The bank insulating layer 140 may cover an edge of the first electrode 310. The emission layer 320 and the second electrode 330 may be stacked on a partial area of the first electrode 310 exposed by the bank insulating layer 140. The emission layer 320 and the second electrode 330 may extend onto the bank insulating layer 140.

The bank insulating layer 140 may include an insulating material. For example, the bank insulating layer 140 may include an organic insulating material. The bank insulating layer 140 may include a material different from the overcoat layer 130. Accordingly, in the display device according to the exemplary embodiment of the present invention, the first electrode 310 of each light emitting device 300 is insulated from the first electrode 310 of the adjacent light emitting device 300 by the bank insulating layer 140. Can be. Accordingly, in the display device according to the exemplary embodiment of the present invention, each light emitting element 300 may be independently controlled by the corresponding thin film transistor 200.

An encapsulation member 400 may be positioned on the light emitting device 300. The sealing member 400 may prevent damage to the light emitting device 300 due to external impact and moisture. The encapsulation member 400 may have a multilayer structure. For example, the encapsulation member 400 may include a first encapsulation layer 410, a second encapsulation layer 420, and a third encapsulation layer 430 sequentially stacked on the light emitting device 300. have.

The first encapsulation layer 410, the second encapsulation layer 420 and the third encapsulation layer 430 may include an insulating material. The second encapsulation layer 420 may include a material different from the first encapsulation layer 410 and the third encapsulation layer 430. For example, the first encapsulation layer 410 and the third encapsulation layer 430 may be an inorganic insulating layer formed of an inorganic insulating material, and the second encapsulation layer 420 may be an organic insulating layer formed of an organic insulating material. . Accordingly, in the display device according to the exemplary embodiment of the present invention, a step due to the light emitting element 300 may be removed by the second encapsulation layer 420. For example, in the display device according to an embodiment of the present invention, a surface of the encapsulation member 400 facing the device substrate 100 may be a flat plane.

3 to 7 are views sequentially illustrating a method of manufacturing a display device according to an exemplary embodiment of the present invention.

A method of manufacturing a display device according to an exemplary embodiment of the present invention will be described with reference to FIGS. 1 to 7. First, as shown in FIG. 3, a method of manufacturing a display device according to an embodiment of the present invention includes a process of forming a buffer insulating layer 110 on a device substrate 100 and an oxide pattern on the buffer insulating layer 110. It may include a step of forming (211).

The process of forming the buffer insulating layer 110 may include a deposition process of coating an insulating material on the device substrate 100. The oxide pattern 211 may include a process of forming an oxide semiconductor layer on the buffer insulating layer 110 and a process of patterning the oxide semiconductor layer. The process of forming the oxide semiconductor layer may include a process of forming a metal oxide layer such as IGZO on the buffer insulating layer 110. Accordingly, the method of manufacturing a display device according to an embodiment of the present invention can prevent the oxide pattern 211 from being contaminated by the device substrate 100.

As shown in FIG. 4, in the display device according to an exemplary embodiment of the present invention, a process of forming a gate insulating layer 220 covering the oxide pattern 211 and forming a gate electrode 230 on the gate insulating layer 220 It may include a forming process.

The gate electrode 230 may be formed of a hydrogen barrier material. For example, the process of forming the gate electrode 230 may include a process of forming a hydrogen barrier material layer on the gate insulating layer 220 and a process of patterning the hydrogen barrier material layer.

The gate electrode 230 may overlap a partial region of the oxide pattern 211. Both ends of the oxide pattern 211 may not overlap the gate electrode 230. For example, a partial region of the oxide pattern 211 overlapping the gate electrode 230 may be located between regions of the oxide pattern 211 that do not overlap the gate electrode 230.

As shown in FIG. 5, the display device according to an exemplary embodiment of the present invention may include a process of forming an oxide semiconductor pattern 210 using the gate electrode 230.

The oxide semiconductor pattern 210 may include a channel region 210C positioned between the source region 210S and the drain region 210D. The channel region 210C may overlap the gate electrode 230. Resistance of the source region 210S and the resistance of the drain region 210D may be lower than that of the channel region 210C. For example, the process of forming the oxide semiconductor pattern 210 may include conducting a process of conducting regions of the oxide pattern 211 that do not overlap with the gate electrode 230.

The conducting process may include a process of doping hydrogen (H) in the corresponding region. For example, the process of forming the oxide semiconductor pattern 210 may include exposing the device substrate 100 on which the gate electrode 230 is formed to hydrogen plasma. Hydrogen may not be doped in a portion of the oxide pattern 211 that overlaps the gate electrode 230 including a hydrogen barrier material. For example, the channel region 210C may have the same horizontal width W1 as the gate electrode 230. The source region 210S and the drain region 210D may not overlap the gate electrode 230. The source region 210S and the drain region 210D may include a hydrogen content higher than that of the channel region 210C. Accordingly, in the display device according to the exemplary embodiment of the present invention, the source region 210S and the drain region 210D may be formed without the patterning process of the gate insulating layer 220. In addition, in the display device according to the exemplary embodiment of the present invention, by using the gate electrode 230 as a mask to perform a conductive process, a decrease in process efficiency due to the addition of a mask may be prevented. For example, in the process of converting the oxide pattern 211 into a conductor through hydrogen plasma treatment, a region of the oxide pattern 211 overlapping the gate electrode 230 is formed by the gate electrode 230 formed of a hydrogen barrier material. Penetration of hydrogen (H) into the oxide pattern 211 may be prevented. In addition, a region of the oxide pattern 211 that does not overlap with the gate electrode 230 may be formed as a source region 210S and a drain region 210D through hydrogen plasma treatment. Also, a region of the oxide pattern 211 overlapping the gate electrode 230 may be formed as a channel region 210C. The gate electrode 230 preferably includes a hydrogen barrier material capable of blocking penetration of hydrogen (H) into the channel region 210C by a hydrogen plasma treatment process. The hydrogen barrier material may include titanium (Ti) or tantalum (Ta). The hydrogen barrier material may mean a material capable of storing or trapping hydrogen by forming a stable bond with hydrogen. Due to such characteristics, a layer made of a hydrogen barrier material may serve to prevent diffusion and penetration of hydrogen into other areas.

6, the display device according to the embodiment of the present invention is to form an interlayer insulating layer 240 on the device substrate 100 on which the oxide semiconductor pattern 210 and the gate electrode 230 are formed. Process and a source contact hole 241h exposing a partial region of the source region 210S and a drain contact exposing a partial region of the drain region 210D in the device substrate 100 on which the interlayer insulating layer 240 is formed A process of forming the hole 242h may be included.

The drain contact hole 242h may be formed simultaneously with the source contact hole 241h. For example, the process of forming the source contact hole 241h and the drain contact hole 242h includes a partial region of the source region 210S and a portion of the drain region 210D on the interlayer insulating layer 240. A process of forming a mask pattern exposing an area and a process of sequentially etching the interlayer insulating layer 240 and the gate insulating layer 220 using the mask pattern may be included.

7, the display device according to the exemplary embodiment of the present invention includes a source electrode 250 and a drain on the device substrate 100 on which the source contact hole 241h and the drain contact hole 242h are formed. A process of forming the electrode 260 may be included.

The drain electrode 260 may be formed together by the same mask process as the source electrode 250. For example, in the process of forming the source electrode 250 and the drain electrode 250, the device on the interlayer insulating layer 240 is formed through the source contact hole 241h and the drain contact hole 242h. A process of forming a conductive layer in contact with the oxide semiconductor pattern 210 and a process of patterning the conductive layer may be included.

1 and 2, the display device according to the exemplary embodiment of the present invention includes the oxide semiconductor pattern 210, the gate insulating layer 220, the gate electrode 230, the interlayer insulating layer 240, and the A process of forming a lower protective layer 120 on the device substrate 100 on which the thin film transistor 200 including the source electrode 250 and the drain electrode 260 is formed, overcoating the lower protective layer 120 A process of forming a layer 130, a process of forming a light emitting device 300 electrically connected to the thin film transistor 200 on the overcoat layer 130, and an encapsulation layer on the light emitting device 300 ( 400) may be included.

The forming of the light emitting device 300 includes forming a pixel contact hole 130h exposing a partial region of the drain electrode 260 on the device substrate 100 on which the overcoat layer 130 is formed, A process of forming a first electrode 310 connected to the thin film transistor 200 through the pixel contact hole 130h, and a process of forming a bank insulating layer 140 covering the edge of the first electrode 310 , A process of sequentially stacking the light emitting layer 320 and the second electrode 320 on a partial region of the first electrode 310 exposed by the bank insulating layer 140.

The process of forming the encapsulation layer 400 includes a first encapsulation layer 410, a second encapsulation layer 420 and a third encapsulation layer 430 on the device substrate 100 on which the light emitting device 300 is formed. It may include a process of forming in order.

As a result, the display device and the method of manufacturing the same according to the exemplary embodiment of the present invention use the gate electrode 230 including a hydrogen barrier material as a mask, without patterning the gate insulating layer 220, and doping with hydrogen to form oxides. The source region 210S and the drain region 210D of the semiconductor pattern 210 may be formed. Accordingly, it is possible to prevent deterioration of characteristics of the thin film transistor 200 due to the patterning process of the gate insulating layer 220. When the gate electrode 230 does not include a hydrogen barrier material, for example, when the gate electrode 230 includes a metal such as molybdenum (Mo), the hydrogen plasma treatment process cannot be performed without a separate mask. Accordingly, through a dry etching process of patterning the gate insulating layer 220, a partial region of the oxide pattern 211 may be made into a conductor. In addition, a source region 210S and a drain region 210D of the oxide semiconductor pattern 210 may be formed. As described above, in the dry etching process of patterning the gate insulating layer 220, the thin film transistor 200 is caused by the movement of indium at the interface between the oxide semiconductor pattern 210 and the gate insulating layer 220. ) May deteriorate.

In addition, in the display device and its manufacturing method according to an exemplary embodiment of the present invention, since the gate electrode 230 is formed of a hydrogen barrier material, it can be used as a mask in a hydrogen plasma treatment process for hydrogen doping. Accordingly, the process of forming the source region 210S and the drain region 210D may be performed without a separate mask. Accordingly, in the display device according to an exemplary embodiment of the present invention, reliability of the thin film transistor 200 may be improved without deteriorating process efficiency.

A display device according to an exemplary embodiment of the present invention is described as including a light emitting element. However, the display device according to another embodiment of the present invention may include a liquid crystal. For example, the display device according to another embodiment of the present invention may be a liquid crystal display device in which a pixel electrode electrically connected to a thin film transistor is positioned on a lower passivation layer, and a liquid crystal layer is positioned on the pixel electrode.

In the display device according to the exemplary embodiment of the present invention, it is described that the gate electrode 230 has a constant thickness. However, as shown in FIG. 8, in the display device according to another exemplary embodiment of the present invention, the gate electrode 230 has a first region 231 and a second region having a thickness thinner than that of the first region 231 ( 232) may be included. The second region 232 may have a shape extending along the surfaces of the oxide semiconductor patterns 210C, 210S, 210D, 211 and 212 from the first region 231. For example, the first region 231 and the second region 232 of the gate electrode 230 may directly contact the gate insulating layer 220. The horizontal width W2 of the second region 232 may be smaller than the horizontal width W1 of the first region 231. The gate electrode 230 may have a stepped portion. For example, the first region 231 of the gate electrode 230 may be a region having a first thickness. In addition, the second region 232 of the gate electrode 230 may be a region having a second thickness smaller than the first thickness. In addition, the second region 232 of the gate electrode 230 may have a shape extending along the surfaces of the oxide semiconductor patterns 210C, 210S, 210D, 211 and 212 from both sides of the first region 231. The first region 231 of the gate electrode 230 may have the same horizontal width W1 as the channel region 210C of the oxide semiconductor patterns 210C, 210S, 210D, 211, and 212. The source region 210S and the drain region 210D of the oxide semiconductor patterns 210C, 210S, 210D, 211, and 212 may not overlap the gate electrode 230. For example, the oxide semiconductor patterns 210C, 210S, 210D, 211, 212 may include a drain buffer region 211 and the source region 210S positioned between the channel region 210C and the drain region 210D. And a source buffer region 212 positioned between the channel region 210C. The second region 232 of the gate electrode 230 may overlap the drain buffer region 211 and the source buffer region 212. For example, the drain buffer region 211 and the source buffer region 212 may each have the same horizontal width W2 as the second region 232 of the gate electrode 230.

The second region 232 of the gate electrode 230 may block some of the hydrogen doped in the process of forming the source region 210S and the drain region 210D. For example, the hydrogen content of the drain buffer region 211 may be higher than the hydrogen content of the channel region 210C and lower than the hydrogen content of the drain region 210D. The hydrogen content of the source buffer region 212 may be higher than that of the channel region 210C and lower than the hydrogen content of the source region 210S. Accordingly, in the display device according to another embodiment of the present invention, the channel region 210C is prevented from being reduced by diffusion of doped hydrogen to form the source region 210S and the drain region 210D. I can. The source buffer region 212 and the drain buffer region 211 may suppress diffusion of hydrogen doped into the source region 210S and the drain region 210D and penetrating into the channel region 210C. .

The difference between the hydrogen content of the source buffer region 212 and the source region 210S and the difference between the hydrogen content of the drain buffer region 211 and the drain region 210D are determined by the thickness of the second region 232 and It can be inversely proportional. For example, as the thickness of the second region 232 increases, the difference between the hydrogen content of the source buffer region 212 and the source region 210S and the hydrogen content of the drain buffer region 211 and the drain region 210D The difference in content can be reduced. Conversely, as the thickness of the second region 232 decreases, the difference between the hydrogen content of the source buffer region 212 and the source region 210S and the hydrogen content of the drain buffer region 211 and the drain region 210D The difference can be large.

The first region 231 and the second region 232 of the gate electrode 230 may be formed by the same mask process. For example, the forming process of the gate electrode 230 includes forming a hydrogen barrier material layer on the gate insulating layer 220 and forming the hydrogen barrier material layer into the first region 231 and the halftone mask. A process of patterning to include the second region 232 may be included. Accordingly, in the display device and the method of manufacturing the same according to another exemplary embodiment of the present invention, a decrease in process efficiency due to the addition of a mask may be prevented.

In the display device according to the exemplary embodiment of the present invention, the gate electrode 230 is described as having a single layer. However, in the display device according to another embodiment of the present invention, the gate electrode 230 may have a multilayer structure. For example, as shown in FIG. 9, in the display device according to another exemplary embodiment of the present invention, the gate electrode 230 is sequentially stacked on the gate insulating layer 220, the first gate layer 233 and the second A gate layer 234 may be included. The second gate layer 234 may include a different material from the first gate layer 233. For example, the second gate layer 234 may have an electrical conductivity higher than that of the first gate layer 233. Accordingly, in the display device according to another exemplary embodiment of the present invention, conduction of the channel region 210C due to hydrogen doping is prevented, and the resistance of the gate electrode 230 may be sufficiently lowered.

The first gate layer 233 may include a hydrogen barrier material capable of blocking penetration of hydrogen (H). The hydrogen barrier material may include titanium (Ti) or tantalum (Ta). In addition, the second gate layer 234 may be a material having an electrical conductivity higher than that of the first gate layer 233. For example, it may be one of a material such as molybdenum (Mo), aluminum (Al), chromium (Cr), tungsten (Wo), and copper (Cu). Alternatively, it may be a molybdenum-titanium alloy (Mo-Ti).

A thickness of the first gate layer 233 and a thickness of the second gate layer 234 may be formed differently. The thickness of the second gate layer 234 may be greater than the thickness of the first gate layer 233.

The first gate layer 233 may have a horizontal width different from that of the second gate layer 234. For example, the first gate layer 233 may have a larger horizontal width than the second gate layer 234. The second gate layer 234 may overlap the channel region 210C. For example, the second gate layer 234 may have the same horizontal width W1 as the channel region 210C. The oxide semiconductor patterns 210C, 210S, 210D, 211, and 212 are formed from a drain buffer region 211 and a source buffer region 212 overlapping the first gate layer 233 outside the second gate layer 234 It may include. The horizontal width of the first gate layer 233 may be greater than the horizontal width of the channel region 210C.

Accordingly, in the display device according to another embodiment of the present invention, the resistance of the gate electrode 230 is sufficiently lowered, and the channel region 210C is prevented from being reduced by diffusion of doped hydrogen for the conductorization process. I can. The source buffer region 212 and the drain buffer region 211 can suppress diffusion of hydrogen doped into the source region 210S and the drain region 210D and penetrating into the channel region 210C. have. In addition, without patterning the gate insulating layer 220, the oxide semiconductor pattern 210 is formed by doping hydrogen using the first gate layer 233 of the gate electrode 230 including a hydrogen barrier material as a mask. A source region 210S and a drain region 210D may be formed. In addition, by improving the electrical conductivity through the second gate layer 234 including a metal having a lower resistance than the first gate layer 233, it is possible to prevent the characteristics of the thin film transistor from deteriorating.

100: device substrate 200: thin film transistor
210: oxide semiconductor pattern 210S: source region
210D: drain region 210C: channel region
220: gate insulating film 230: gate electrode
300: light emitting element

Claims (14)

An oxide semiconductor pattern positioned on the device substrate and including a channel region positioned between a source region and a drain region;
A gate electrode overlapping the channel region of the oxide semiconductor pattern and including a hydrogen barrier material; And
A gate insulating layer positioned between the oxide semiconductor pattern and the gate electrode and extending onto the source region and the drain region of the oxide semiconductor pattern,
The resistance of the source region and the resistance of the drain region are lower than that of the channel region,
The source region and the drain region have a higher hydrogen content than the channel region. The method of claim 1,
The source region and the drain region are formed of the same oxide semiconductor as the channel region. The method of claim 1,
The gate electrode includes a first region overlapping the channel region and a second region extending from the first region along a surface of the oxide semiconductor pattern,
The thickness of the second area is smaller than the thickness of the first area. The method of claim 3,
The first region and the second region of the gate electrode contact the gate insulating layer. The method of claim 3,
The oxide semiconductor pattern further includes a source buffer region positioned between the source region and the channel region, and a drain buffer region positioned between the channel region and the drain region,
The second region of the gate electrode overlaps the source buffer region and the drain buffer region of the oxide semiconductor pattern. The method of claim 5,
The source buffer region has a higher hydrogen content than the channel region and lower than the source region,
The drain buffer region is higher than the channel region and has a lower hydrogen content than the drain buffer region. The method of claim 5,
A display device wherein a difference between the hydrogen content of the source buffer region and the source region, and a difference between the hydrogen content of the drain buffer region and the drain region are in inverse proportion to the thickness of the second region. The method of claim 1,
The hydrogen barrier material includes titanium (Ti) or tantalum (Ta). The method of claim 1,
The gate electrode includes a first gate layer and a second gate layer sequentially stacked on the gate insulating layer,
A display device in which a horizontal width of the second gate layer is smaller than a horizontal width of the first gate layer. The method of claim 9,
A display device in which a horizontal width of the first gate layer is greater than a horizontal width of the channel region. The method of claim 9,
The second gate layer includes a material different from that of the first gate layer. The method of claim 11,
The first gate layer includes a hydrogen barrier material, and an electrical conductivity of the second gate layer is higher than that of the first gate layer. The method of claim 11,
The thickness of the second gate layer is greater than that of the first gate layer. The method of claim 13,
The first gate layer includes titanium (Ti) or tantalum (Ta),
The second gate layer includes one of molybdenum (Mo), aluminum (Al), chromium (Cr), tungsten (Wo), copper (Cu), and molybdenum-titanium alloy (Mo-Ti).

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