CN107275372B - Display panel and image display system using same - Google Patents
Display panel and image display system using same Download PDFInfo
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- CN107275372B CN107275372B CN201710343540.3A CN201710343540A CN107275372B CN 107275372 B CN107275372 B CN 107275372B CN 201710343540 A CN201710343540 A CN 201710343540A CN 107275372 B CN107275372 B CN 107275372B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
- G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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Abstract
An embodiment of the present invention provides a display panel, including: a substrate including a pixel region and a peripheral region; a control element located on the substrate of the pixel region; a conductive layer on the substrate in the peripheral region; a first insulating layer on the conductive layer in the peripheral region, wherein an area ratio of the first insulating layer to the conductive layer in the peripheral region is between about 0.27 and 0.99; a lower electrode layer on the first insulating layer; and a second insulating layer on the lower electrode layer.
Description
The present application is a divisional application of patent applications having an application date of 2009, 23/4, application No. 201310514617.0, and an invention name of "display panel and image display system using the same".
Technical Field
The present invention relates to a display panel, and more particularly, to an active organic light emitting diode panel and an image display system using the same.
Background
Active light emitting devices, such as light emitting diodes and organic light emitting diodes, are widely used in flat panel displays. Among them, an active matrix organic electroluminescent diode (AM-OLED) is gaining attention because of its characteristics such as thin volume, light weight, high self-luminous efficiency, low power consumption, wide viewing angle, high contrast, high response speed, and full color.
In an AMOLED panel, a wide (e.g., greater than 100 μm) and long metal line (metaltrack) is used as a power line around the peripheral area of the panel to provide power for display. The metal lines in the peripheral region may be formed in the same layer as the electrode layer (anode or cathode) in the pixel region, and the metal lines in the peripheral region have a relatively wide width or a relatively large area, so that the difference between the surface morphology (topograph) of the metal lines in the peripheral region and the surface morphology of the electrode layer in the pixel region is very large, for example, the surface roughness of the metal lines in the peripheral region is insufficient, which may affect the quality of the subsequently formed material layer, for example, the thickness of the insulating layer formed above the metal lines in the peripheral region is too thin, which may cause a short circuit between two metal lines above and below the insulating layer, thereby seriously affecting the operation of the display panel. Furthermore, since the metal lines in the peripheral region have a relatively large area, excessive stress is easily generated.
Therefore, there is a need for a display panel that can improve the quality of the display panel.
Disclosure of Invention
An embodiment of the present invention provides a display panel, including: a substrate including a pixel region and a peripheral region; a control element located on the substrate of the pixel region; a conductive layer on the substrate in the peripheral region; a first insulating layer on the conductive layer in the peripheral region, wherein an area ratio of the first insulating layer to the conductive layer in the peripheral region is between about 0.27 and 0.99; a lower electrode layer on the first insulating layer; and a second insulating layer on the lower electrode layer.
Another embodiment of the present invention provides an image display system, which includes a display device, wherein the display device includes the display panel.
Drawings
FIGS. 1A-1E illustrate a series of process cross-sectional views of a display panel according to one embodiment of the present invention;
FIGS. 2A-2D are top views of insulating layers on conductive layers in a peripheral region, in accordance with various embodiments of the present invention;
FIG. 3 is a partial top view of a display panel according to an embodiment of the invention;
fig. 4 shows a schematic diagram of an image display system according to an embodiment of the invention.
Description of the main elements
1-pixel area;
2-peripheral area;
100-substrate;
102-an active layer;
104. 106a, 106b, 106c dielectric layers;
106d, 106 e-openings;
T1、T2transistor；
C-capacitance;
111-contact openings;
112-conducting layer;
113-a first trench;
115 to a second groove;
108 to a first insulating layer;
114-lower electrode layer;
110 to a second insulating layer;
118 to a light emitting layer;
116 — an upper electrode layer;
119 to an opening of the first insulating layer;
121-a recess;
123-bulge structure;
t1, t3 to the thickness of the second insulating layer 110;
400-a display panel;
600-a display device;
700-input device;
800-electronic device.
Detailed Description
The display panel of the embodiment of the invention changes the surface form of the conductive circuit by the design or layout of the opening in the insulating layer below the conductive circuit such as metal in the formed peripheral area, thereby ensuring that the subsequently formed insulating layer has enough thickness, and avoiding the short circuit between the upper electrode layer and the lower electrode layer which are used as the conductive circuit in the peripheral area.
Fig. 1A-1E show process cross-sectional views of a display panel according to an embodiment of the invention. FIG. 3 is a partial top view of a display panel according to an embodiment of the invention, wherein cross-sections of the cross-sectional lines A-A' are shown in FIGS. 1A-1D, and further, for simplicity of illustration, details of the pixel area are not shown in the top view of FIG. 3.
First, as shown in fig. 1A, a substrate 100 having a pixel region 1 and a peripheral region 2 is provided. In one embodiment, a buffer layer (not shown) may be formed on the substrate 100, and the material thereof may be, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. Then, through the conventional methodThe method forms an active layer 102, a dielectric layer 104, a gate electrode, and a capacitor top electrode on a substrate 100 to form a control element of a panel, such as a transistor T1、T2And a capacitor C, and forming dielectric layers 106a and 106b on the above elements. The dielectric layers 106a and 106b may be silicon oxide, silicon nitride, silicon oxynitride, a stack thereof, or a combination thereof. The active layer 102 may be doped with desired impurities as desired by selective implantation to form source, drain, and capacitor bottom electrode regions, for example. In other embodiments, the lightly doped region may be formed first, and then the gate electrode may be defined and then heavily doped to form lightly doped source/drain regions on both sides of the channel region. Next, the dielectric layers 104, 106a, and 106b are patterned to form exposed transistors T1Source region and transistor T2Openings 106d and 106e of the drain region.
Next, referring to fig. 1B and fig. 3, a conductive material deposition and selective etching step is performed to form a conductive layer 112 on the substrate 100 in the pixel region 1 and the peripheral region 2, wherein the conductive layer 112 in the pixel region 1 is filled in and exposes the transistor T1Source region and transistor T2Openings 106d and 160e of the drain region (see fig. 1A) and transistor T1And a transistor T2The electrical connection is used as a data line. On the other hand, the conductive layer 112 in the peripheral region 2 is formed on the substrate 100, and the conductive layer 112 in the peripheral region 2 may have a first trench 113 therein, where the first trench 113 is helpful to release a high stress generated by a large area of the conductive layer 112 in the peripheral region 2, and in addition, the photoresist removing capability in the process may be increased. It is noted that the first trenches 113 are not limited to the pattern and distribution shown in fig. 3.
Referring to fig. 1C and fig. 3, an insulating material forming and selective etching step is performed to form a first insulating layer 108 on the conductive layer 112 in the peripheral region 2, and the first insulating layer 108 is also formed on the substrate 100 in the pixel region 1, wherein the first insulating layer 108 in the pixel region 1 has a contact opening 111 for exposing the conductive layer 112 as a data line. It is noted that the first insulating layer 108 in the peripheral region 2 has at least one opening 119 exposing the conductive layer 112, such that the first insulating layer 108 presents rectangular islands separated from each other (as shown in the top view of fig. 3), and the area ratio of the first insulating layer 108 in the peripheral region 2 to the conductive layer 112 thereunder is between about 0.27 and 0.99, preferably between 0.67 and 0.80. The first insulating layer 108 of the present embodiment is formed by coating an organic insulating material by spin coating, and then performing photolithography and etching steps. In one embodiment, the first insulating layer 108 in the peripheral region 2 fills the first trench 113 in the conductive layer 112.
In one embodiment, before forming the first insulating layer 108, a dielectric layer 106c may be formed on the dielectric layer 106b of the pixel region 1.
Next, referring to fig. 1D and fig. 3, a conductive material deposition and selective etching step is performed to conformably form a lower electrode layer 114 on the first insulating layer 108 in the pixel region 1 and the peripheral region 2, where the lower electrode layer 114 may be formed of at least one metal layer and/or other conductive layers, and the lower electrode layer 114 in the pixel region 1 is filled into the contact opening 111 (as shown in fig. 1C) exposing the conductive layer 112 and electrically connected to the conductive layer 112 serving as a data line. The lower electrode layer 114 in the peripheral region 2 is conformally formed on the first insulating layer 108, and has at least one recess 121. Furthermore, the lower electrode layer 114 in the peripheral region 2 and the conductive layer 112 therebelow are used together as a conductive line such as a power line, which has a relatively wide line width and a relatively large area.
It should be noted that, since the first insulating layer 108 in the peripheral region 2 has the opening 119, the upper surface of the compliantly formed lower electrode layer 114 has the recess 121 corresponding to the position of the opening 119, the width w of the recess 121 is between about 2.5 μm and 300 μm, the interval b is between about 20 μm and 80 μm, and the depth d is greater than 0.08-0.30 μm, and preferably about 0.1 μm. In summary, the upper surface of the lower electrode layer 114 in the peripheral region 2 has a protrusion 123 due to the recess 121 corresponding to the opening 119 (see fig. 1C).
Furthermore, in one embodiment, the surface roughness of the upper surface of the lower electrode layer 114 in the peripheral region 2 is between about 5% and 40%, and in another embodiment, the surface roughness of the lower electrode layer 114 is between about 10% and 30%. In yet another embodiment, the surface roughness of the bottom electrode layer 114 is between about 15% and 25%. Here, the surface roughness is defined as a value obtained by dividing the total area of the upper surface and the side surface of the protrusion structure 123 of the lower electrode layer 114 by the projected area of the entire lower electrode layer 114. That is, the ratio of the area occupied by the upper surface and the side surface of the protrusion structure 123.
Since the line width of the bottom electrode layer 114 in the peripheral region 2 is larger (the area is larger) and has higher stress, in an embodiment, the bottom electrode layer 114 in the peripheral region 2 may define a second trench 115, and the second trench 115 is helpful for releasing the higher stress generated by the large area of the bottom electrode layer 114 in the peripheral region 2.
Next, referring to fig. 1E, an organic insulating material is coated on the lower electrode layer 114 in the pixel region 1 and the peripheral region 2 by, for example, a spin coating method, and then a photolithography and an etching step are performed to selectively etch the organic insulating material, so as to form the second insulating layer 110. The second insulating layer 110 of the pixel region 1 has an opening exposing the lower electrode layer 114 to serve as a Pixel Definition Layer (PDL). It should be noted that, due to the design of the opening 119 of the first insulating layer 108 in the peripheral region 2, the area ratio of the first insulating layer 108 in the peripheral region 2 to the conductive layer 112 thereunder is between about 0.27 and 0.99, and the subsequently formed recess 121 with a specific size and spacing is further formed on the upper surface of the lower electrode layer 114, in other words, the lower electrode layer 114 has a specific surface roughness, so that a sufficient amount of organic insulating material can be easily retained during the spin coating process of the second insulating layer 110, and the second insulating layer 110 in the peripheral region 2 has a sufficient thickness t3, for example, between about 1.5 μm and 3 μm, and preferably, between about 2.0 μm and 2.6 μm.
In an embodiment, the thickness t1 of the second insulating layer 110 formed in the pixel region 1 and the thickness t3 of the second insulating layer 110 in the peripheral region 2 are equal, or the thicknesses of the second insulating layers 110 in the pixel region 1 and the peripheral region 2 are slightly different.
Then, the light emitting layer 118 and the upper electrode layer 116 are formed on the second insulating layer 110 in the pixel region 1 to complete the manufacture of the display panel according to the embodiment of the invention, and the upper electrode layer 116 is also formed on the second insulating layer 110 in the peripheral region 2.
As described above, by designing the opening 119 in the first insulating layer 108, the surface configuration of the bottom electrode layer 114 in the peripheral region 2 can be changed. That is, the specific concave portions 121 and the protruding structures 123 on the upper surface of the lower electrode layer 114 in the peripheral region 2 help to retain a sufficient amount of the organic insulating material during the spin coating process, so that the second insulating layer 110 in the peripheral region 2 has a sufficient thickness, and thus, a short circuit between the lower electrode layer 114 and the upper electrode layer 116 in the peripheral region 2 can be avoided.
Furthermore, the first trench 113 and the second trench 115 are respectively disposed in the conductive layer 112 and the lower electrode layer 114 in the peripheral region 2, so that an excessive stress can be released, and the reliability of the display panel can be improved.
In the peripheral area, the openings 119 formed in the first insulating layer 108 are not limited to the pattern or layout shown in fig. 3, for example, in an embodiment, the openings 119 formed in the first insulating layer 108 in the peripheral area 2 may be arranged in an array, as shown in fig. 2A. In another embodiment, the opening 119 may be rectangular or elongated, as shown in fig. 2D, or may be circular, polygonal, or other irregular shapes, which are not shown. In another embodiment, the openings 119 formed in the first insulating layer 108 in the peripheral region 2 may also make the first insulating layers 108 in island shapes separated from each other, and may also be arranged in an array, as shown in fig. 2B. Further, the first insulating layer 108 is not limited to the square shape shown in fig. 2B, and specifically, the first insulating layer 108 may have a circular shape and a square shape, and may be irregularly arranged, as shown in fig. 2C.
In addition, the embodiment of the invention is not limited to be applied to the active array type organic light emitting diode panel, and can also be applied to other display panels.
FIG. 4 is a block diagram of an image display system according to an embodiment of the present invention, which can be implemented in a display device 600 or an electronic device 800, such as a mobile phone, a digital camera, a Personal Digital Assistant (PDA), a notebook computer, a desktop computer, a television, a car monitor, or a portable DVD player. In this embodiment, the display device 600 includes the display panel 400, i.e., the display panel of the above-described embodiment, such as the display panel shown in fig. 3. In addition, in other embodiments, the display device 600 may be a part of the electronic device 800, as shown in fig. 4, the electronic device 800 includes the display device 600 and the input unit 700. The input unit 700 is coupled to the display device 600 for providing an input signal (e.g., an image signal) to the display device 600 to generate an image.
Furthermore, the display panel provided by the embodiment of the invention can be applied to various electronic devices, such as a mobile phone, a digital camera, a personal digital assistant, a notebook computer, a desktop computer, a television, a car display or a portable DVD player, which are not shown in the figure.
Although the present invention has been described with reference to a few preferred embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (23)
1. An organic light emitting diode display panel includes:
a substrate including a pixel region and a peripheral region;
a conductive layer on the substrate in the peripheral region;
a first insulating layer on the conductive layer in the peripheral region and having a plurality of openings exposing the conductive layer;
a lower electrode layer located on the first insulating layer and having a plurality of recesses, the recesses corresponding to the openings respectively and being compliantly located on the upper surface of the lower electrode layer;
a second insulating layer on the lower electrode layer; and
an upper electrode layer on the second insulating layer of the peripheral region, the second insulating layer separating the upper electrode layer from the lower electrode layer at a location of at least one of the recesses.
2. The OLED display panel of claim 1, wherein a width of one of the recesses is between 2.5 μm and 300 μm.
3. The OLED display panel of claim 1, wherein the depth of one of the recesses is between 0.08 μm and 0.30 μm.
4. The OLED display panel of claim 1, wherein the distance between two adjacent recesses is between 20 μm and 80 μm.
5. The OLED display panel of claim 1, wherein the second insulating layer has a thickness of 1.5 μm to 3.0 μm and is a coated organic insulating layer.
6. The OLED display panel of claim 1, wherein the surface roughness of the top surface of the bottom electrode layer is between 5% and 40%, the surface roughness of the top surface of the bottom electrode layer is a value obtained by dividing the total area of the top surface and the side surface of the protruding structure of the bottom electrode layer by the projected area of the whole bottom electrode layer.
7. A display panel, comprising:
a substrate including a pixel region and a peripheral region;
a control element located on the pixel region;
a first metal layer located on the peripheral region and the pixel region;
a first insulating layer on the peripheral region and on the first metal layer, wherein the first insulating layer on the peripheral region includes a plurality of openings on the first metal layer;
a second metal layer located on the first insulating layer of the peripheral region and electrically connected to the first metal layer, wherein a portion of the second metal layer is located in the openings;
a second insulating layer on the second metal layer in the peripheral region; and
an electrode layer on the second insulating layer,
wherein the upper surface of the second insulating layer in the peripheral area is flat, and the lower surface of the second insulating layer in the peripheral area is rough.
8. The display panel of claim 7, wherein the openings are arranged in a line.
9. The display panel according to claim 7, wherein the second insulating layer is further disposed on the pixel region, and a thickness of the second insulating layer in the pixel region is equal to a thickness of the second insulating layer in the peripheral region.
10. The display panel of claim 7, further comprising a light emitting layer over the pixel region, wherein the second metal layer is further over the pixel region and the light emitting layer is between the second metal layer and the electrode layer.
11. The display panel of claim 7, wherein the upper surface of the second metal layer in the peripheral region includes a plurality of recesses corresponding to the openings, respectively.
12. The display panel of claim 11, wherein a width of one of the recesses is between 2.5 μm and 300 μm.
13. The display panel of claim 11, wherein a depth of one of the recesses is between 0.08 μm and 0.30 μm.
14. The display panel of claim 11, wherein a pitch between two adjacent recesses is between 20 μm and 80 μm.
15. The display panel of claim 11, wherein a portion of the second insulating layer is located in one of the recesses.
16. The display panel of claim 11, wherein one of the openings is wider than one of the recesses.
17. The display panel of claim 7, wherein the first metal layer in the pixel region is electrically connected to the control element as a data line.
18. The display panel of claim 17, wherein the first insulating layer is further disposed on the pixel region, the first insulating layer disposed on the pixel region has a contact opening to expose the data line, and the second metal layer is filled in the contact opening and electrically connected to the data line.
19. An electronic device, comprising:
a display device comprising a display panel, wherein the display panel comprises:
a substrate including a pixel region and a peripheral region;
a control element located on the pixel region;
a first metal layer located on the peripheral region and the pixel region;
a first insulating layer on the peripheral region and on the first metal layer, wherein the first insulating layer on the peripheral region includes a plurality of openings on the first metal layer;
a second metal layer located on the first insulating layer of the peripheral region and electrically connected to the first metal layer, wherein a portion of the second metal layer is located in the openings;
a second insulating layer on the second metal layer in the peripheral region; and
an electrode layer on the second insulating layer, the second insulating layer separating the electrode layer from the second metal layer at a location of at least one of the openings.
20. The electronic device of claim 19, wherein an upper surface of the second metal layer in the peripheral region includes a plurality of recesses corresponding to the portions of the second metal layer in the openings, respectively, and wherein a portion of the second insulating layer is in the recesses.
21. The electronic device of claim 20, wherein a width of each of the recesses is between 2.5 μm and 300 μm.
22. The electronic device according to claim 20, wherein a depth of one of the recesses is between 0.08 μm and 0.30 μm.
23. The electronic device of claim 20, wherein a pitch between two adjacent recesses is between 20 μm and 80 μm.
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| CN2009101356421A CN101872780B (en) | 2009-04-23 | 2009-04-23 | Display panel and image display system using same |
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| KR102381285B1 (en) * | 2015-08-06 | 2022-03-31 | 삼성디스플레이 주식회사 | Flexible display device and manufacturing method thereof |
| CN108878454B (en) * | 2018-07-03 | 2022-04-01 | 京东方科技集团股份有限公司 | Display panel, manufacturing method thereof and display device |
| CN110416270B (en) | 2019-07-30 | 2022-01-07 | 京东方科技集团股份有限公司 | OLED display panel, detection method thereof and display device |
| CN111009568B (en) * | 2019-12-27 | 2022-10-11 | 武汉天马微电子有限公司 | Display panel and display device |
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| CN101071214A (en) * | 2007-07-05 | 2007-11-14 | 友达光电股份有限公司 | Liquid crystal display device and its manufacturing method |
| CN101359139A (en) * | 2007-08-01 | 2009-02-04 | 爱普生映像元器件有限公司 | Liquid crystal display panel and manufacturing method thereof |
| CN101393925A (en) * | 2007-01-08 | 2009-03-25 | 统宝光电股份有限公司 | Image displaying system |
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| JP2002196699A (en) * | 2000-12-25 | 2002-07-12 | Toshiba Corp | Active matrix substrate and liquid crystal display device |
| CN100378551C (en) * | 2001-10-22 | 2008-04-02 | 三星电子株式会社 | Liquid crystal display and its manufacture method |
| KR100741962B1 (en) * | 2003-11-26 | 2007-07-23 | 삼성에스디아이 주식회사 | Flat Panel Display |
| TWI300240B (en) * | 2006-03-29 | 2008-08-21 | Toppoly Optoelectronics Corp | Systems for providing conducting pad and fabrication method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101393925A (en) * | 2007-01-08 | 2009-03-25 | 统宝光电股份有限公司 | Image displaying system |
| CN101071214A (en) * | 2007-07-05 | 2007-11-14 | 友达光电股份有限公司 | Liquid crystal display device and its manufacturing method |
| CN101359139A (en) * | 2007-08-01 | 2009-02-04 | 爱普生映像元器件有限公司 | Liquid crystal display panel and manufacturing method thereof |
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