CN110416316A - Thin film transistor and its manufacturing method, display base plate and display device - Google Patents
Thin film transistor and its manufacturing method, display base plate and display device Download PDFInfo
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- CN110416316A CN110416316A CN201910711793.0A CN201910711793A CN110416316A CN 110416316 A CN110416316 A CN 110416316A CN 201910711793 A CN201910711793 A CN 201910711793A CN 110416316 A CN110416316 A CN 110416316A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78642—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- Thin Film Transistor (AREA)
Abstract
The present invention provides a kind of thin film transistor and its manufacturing method, display base plate and display devices, belong to field of display technology.Wherein, thin film transistor (TFT), comprising: the first pole on underlay substrate；Positioned at described first extremely on wall, first pole is not completely covered the wall；The second pole on the wall, second pole cover at least partly region in at least partly region of the first surface of the wall and the first side surface of the covering wall；The active layer being connect with first pole and second pole；Cover the gate insulation layer of the active layer；The grid being oppositely arranged across the gate insulation layer and the active layer.Technical solution of the present invention is able to solve the short-channel effect of the thin film transistor (TFT) of vertical structure, improves the stability of the thin film transistor (TFT) of vertical structure.
Description
Technical field
The present invention relates to field of display technology, particularly relate to a kind of thin film transistor and its manufacturing method, display base plate and
Display device.
Background technique
In recent years, as (Virtual Reality virtually shows AR (Augmented Reality, augmented reality)/VR
Real technology) display explosion type development, the exploitation of superelevation PPI (pixel density) (>=1000PPI) display base plate technology is just gradually
One of main flow direction as display technology.But existing bottom gate thin film transistor and back channel-etch type thin film transistor
Size it is all bigger, be not suitable for the display base plate of superelevation PPI.The size of the thin film transistor (TFT) (TFT) of vertical structure is compared
It is greatly reduced in bottom gate thin film transistor and back channel-etch type thin film transistor, presents the thin film transistor (TFT) of vertical structure
Application prospect in superelevation PPI display base plate.
The thin film transistor (TFT) of vertical structure can break through the limitation of the techniques such as exposure, realize ultrashort channel, and it is brilliant to reduce film
The size of body pipe, but simultaneously, it with the diminution of thin film transistor channel, also will appear short-channel effect, influence thin film transistor (TFT)
Stability.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of thin film transistor and its manufacturing method, display base plate and displays
Device is able to solve the short-channel effect of the thin film transistor (TFT) of vertical structure, improves the stabilization of the thin film transistor (TFT) of vertical structure
Property.
In order to solve the above technical problems, the embodiment of the present invention offer technical solution is as follows:
On the one hand, a kind of thin film transistor (TFT) is provided, comprising:
The first pole on underlay substrate；
Positioned at described first extremely on wall, first pole is not completely covered the wall；
The second pole on the wall, second pole cover the first surface of the wall at least partly
At least partly region of region and the first side surface of the covering wall；
The active layer being connect with first pole and second pole；
Cover the gate insulation layer of the active layer；
The grid being oppositely arranged across the gate insulation layer and the active layer；
Wherein, the first surface is a side surface of the wall far from the underlay substrate, and described first extremely
One of them in source electrode and drain electrode, the described second another extremely in source electrode and drain electrode.
Optionally, second pole covers the whole region of the first side surface of the wall.
Optionally, the wall on the underlay substrate orthographic projection and first pole on the underlay substrate
Orthographic projection partly overlap, first side surface be side surface of the wall far from first pole.
Optionally, the active layer include first part on the wall, positioned at described first extremely on the
Two parts and the Part III connecting with second pole, the second part cover first pole and are not covered by the wall
The region of lid, the Part III is between second pole and the wall or is located at described second extremely far from the lining
On one side surface of substrate.
Optionally, the gate insulation layer is located at side of the active layer far from first side surface.
Optionally, the angle between first side surface and the underlay substrate is less than 60 °.
The embodiment of the invention also provides a kind of display base plates, including thin film transistor (TFT) as described above.
The embodiment of the invention also provides a kind of display devices, including display base plate as described above.
The embodiment of the invention also provides a kind of production methods of thin film transistor (TFT), comprising:
The first pole of thin film transistor (TFT) is formed on underlay substrate；
Described first extremely on form wall, first pole is not completely covered for the wall；
The second pole of the thin film transistor (TFT) is formed, second pole covers at least portion of the first surface of the wall
At least partly region of subregion and the first side surface of the covering wall；
Form the active layer connecting with first pole and second pole；
Form the gate insulation layer for covering the active layer；
Form the grid being oppositely arranged across the gate insulation layer and the active layer；
Wherein, the first surface is a side surface of the wall far from the underlay substrate, and described first extremely
One of them in source electrode and drain electrode, the described second another extremely in source electrode and drain electrode.
Optionally, forming second pole includes:
Form second pole for covering the whole region of the first side surface of the wall.
The embodiment of the present invention has the advantages that
In above scheme, at least partly region of the first side surface of the second pole covering wall of thin film transistor (TFT), In
When thin film transistor (TFT) works, the second pole for covering the first side surface of wall is capable of providing back channel electric field, effectively shielding leakage
Influence of the electric field to channel and source is held, weakens groove potential field intensity, and then reduce short-channel effect, is effectively relieved due to hanging down
Straight TFT channel is short and bring short-channel effect, improves the stability of vertical TFT, is more advantageous to vertical TFT in actual products
Application.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of the thin film transistor (TFT) of existing vertical structure；
Fig. 2 is the structural schematic diagram of existing back channel-etch type thin film transistor；
Fig. 3 is the structural schematic diagram of existing top gate type thin film transistor；
Fig. 4-Fig. 8 is the production process schematic diagram of thin film transistor (TFT) of the embodiment of the present invention.
Appended drawing reference
1 underlay substrate, 2 buffer layer, 3 source electrode, 4 wall
5 drain electrode 6 active layer, 7 gate insulation layer, 8 grids
9 interlayer insulating films
Specific embodiment
To keep the embodiment of the present invention technical problems to be solved, technical solution and advantage clearer, below in conjunction with
Drawings and the specific embodiments are described in detail.
Fig. 1 is the structural schematic diagram of the thin film transistor (TFT) of existing vertical structure, and Fig. 2 is that existing back channel-etch type film is brilliant
The structural schematic diagram of body pipe, Fig. 3 are the structural schematic diagram of existing top gate type thin film transistor, wherein 1 is underlay substrate, and 2 be slow
Layer is rushed, 3 be source electrode, and 4 be wall, and 5 be drain electrode, and 6 be active layer, and 7 be gate insulation layer, and 8 be grid, and 9 be interlayer insulating film.It can
To find out, the width D 1 of the thin film transistor (TFT) of vertical structure is less than the width D 2 of back channel-etch type thin film transistor, hangs down simultaneously
The width D 1 of the thin film transistor (TFT) of straight structure is less than the width D 3 of top gate type thin film transistor.The thin film transistor (TFT) of vertical structure
Size is greatly reduced compared to bottom gate thin film transistor and back channel-etch type thin film transistor, presents the thin of vertical structure
Application prospect of the film transistor in superelevation PPI display base plate.
The thin film transistor (TFT) of vertical structure can break through the limitation of the techniques such as exposure, realize ultrashort channel, and it is brilliant to reduce film
The size of body pipe, but simultaneously, it with the diminution of thin film transistor channel, also will appear short-channel effect, influence thin film transistor (TFT)
Stability.
Short-channel effect will lead to the threshold voltage vt h of thin film transistor (TFT) and institute's making alive is related to journey very serious
Degree, the reason is that when channel reduces to a certain extent, it may occur that leakage to potential barrier reduces phenomena such as (DIBL), serious to will lead to source
Leak break-through, film crystal tube failure.The reason of generating short-channel effect is the length reduction when thin film transistor (TFT), drain terminal forceful electric power
Field, which acts on source, to enhance, and source potential barrier reduces, and causes the electronics of source to be easier to enter in channel, influences thin film transistor (TFT)
Vth, Ioff characteristic, source electric field is stronger, which is more obvious, be embodied in same thin film transistor (TFT) different Vds electricity
Pressure, Vth are different；Vds is bigger, and Ioff is bigger.
To solve the above-mentioned problems, the embodiment of the present invention provides a kind of thin film transistor and its manufacturing method, display base plate
And display device, it is able to solve the short-channel effect of the thin film transistor (TFT) of vertical structure, improves the thin film transistor (TFT) of vertical structure
Stability.
The embodiment of the present invention provides a kind of thin film transistor (TFT), comprising:
The first pole on underlay substrate；
Positioned at described first extremely on wall, first pole is not completely covered the wall；
The second pole on the wall, second pole cover the first surface of the wall at least partly
At least partly region of region and the first side surface of the covering wall；
The active layer being connect with first pole and second pole；
Cover the gate insulation layer of the active layer；
The grid being oppositely arranged across the gate insulation layer and the active layer；
Wherein, the first surface is a side surface of the wall far from the underlay substrate, and described first extremely
One of them in source electrode and drain electrode, the described second another extremely in source electrode and drain electrode.
In the present embodiment, at least partly region of the first side surface of the second pole covering wall of thin film transistor (TFT), In
When thin film transistor (TFT) works, the second pole for covering the first side surface of wall is capable of providing back channel electric field, effectively shielding leakage
Influence of the electric field to channel and source is held, weakens groove potential field intensity, and then reduce short-channel effect, is effectively relieved due to hanging down
Straight TFT channel is short and bring short-channel effect, improves the stability of vertical TFT, is more advantageous to vertical TFT in actual products
Application.
Preferably, second pole covers the whole region of the first side surface of the wall, is capable of increasing in this way
The back channel electric field that two poles provide farthest shields influence of the drain terminal electric field to channel and source, weakens groove potential field
Intensity, and then reduce short-channel effect.
In one specific embodiment, orthographic projection of the wall on the underlay substrate and first pole are in the lining
Orthographic projection on substrate partly overlaps, and first side surface is side surface of the wall far from first pole.
Specifically, the active layer may include first part on the wall, be located at described first extremely on
Second part and the Part III that is connect with second pole, the second part cover first pole not by the interval
The region of layer covering, the Part III is between second pole and the wall or is located at described second extremely far from institute
It states on a side surface of underlay substrate.
Specifically, the gate insulation layer is located at side of the active layer far from first side surface.
Second pole is formed on the first side surface, if the angle between the first side surface and underlay substrate is excessive,
When depositing conductive material the second pole of formation on the first side surface, it will affect the continuity of the conductive material of deposition, be subsequently formed
Second is easy to the situation for open circuit occur, and therefore, the angle between first side surface and the underlay substrate is preferably smaller than
60 °, it can guarantee continuity of second pole on the first side surface, the folder between the first side surface and the underlay substrate in this way
Angle can be 45 °, 30 °, 20 ° etc..
In one specific embodiment, the drain electrode of the first extremely thin film transistor (TFT), the source electrode of the second extremely thin film transistor (TFT) is such as schemed
Shown in 8, thin film transistor (TFT) includes: the buffer layer 2 on underlay substrate 1；Drain electrode 5 on buffer layer 2；Positioned at drain electrode 5
On wall 4, wall 4 partly overlaps in the orthographic projection on underlay substrate 1 with 5 orthographic projection on underlay substrate 1 of drain electrode；
Source electrode 3 on wall 4, source electrode 3 cover the partial region of 4 upper surface of wall, cover the first side surface of wall 4
Whole region, and extend to and contacted with buffer layer 2, the first side surface is a side surface of the wall 4 far from drain electrode 5；It is located at
Active layer 6 on wall 4, a part of active layer 6 are located at the upper surface of source electrode 3, and a part is located at the upper table of wall 4
Face, a part are located at the upper surface of drain electrode 5；Cover the gate insulation layer 7 of active layer 6；Grid 8 on gate insulation layer 7, grid
8 are located at side of the gate insulation layer 7 far from the first side surface.
As shown in figure 8, the source electrode 3 positioned at the first side surface is capable of providing as shown by arrows in thin film transistor (TFT) work
Back channel electric field, effectively shield influence of the drain terminal electric field to channel and source, weaken groove potential field intensity, and then reduce short
Channelling effect is effectively relieved since vertical TFT channel is short and bring short-channel effect, improves the stability of vertical TFT, more have
Conducive to the application of vertical TFT in actual products.
The embodiment of the invention also provides a kind of display base plates, including thin film transistor (TFT) as described above.
The embodiment of the invention also provides a kind of display devices, including display base plate as described above.The display device packet
Include but be not limited to: radio frequency unit, network module, audio output unit, input unit, sensor, display unit, user input list
The components such as member, interface unit, memory, processor and power supply.It will be understood by those skilled in the art that above-mentioned display device
Structure do not constitute the restriction to display device, display device may include above-mentioned more or fewer components, or combination
Certain components or different component layouts.In embodiments of the present invention, display device include but is not limited to display, mobile phone,
Tablet computer, television set, wearable electronic, navigation display equipment etc..
The display device can be with are as follows: any tool such as LCD TV, liquid crystal display, Digital Frame, mobile phone, tablet computer
There are the products or components of display function, wherein the display device further includes flexible circuit board, printed circuit board and backboard.
The embodiment of the invention also provides a kind of production methods of thin film transistor (TFT), comprising:
The first pole of thin film transistor (TFT) is formed on underlay substrate；
Described first extremely on form wall, first pole is not completely covered for the wall；
The second pole of the thin film transistor (TFT) is formed, second pole covers at least portion of the first surface of the wall
At least partly region of subregion and the first side surface of the covering wall；
Form the active layer connecting with first pole and second pole；
Form the gate insulation layer for covering the active layer；
Form the grid being oppositely arranged across the gate insulation layer and the active layer；
Wherein, the first surface is a side surface of the wall far from the underlay substrate, and described first extremely
One of them in source electrode and drain electrode, the described second another extremely in source electrode and drain electrode.
In the present embodiment, at least partly region of the first side surface of the second pole covering wall of thin film transistor (TFT), In
When thin film transistor (TFT) works, the second pole for covering the first side surface of wall is capable of providing back channel electric field, effectively shielding leakage
Influence of the electric field to channel and source is held, weakens groove potential field intensity, and then reduce short-channel effect, is effectively relieved due to hanging down
Straight TFT channel is short and bring short-channel effect, improves the stability of vertical TFT, is more advantageous to vertical TFT in actual products
Application.
Optionally, forming second pole includes:
Second pole for covering the whole region of the first side surface of the wall is formed, is capable of increasing second in this way
The back channel electric field that pole provides farthest shields influence of the drain terminal electric field to channel and source, weakens groove potential field strength
Degree, and then reduce short-channel effect.
Below by taking the first extremely extremely source electrode of drain electrode, second as an example, in conjunction with attached drawing to the system of thin film transistor (TFT) of the invention
Describe in detail as method, the production method of the thin film transistor (TFT) of the present embodiment specifically includes the following steps:
Step 1, as shown in figure 4, provide a underlay substrate 1, on underlay substrate 1 formed drain electrode 5 figure；
Wherein, buffer layer 2 can also be formed on underlay substrate 1, is being buffered later before the figure for forming drain electrode 5
The figure of drain electrode 5 is formed on layer 2.
The method of sputtering or thermal evaporation can be used, and deposition thickness is about on the buffer layer 2Conduction
Layer, conductive layer can be Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, the alloy of the metals such as Ta, W and these metals, conductive layer
It can be single layer structure or multilayered structure, multilayered structure such as Cu Mo, Ti Cu Ti, Mo Al Mo etc..Certainly, conductive layer
It can also be the transparent conductive oxides such as ITO.Photoresist is coated on the electrically conductive, forms photoresist reservation after being exposed development
Region and photoresist do not retain region, and the figure of the corresponding drain electrode 5 of photoresist retention area performs etching conductive layer, such as Fig. 4 institute
Show, forms drain electrode 5.
Step 2, as shown in figure 5, formed wall 4 figure；
Specifically, an interlayer interlayer material is coated on the underlay substrate 1 Jing Guo step 1, material spacer layer can be
The thickness of SiOx or resinous material, material spacer layer is not less thanIf material spacer layer uses resinae material
Material, then after forming this layer of resinous material, it is also necessary to do Low Temperature Heat Treatment to it, such as 100~180 DEG C at a temperature of
Heating 30-60 minutes, gas, steam and the H inside resinous material is discharged；
Photoresist is coated on material spacer layer, forms photoresist retention area after being exposed development and photoresist is not protected
Region is stayed, photoresist retention area corresponds to the figure of wall 4, performs etching to material spacer layer, as shown in figure 5, between being formed
Interlayer 4, the angle α between the side surface and underlay substrate 1 of wall 4 are not more than 60 °.It can guarantee the of subsequent deposition in this way
Continuity of the diarcs at material on the first side surface, the angle between the first side surface and the underlay substrate can be
45 °, 30 °, 20 ° etc..
As shown in figure 5, drain electrode 5, orthographic projection of the wall 4 on underlay substrate 1 and drain electrode 5 are not completely covered for wall 4
Orthographic projection on underlay substrate 1 partly overlaps.
Step 3, as shown in fig. 6, on the underlay substrate 1 Jing Guo step 2 formed source electrode 3；
Can be about using the method deposition thickness of sputtering or thermal evaporationConductive layer, conductive layer can
To be Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, the alloy of the metals such as Ta, W and these metals, conductive layer can be single layer
Structure or multilayered structure, multilayered structure such as Cu Mo, Ti Cu Ti, Mo Al Mo etc..Certainly, conductive layer can also be ITO
Equal transparent conductive oxides.Photoresist is coated on the electrically conductive, forms photoresist retention area and photoetching after being exposed development
Glue does not retain region, and photoresist retention area corresponds to the figure of source electrode 3, performs etching to conductive layer, as shown in fig. 6, the source that formed
Pole 3.
As shown in fig. 6, source electrode 3 covers a part of 4 upper surface of wall, the complete of the first side surface of wall 4 is covered
Portion region, the first side surface are a side surface of the wall 4 far from drain electrode 5.Source electrode 3 is also extend on buffer layer 2.
Step 4, as shown in fig. 7, forming active layer 6 and gate insulation layer 7；
As shown in fig. 7, form active layer 6 and gate insulation layer 7 on the underlay substrate 1 Jing Guo step 3, active layer 6 can be with
Using materials such as IGZO, IZO, IGZTO, ITZO and ITGO, gate insulation layer 7 can select oxide, nitride or oxynitriding
Object is closed, corresponding reaction gas is SiH4、NH3、N2Or SiH2Cl2、NH3、N2.Gate insulation layer 7 can also be Al2O3Equal high-k
Metal oxide dielectric material.Usual Al2O3Equal high-k metal oxide dielectric material can be carved with Al etching liquid
Erosion, principle active component H3PO4, reaction equation Al2O3+H3PO4→Al3++PO4 3-+H2Al(PO4)+H2O, in order to anti-
Only active layer 6 is caused to damage when gate insulator layer 7, uses Al in gate insulation layer 72O3Equal high-k metal oxide dielectric
When material, 6 material of active layer need to be the oxide material of the anti-Al etching liquid such as (but being not limited to) IGZTO, ITZO and ITGO, be total to
Logical speciality is preferably to keep out the damage of Al etching liquid containing ingredient Sn.
It is of course also possible to not be patterned to gate insulation layer 7, the gate insulation layer 7 of a flood is formed.
Step 5, as shown in figure 8, formed grid 8 figure.
Specifically, can be about using the method deposition thickness of sputtering or thermal evaporation on the underlay substrate Jing Guo step 4Conductive layer, conductive layer can be Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, the metals such as Ta, W and
The alloy of these metals, conductive layer can be single layer structure or multilayered structure, multilayered structure such as Cu Mo, Ti Cu Ti,
Mo Al Mo etc..Certainly, conductive layer can also be the transparent conductive oxides such as ITO.Photoresist is coated on the electrically conductive, is exposed
Photoresist retention area is formed after photodevelopment and photoresist does not retain region, and photoresist retention area corresponds to the figure of grid 8, right
Conductive layer performs etching, as shown in figure 8, forming grid 8.
In the present embodiment, when thin film transistor (TFT) works, the source electrode 3 positioned at the first side surface is capable of providing as shown by arrows
Channel electric field is carried on the back, influence of the drain terminal electric field to channel and source is effectively shielded, weakens groove potential field intensity, and then reduce short ditch
Channel effect is effectively relieved since vertical TFT channel is short and bring short-channel effect, improves the stability of vertical TFT, more favorably
In the application of vertical TFT in actual products.
In each method embodiment of the present invention, the serial number of each step can not be used to limit the successive suitable of each step
Sequence, for those of ordinary skill in the art, without creative efforts, the successive variation to each step
Within protection scope of the present invention.
It is to be appreciated that all the embodiments in this specification are described in a progressive manner, phase between each embodiment
It may refer to each other with similar part, each embodiment focuses on the differences from other embodiments.In particular,
For embodiment, since it is substantially similar to product embodiments, so describing fairly simple, related place is referring to product
The part of embodiment illustrates.
Unless otherwise defined, the technical term or scientific term that the disclosure uses should be tool in disclosure fields
The ordinary meaning for thering is the personage of general technical ability to be understood." first ", " second " used in the disclosure and similar word are simultaneously
Any sequence, quantity or importance are not indicated, and are used only to distinguish different component parts." comprising " or "comprising" etc.
Similar word means that the element or object before the word occur covers the element or object for appearing in the word presented hereinafter
And its it is equivalent, and it is not excluded for other elements or object.The similar word such as " connection " or " connected " is not limited to physics
Or mechanical connection, but may include electrical connection, it is either direct or indirectly."upper", "lower",
"left", "right" etc. is only used for indicating relative positional relationship, and after the absolute position for being described object changes, then the relative position is closed
System may also correspondingly change.
It is appreciated that ought such as layer, film, region or substrate etc element be referred to as be located at another element "above" or "below"
When, which " direct " can be located at "above" or "below" another element, or may exist intermediary element.
In the description of above embodiment, particular features, structures, materials, or characteristics can be at any one or more
It can be combined in any suitable manner in a embodiment or example.
The above, the only specific embodiment of the disclosure, but the protection scope of the disclosure is not limited thereto, it is any
Those familiar with the art can easily think of the change or the replacement in the technical scope that the disclosure discloses, and should all contain
It covers within the protection scope of the disclosure.Therefore, the protection scope of the disclosure should be based on the protection scope of the described claims.
Claims (10)
1. a kind of thin film transistor (TFT) characterized by comprising
The first pole on underlay substrate；
Positioned at described first extremely on wall, first pole is not completely covered the wall；
The second pole on the wall, second pole cover at least partly region of the first surface of the wall
And at least partly region of the first side surface of the covering wall；
The active layer being connect with first pole and second pole；
Cover the gate insulation layer of the active layer；
The grid being oppositely arranged across the gate insulation layer and the active layer；
Wherein, the first surface is a side surface of the wall far from the underlay substrate, the described first extremely source electrode
With one of them in drain electrode, the described second another extremely in source electrode and drain electrode.
2. thin film transistor (TFT) according to claim 1, which is characterized in that second pole covers the first of the wall
The whole region of side surface.
3. thin film transistor (TFT) according to claim 1, which is characterized in that the wall on the underlay substrate just
Projection partly overlaps with orthographic projection of first pole on the underlay substrate, and first side surface is that the wall is remote
Side surface from first pole.
4. thin film transistor (TFT) according to claim 3, which is characterized in that the active layer includes being located on the wall
First part, positioned at described first extremely on second part and the Part III that is connect with second pole, described second
Divide the covering region that first pole is not covered by the wall, the Part III is located at second pole and the interval
Between layer or on the described second extremely side surface far from the underlay substrate.
5. thin film transistor (TFT) according to claim 4, which is characterized in that it is separate that the gate insulation layer is located at the active layer
The side of first side surface.
6. thin film transistor (TFT) according to claim 1, which is characterized in that first side surface and the underlay substrate it
Between angle less than 60 °.
7. a kind of display base plate, which is characterized in that including thin film transistor (TFT) such as of any of claims 1-6.
8. a kind of display device, which is characterized in that including display base plate as claimed in claim 7.
9. a kind of production method of thin film transistor (TFT) characterized by comprising
The first pole of thin film transistor (TFT) is formed on underlay substrate；
Described first extremely on form wall, first pole is not completely covered for the wall；
The second pole of the thin film transistor (TFT) is formed, second pole covers at least partly area of the first surface of the wall
At least partly region of domain and the first side surface of the covering wall；
Form the active layer connecting with first pole and second pole；
Form the gate insulation layer for covering the active layer；
Form the grid being oppositely arranged across the gate insulation layer and the active layer；
Wherein, the first surface is a side surface of the wall far from the underlay substrate, the described first extremely source electrode
With one of them in drain electrode, the described second another extremely in source electrode and drain electrode.
10. the production method of thin film transistor (TFT) according to claim 9, which is characterized in that forming second pole includes:
Form second pole for covering the whole region of the first side surface of the wall.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111370496A (en) * | 2020-03-18 | 2020-07-03 | 京东方科技集团股份有限公司 | Thin film transistor, manufacturing method thereof and display device |
| CN113299741A (en) * | 2021-05-07 | 2021-08-24 | 惠州市华星光电技术有限公司 | Thin film transistor device, backlight module and display panel |
| CN113745345A (en) * | 2021-08-26 | 2021-12-03 | 深圳市华星光电半导体显示技术有限公司 | Thin film transistor substrate, manufacturing method thereof and display device |
| CN113972221A (en) * | 2021-10-09 | 2022-01-25 | Tcl华星光电技术有限公司 | Display panel, preparation method of display panel and display terminal |
| WO2023082330A1 (en) * | 2021-11-15 | 2023-05-19 | 武汉华星光电半导体显示技术有限公司 | Thin film transistor, electronic apparatus, preparation method therefor, and display apparatus |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111370496A (en) * | 2020-03-18 | 2020-07-03 | 京东方科技集团股份有限公司 | Thin film transistor, manufacturing method thereof and display device |
| WO2021184910A1 (en) * | 2020-03-18 | 2021-09-23 | 京东方科技集团股份有限公司 | Thin film transistor and method for manufacturing same, and display device |
| CN111370496B (en) * | 2020-03-18 | 2021-10-26 | 京东方科技集团股份有限公司 | Thin film transistor, manufacturing method thereof and display device |
| CN113299741A (en) * | 2021-05-07 | 2021-08-24 | 惠州市华星光电技术有限公司 | Thin film transistor device, backlight module and display panel |
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| WO2023082330A1 (en) * | 2021-11-15 | 2023-05-19 | 武汉华星光电半导体显示技术有限公司 | Thin film transistor, electronic apparatus, preparation method therefor, and display apparatus |
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Application publication date: 20191105 |