CN108873526B - Array substrate, manufacturing method thereof and display device - Google Patents
Array substrate, manufacturing method thereof and display device Download PDFInfo
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- CN108873526B CN108873526B CN201810795868.3A CN201810795868A CN108873526B CN 108873526 B CN108873526 B CN 108873526B CN 201810795868 A CN201810795868 A CN 201810795868A CN 108873526 B CN108873526 B CN 108873526B
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/136295—Materials; Compositions; Manufacture processes
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- Engineering & Computer Science (AREA)
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- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Nonlinear Science (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention provides an array substrate, a manufacturing method thereof and a display device. The array substrate comprises a data line, wherein the data line is of a composite structure consisting of a conductive area and an insulating area, and the conductive area and the insulating area are distributed along the width direction of the data line. The material of the conductive region includes a metal, and the material of the insulating region includes a metal compound obtained by subjecting the metal to plasma treatment. According to the invention, the data line is designed into a composite structure consisting of the insulating area and the conductive area in the width direction of the data line, so that the coupling capacitance between the data line and the common electrode and between the data line and the pixel electrode can be reduced, and the product quality and performance are greatly improved on the premise of ensuring the key size and yield of the data line.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a manufacturing method of the array substrate and a display device.
Background
Liquid Crystal Display (LCD) panels, as a flat panel Display device, are increasingly used in the high performance Display field due to their features of light weight, small size, low power consumption, high Display resolution, no radiation, and relatively low manufacturing cost. The LCD main body structure comprises an array substrate and a color Film substrate which are oppositely arranged, and liquid crystal filled between the two substrates, wherein the array substrate comprises a plurality of pixel units which are vertically crossed and limited by a plurality of grid lines and a plurality of data lines, and each pixel unit is provided with a Thin Film Transistor (TFT) and a pixel electrode. When the liquid crystal display panel works, the control signal applied on the grid line enables the data signal on the data line to be transmitted to the pixel electrode, meanwhile, voltage is provided for the common electrode, the common electrode and the pixel electrode form an electric field, and the arrangement direction of liquid crystal molecules is changed under the action of an external electric field, so that the light transmittance is controlled, and the display of different gray levels is realized.
Disclosure of Invention
The technical problem to be solved by the embodiments of the present invention is to provide an array substrate, a manufacturing method thereof, and a display device, so as to effectively reduce coupling capacitance.
In order to solve the above technical problem, an embodiment of the present invention provides an array substrate, including a data line, where the data line is a composite structure composed of a conductive region and an insulating region, and the conductive region and the insulating region are distributed along a width direction of the data line.
Optionally, the insulating region is located on both sides of the conductive region.
Optionally, the material of the conductive region comprises a metal, and the material of the insulating region comprises a metal compound.
Optionally, the metal compound is obtained by plasma treatment of the metal.
Optionally, the metal compound comprises a metal oxide or a metal nitride.
Optionally, the thin film transistor further comprises a source electrode and a drain electrode of the thin film transistor, wherein the source electrode and the drain electrode of the thin film transistor comprise a conductive region and an insulating region.
Optionally, the width of the insulating region is 5% to 30% of the width of the conductive region.
The embodiment of the invention also provides a display device which comprises a first substrate and a second substrate which are oppositely arranged, wherein the first substrate adopts the array substrate.
In order to solve the above technical problem, an embodiment of the present invention further provides a method for manufacturing an array substrate, including:
and forming a data line, wherein the data line is a composite structure consisting of a conductive region and an insulating region, and the conductive region and the insulating region are distributed along the width direction of the data line.
Optionally, the insulating region is located on both sides of the conductive region.
Optionally, forming the data line comprises:
depositing a metal film, coating photoresist on the metal film, and forming a data line pattern through mask, exposure, development and etching processes;
forming the data lines into a conductive area and insulating areas positioned on two sides of the conductive area by plasma processing;
and stripping the residual photoresist.
Optionally, the plasma treatment comprises one of: oxygen plasma treatment, nitrogen plasma treatment, sulfur hexafluoride and oxygen plasma treatment.
Optionally, when the data line is formed, a source electrode and a drain electrode of the thin film transistor are also formed at the same time, and the source electrode and the drain electrode include a conductive region and an insulating region.
Optionally, the width of the insulating region is 5% to 30% of the width of the conductive region.
According to the array substrate, the preparation method thereof and the display device provided by the embodiment of the invention, the data line is designed into the composite structure consisting of the insulating area and the conductive area in the width direction of the data line, so that the coupling capacitance between the data line and the common electrode and between the data line and the pixel electrode can be reduced, and the product quality and performance are greatly improved on the premise of ensuring the key size and yield of the data line.
Of course, not all of the advantages described above need to be achieved at the same time in the practice of any one product or method of the invention. Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the embodiments of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the example serve to explain the principles of the invention and not to limit the invention. The shapes and sizes of the various elements in the drawings are not to scale and are merely intended to illustrate the invention.
Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the invention;
FIG. 2 is a schematic diagram of a gate electrode pattern formed according to the first embodiment of the present invention;
FIG. 3 is a schematic view illustrating an active layer pattern according to a first embodiment of the present invention;
FIG. 4 is a schematic diagram illustrating a first transparent electrode pattern according to a first embodiment of the present invention;
FIG. 5 is a schematic diagram illustrating a first embodiment of the present invention after forming patterns such as data lines;
FIG. 6 is a schematic view of the first embodiment of the present invention after plasma treatment;
FIG. 7 is a diagram illustrating a passivation layer and a second transparent electrode pattern according to the first embodiment of the present invention;
FIG. 8 is a schematic view illustrating an active layer and an ohmic contact layer patterned according to a second embodiment of the present invention;
FIG. 9 is a schematic diagram illustrating a second embodiment of the present invention after forming a first transparent electrode pattern;
FIG. 10 is a schematic diagram illustrating a second embodiment of the present invention after forming patterns such as data lines;
FIG. 11 is a schematic view of a second embodiment of the present invention after plasma treatment;
FIG. 12 is a schematic diagram illustrating an ohmic contact layer etched according to a second embodiment of the invention;
fig. 13 is a diagram illustrating a passivation layer and a second transparent electrode pattern according to a second embodiment of the present invention.
Description of reference numerals:
10-a substrate; 11-a gate electrode; 12-a gate insulating layer;
13-an active layer; 14 — a first transparent electrode; 15-data line;
16-a source electrode; 17-a drain electrode; 18-a passivation layer;
19-a second transparent electrode; 20-ohmic contact layer; 15a — a conductive region;
15 b-insulating region.
Detailed Description
The following detailed description of embodiments of the invention is provided in connection with the accompanying drawings and examples. The following examples are intended to illustrate the invention but are not intended to limit the scope of the invention. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.
In the related art, in the TFT-LCD array substrate, since there are many electrodes and charges are easily accumulated on the electrodes, a coupling capacitance is generated between the electrodes. For example, a coupling capacitance Cdc may be formed between the data line and the common electrode, a coupling capacitance Cpd may be formed between the data line and the pixel electrode, and coupling capacitances Cgs and Cgd may be formed between the gate electrode of the thin film transistor and the source and drain electrodes. Research shows that these coupling capacitors not only increase the load of the data lines and the gate lines, which results in an increase in power consumption of the display panel, but also adversely affect the display, resulting in poor display characteristics such as greenness and crosstalk.
In order to reduce the coupling capacitance, various solutions have been proposed in the related art, such as adding a shielding structure on the data line, adding an insulating layer above the data line, and reducing the width of the data line. However, through research by the inventors of the present application, it is found that the solution of adding the shielding structure to the data line can only reduce the coupling capacitance Cpd between the data line and the pixel electrode, and the solution of adding the insulating layer to the data line can only reduce the coupling capacitance Cdc between the data line and the common electrode, and both of them increase the number of patterning processes. However, the margin (margin) in the design and preparation process of the conventional array substrate is very small, the minimum critical dimension CD of the data line can only be 3 μm, and under the condition of the process limit, the solution for reducing the width of the data line cannot ensure the yield.
Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the invention. As shown in fig. 1, the array substrate according to the embodiment of the invention includes a data line 15, and the data line 15 includes an insulating region 15a and a conductive region 15b, that is, the data line 15 is a composite structure composed of the insulating region 15a and the conductive region 15b, and the insulating region 15a and the conductive region 15b are distributed along the width direction of the data line 15.
Wherein the material of the conductive region 15b includes a metal, such as aluminum Al, molybdenum Mo, copper Cu, silver Ag, etc., and the material of the insulating region 15a includes a metal compound, which is an oxide (metal oxide) or a nitride (metal nitride) of the corresponding metal, such as aluminum oxide Al2O3Copper oxide CuO, molybdenum oxide MoOx, copper nitride Cu3N, molybdenum nitride MoN, and the like. The metal compound is obtained by subjecting the corresponding metal to plasma treatment.
Wherein the insulating regions 15a are located on both sides of the conductive region 15 b.
Further, the width of the insulating region 15a is 5% to 30% of the width of the conductive region 15b in a direction perpendicular to the data line (width direction of the data line).
Specifically, the array substrate of the embodiment of the invention comprises:
a substrate 10;
a gate insulating layer 12 disposed on the substrate 10;
a data line 15 and a first transparent electrode 14 disposed on the gate insulating layer 12, wherein the data line 15 includes a conductive region 15b and insulating regions 15a at both sides of the conductive region 15 b;
a passivation layer 18 covering the data line 15 and the first transparent electrode 14;
and a second transparent electrode 19 disposed on the passivation layer 18.
Furthermore, the array substrate in the embodiment of the present invention further includes a thin film transistor, a source electrode and a drain electrode of the thin film transistor include a conductive region and an insulating region, that is, the source electrode is a composite structure composed of the insulating region and the conductive region, the drain electrode is also a composite structure composed of the insulating region and the conductive region, and the insulating region is located outside the conductive region.
According to the array substrate provided by the embodiment of the invention, in the width direction of the data line, the data line is composed of the conductive area and the insulating areas positioned on the two sides of the conductive area, so that the coupling capacitance is effectively reduced. On one hand, since only the conductive region in the data line forms a coupling capacitance with the second transparent electrode, which is equivalent to reducing the area of the capacitor plate, the coupling capacitance formed between the data line and the second transparent electrode is reduced. On the other hand, because the two sides of the data line are the insulation regions, the electric charges gathered at the two sides of the data line are reduced, and therefore the coupling capacitance between the data line and the first transparent electrode is reduced. Compared with the solution of adding a shielding structure on the data line or adding an insulating layer on the data line, the embodiment of the invention can simultaneously reduce the coupling capacitance Cdc between the data line and the common electrode and the coupling capacitance Cpd between the data line and the pixel electrode. Compared with the solution of reducing the width of the data line, the embodiment of the invention can greatly improve the product quality and performance on the premise of ensuring the critical dimension CD and the yield of the data line.
The technical solution of the embodiment of the present invention is explained in detail by the specific embodiment below.
First embodiment
Fig. 2 to 6 are schematic views illustrating the preparation of an array substrate according to a first embodiment of the present invention, the array substrate being a High Aperture Advanced Super Dimensional Switching (HADS) HADS mode array substrate. The HADS mode is a display mode with a high aperture ratio and a wide viewing angle, which is developed based on an Advanced Super Dimension Switch (ADS) mode, and the viewing angle thereof may reach 178 degrees. The operating principle of the array substrate in the ADS mode and the HADS mode is that a multi-dimensional electric field is generated between a slit electrode layer and a plate electrode layer to drive liquid crystals to deflect. The process of manufacturing the HADS mode array substrate will be described with reference to fig. 2 to 6. In the figure, the left side is a thin film transistor region of the array substrate, and the right side is a data line region of the array substrate. The "patterning process" in this embodiment includes processes of depositing a film, coating a photoresist, exposing a mask, developing, etching, and stripping the photoresist, and is a well-established manufacturing process in the related art. The deposition may be performed by a known process such as sputtering, evaporation, chemical vapor deposition, etc., the coating may be performed by a known coating process, and the etching may be performed by a known method, which is not particularly limited herein.
In the first patterning process, a gate structure layer pattern is formed on the substrate through the patterning process. The gate structure layer includes a gate electrode and a gate line (not shown). Forming the gate structure layer pattern includes: a gate metal film is deposited on the substrate 10, a layer of photoresist is coated on the gate metal film, the photoresist is exposed and developed using a single tone mask, the gate metal film is etched and the remaining photoresist is stripped, forming a gate electrode 11 and a gate line (not shown) pattern, as shown in fig. 2. The gate metal film may be made of copper, aluminum, molybdenum, or other metals.
In the second patterning process, an active layer pattern is formed on the substrate on which the gate structure layer is formed through the patterning process. The forming of the active layer pattern includes: sequentially depositing a gate insulating layer and an active layer film on the substrate with the gate structure layer, coating a layer of photoresist on the active layer film, exposing and developing the photoresist by using a single-tone mask, etching the active layer film and stripping the residual photoresist to form patterns of a gate insulating layer 12 and an active layer 13, as shown in fig. 3. The gate insulating layer may be made of silicon oxide or silicon nitride, or a composite layer of silicon oxide and silicon nitride, or a composite layer of silicon oxide, silicon oxynitride, and silicon nitride. The active layer thin film is made of amorphous silicon (a-Si) to form an amorphous silicon thin film transistor.
In the third patterning process, a first transparent electrode pattern is formed on the substrate on which the pattern is formed through the patterning process. Forming the first transparent electrode pattern includes: depositing a transparent conductive film on the substrate with the pattern, coating a layer of photoresist on the transparent conductive film, exposing and developing the photoresist by using a single-tone mask, etching the transparent conductive film and stripping the residual photoresist to form a first transparent electrode 14 pattern, as shown in fig. 4. The transparent conductive film is made of transparent and conductive material, such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO).
In the fourth patterning process, a data structure layer pattern is formed on the substrate with the pattern through the patterning process. The data structure layer pattern includes a data line, a source electrode and a drain electrode. Forming the data structure layer pattern includes: depositing a source-drain metal film on the substrate with the patterns, coating a layer of photoresist on the source-drain metal film, exposing and developing the photoresist by using a single-tone mask, and etching the source-drain metal film to form the patterns of the data line 15, the source electrode 16 and the drain electrode 17, as shown in fig. 5. The source-drain metal film can be made of aluminum Al, molybdenum Mo, copper Cu, silver Ag and the like.
Subsequently, plasma treatment is performed such that a metal compound is formed on both sides of the data line 15 pattern, a metal compound is formed on the outer sides of the source electrode 16 and drain electrode 17 pattern, and the photoresist is stripped, as shown in fig. 6. The plasma treatment may employ O2、SF6/O2Or N2And the like, since the upper surfaces of the data line 15, the source electrode 16 and the drain electrode 17 are covered with the photoresist, plasma treatment is performed only for the exposed side surfaces of the data line 15, the source electrode 16 and the drain electrode 17, a metal compound as an insulating region is formed on both sides of the data line 15, a metal compound as an insulating region is formed on the outer sides of the source electrode 16 and the drain electrode 17, and metal as a conductive region is formed between the metal compounds. After the data line 15, the source electrode 16 and the drain electrode 17 are patterned, since the source electrode 16 is connected to the data line 15, 3 sides of the source electrode 16 are exposed, and four sides of the drain electrode 17 are exposed, and the outer sides of the source electrode 16 and the drain electrode 17 refer to 3 sides of the source electrode 16 and four sides of the drain electrode 17. In order to ensure the critical dimension CD and the yield of the data line, the width of the single-sided metal compound of the data line 15 is 3% to 27% of the width of the data line, i.e., the width of the single-sided metal compound (insulating region) is 5% to 30% of the width of the conductive region. For example, when the width of the data line 15 is 3 μm, the width of the one-sided metal compound is about 0.09 to 0.81 μm. Similarly, the width of the one-sided metal compound of the source electrode 16 is 3% to 27% of the width of the source electrode, and the width of the one-sided metal compound of the drain electrode 17 is 3% to 27% of the width of the drain electrode. In practical implementation, in order to reduce the influence of the data line on the charging rate, it may be considered to increase the thickness of the deposited source/drain metal film appropriately, so that the cross-sectional area of the conductive region of the present embodiment is equivalent to the cross-sectional area of the conventional data line, so as to offset the data lineInfluence of non-metal on both sides of the wire on charging.
Subsequent processes are the same as the related art HADS array substrate fabrication process, and a passivation layer 18 and a second transparent electrode 19 are patterned, as shown in fig. 7.
The HADS mode array substrate formed in this embodiment includes:
a substrate 10;
a gate electrode 11 disposed on the substrate 10;
a gate insulating layer 12 covering the gate electrode 11;
an active layer 13, a first transparent electrode 14, a data line 15, a source electrode 16 and a drain electrode 17 which are disposed on the gate insulating layer, wherein the data line 15, the source electrode 16 and the drain electrode 17 each include a conductive region and an insulating region, one end of the conductive region of the source electrode 16 is disposed on the active layer 13, one end of the conductive region of the drain electrode 17 is also disposed on the active layer 13, a channel region is formed between the source electrode 16 and the drain electrode 17, the other end of the conductive region of the source electrode 16 is connected to the conductive region of the data line 15, and the other end of the conductive region of the drain electrode 17 is connected to the first transparent electrode 14;
a passivation layer 18 covering the first transparent electrode 14, the data line 15, the source electrode 16, and the drain electrode 17;
and a second transparent electrode 19 disposed on the passivation layer 18.
In this embodiment, the first transparent electrode 14 may be a pixel electrode, and the second transparent electrode pattern 19 may be a common electrode.
In the array substrate provided by this embodiment, the data line, the source electrode and the drain electrode are designed to be a composite structure composed of the conductive region and the insulating region, so that not only is the coupling capacitance Cdc formed between the data line and the common electrode reduced, but also the coupling capacitance Cpd formed between the data line and the pixel electrode is reduced, and further the coupling capacitance Cgs between the gate electrode and the source electrode and the coupling capacitance Cgd between the gate electrode and the drain electrode are reduced. Specifically, since only the conductive region in the data line forms a coupling capacitance with the common electrode, which is equivalent to reducing the effective area of the data line forming the coupling capacitance or reducing the area of the capacitor plate, the coupling capacitance Cdc between the data line and the common electrode is reduced. Since the two sides of the data line are the insulation regions, the charges accumulated on the two sides of the data line are reduced, and thus the coupling capacitance Cpd between the data line and the pixel electrode is reduced. Since only the conductive region of the source electrode and the drain electrode forms a coupling capacitance with the gate electrode, which is equivalent to reducing the effective area of the coupling capacitance formed by the source electrode and the gate electrode, the coupling capacitance Cgs between the source electrode and the gate electrode and the coupling capacitance Cgd between the drain electrode and the gate electrode are reduced. The embodiment can effectively reduce the coupling capacitance, improve the product quality and performance and does not need to increase the times of the composition process on the premise of ensuring the key sizes of the data line, the source electrode and the drain electrode.
Second embodiment
Fig. 8 to 13 are schematic views illustrating the preparation of an array substrate according to a second embodiment of the present invention, the array substrate also being in HADS mode. In the figure, the left side is a thin film transistor region of the array substrate, and the right side is a data line region of the array substrate.
The first patterning process of this embodiment is the same as the first patterning process of the first embodiment described above, as shown in fig. 2.
In the second patterning process, an active layer and an ohmic contact layer pattern are formed on the substrate on which the patterns are formed through the patterning process. The forming of the active layer and the ohmic contact layer pattern includes: depositing a gate insulating layer, an active layer film and an ohmic contact layer film in sequence on the substrate with the gate structure layer, coating a layer of photoresist on the ohmic contact layer film, exposing and developing the photoresist by using a single-tone mask, etching the ohmic contact layer film and stripping the residual photoresist to form patterns of the gate insulating layer 12, the active layer 13 and the ohmic contact layer 20, wherein the ohmic contact layer 20 is arranged on the active layer 13, and the patterns of the ohmic contact layer 20 and the active layer 13 are the same, as shown in fig. 8.
In the third patterning process, a first transparent electrode pattern is formed on the substrate having the pattern formed thereon through a patterning process, which is the same as the third patterning process of the first embodiment, as shown in fig. 9.
In the fourth patterning process, a data structure layer pattern is formed on the substrate with the pattern through the patterning process. The data structure layer pattern includes a data line, a source electrode and a drain electrode. Forming the data structure layer pattern includes: depositing a source-drain metal film on the substrate with the patterns, coating a layer of photoresist on the source-drain metal film, exposing and developing the photoresist by using a single-tone mask, and etching the source-drain metal film to form the patterns of the data line 15, the source electrode 16 and the drain electrode 17, as shown in fig. 10.
Subsequently, plasma treatment is performed on the exposed outer sides of the data line 15, the source electrode 16, and the drain electrode 17 pattern, so that the data line 15, the source electrode 16, and the drain electrode 17 form a conductive region and an insulating region, as shown in fig. 11. The plasma processing method, the structural parameters of the conductive region and the insulating region, etc. are the same as those of the first embodiment, and are not described herein again.
Subsequently, the ohmic contact layer 20 between the source electrode 16 and the drain electrode 17 is etched to expose the surface of the active layer 13, a channel region is formed between the source electrode 16 and the drain electrode 17, and the photoresist is stripped, as shown in fig. 12. In this embodiment, the same set of dry etching equipment is used for plasma treatment and ohmic contact layer etching, so that no additional process is added in the scheme of this embodiment.
Subsequent processes are the same as the related art HADS array substrate fabrication process, and a passivation layer 18 and a second transparent electrode 19 are patterned, as shown in fig. 13.
The array substrate formed in this embodiment includes:
a substrate 10;
a gate electrode 11 disposed on the substrate 10;
a gate insulating layer 12 covering the gate electrode 11;
an active layer 13 disposed on the gate insulating layer, an ohmic contact layer 20, a first transparent electrode 14, a data line 15, a source electrode 16 and a drain electrode 17, wherein, the ohmic contact layer 20 is arranged on the active layer 13, the data line 15 comprises a conductive region and insulating regions positioned at two sides of the conductive region, the source electrode 16 and the drain electrode 17 both comprise a conductive region and an insulating region positioned at the outer side of the conductive region, one end of the conductive region of the source electrode 16 is arranged on the ohmic contact layer 20, one end of the conductive region of the drain electrode 17 is also arranged on the ohmic contact layer 20, the ohmic contact layer 20 between the source electrode 16 and the drain electrode 17 is etched away to expose the surface of the active layer 13, a channel region is formed between the source electrode 16 and the drain electrode 17, the other end of the conductive region of the source electrode 16 is connected with the conductive region of the data line 15, and the other end of the conductive region of the drain electrode 17 is connected with the first transparent electrode 14;
a passivation layer 18 covering the first transparent electrode 14, the data line 15, the source electrode 16, and the drain electrode 17;
and a second transparent electrode 19 disposed on the passivation layer 18.
In this embodiment, the first transparent electrode 14 may be a pixel electrode, and the second transparent electrode pattern 19 may be a common electrode. The materials and structural parameters of the film layers in this embodiment are the same as those in the first embodiment, and are not described again here.
As with the first embodiment, the array substrate of this embodiment can effectively reduce the coupling capacitance on the premise of ensuring the critical dimensions of the data line, the source electrode and the drain electrode. Meanwhile, the ohmic contact layer is arranged, so that the connection between the source electrode and the drain electrode and the active layer is further ensured, and the working reliability of the thin film transistor is improved. In addition, because the same set of dry etching equipment is adopted for plasma treatment and ohmic contact layer etching, the times of a composition process are not increased, and additional processes and equipment are not increased.
Although the technical solution of the embodiment of the present invention is described in the foregoing with the HADS mode array substrate, the technical solution of the present invention can be applied to array substrates of other modes, such as a Twisted Nematic (TN) mode and an Advanced Super Dimension Switch (ADS) mode, and will not be described herein again. Although the active layer of the foregoing embodiment adopts an a-Si structure, in practical implementation, the active layer may also adopt polysilicon to form a Low Temperature Polysilicon (LTPS) thin film transistor, and may also be Indium Gallium Zinc Oxide (IGZO), Indium Tin Zinc Oxide (ITZO) or other metal Oxide with semiconductor properties to form an Oxide (Oxide) thin film transistor, and the present invention is not limited in particular. Although the foregoing embodiment has been described by taking "the insulating region is located on both sides of the conductive region in the data line" as an example, in practical implementation, the insulating region may be disposed on one side of the conductive region, and a halftone or gray-tone mask may be used in the patterning process for forming the data structure layer pattern, so as to achieve the technical effect of effectively reducing the coupling capacitance.
Third embodiment
Based on the inventive concept of the foregoing embodiment, an embodiment of the present invention further provides a method for manufacturing an array substrate, where the method for manufacturing an array substrate includes:
and forming a data line, wherein the data line is a composite structure consisting of a conductive region and an insulating region, and the conductive region and the insulating region are distributed along the width direction of the data line.
Wherein the insulating region is located on both sides of the conductive region.
Forming the data line includes:
depositing a metal film, coating photoresist on the metal film, and forming a data line pattern through mask, exposure, development and etching processes;
forming the data lines into a conductive area and insulating areas positioned on two sides of the conductive area by plasma processing;
and stripping the residual photoresist.
The plasma treatment may be oxygen plasma treatment, nitrogen plasma treatment, sulfur hexafluoride and oxygen plasma treatment.
When the data line is formed, a source electrode and a drain electrode of the thin film transistor are also formed simultaneously, and the source electrode and the drain electrode comprise a conductive area and an insulating area.
Wherein, the width of the insulation region is 5% -30% of the width of the conductive region.
In one embodiment, the preparation method specifically comprises:
s11, forming a grid line, a grid electrode, a grid insulating layer and an active layer on the substrate;
s12, forming a first transparent electrode on the gate insulating layer;
s13, depositing a source-drain metal film on the substrate with the patterns, coating a layer of photoresist on the source-drain metal film, and etching the source-drain metal film after exposing and developing the photoresist to form data line, source electrode and drain electrode patterns;
s14, performing plasma treatment to form metal compound on the exposed outer sides of the data line, the source electrode and the drain electrode pattern;
s15, stripping the photoresist;
and S16, forming a passivation layer and a second transparent electrode.
Wherein, step S11 includes:
s111, forming a grid line and a grid electrode on the substrate;
and S112, sequentially depositing a gate insulating layer and an active layer film on the substrate on which the gate line and the gate electrode are formed, and forming an active layer on the gate insulating layer through a composition process.
Wherein, step S14 includes:
by the use of O2、SF6/O2Or N2And forming metal compounds as insulating regions on both sides of the data line, forming metal compounds outside the source and drain electrodes, forming metal as a conductive region between the metal compounds, and forming the width of the one-side insulating region to be 5-30% of the width of the conductive region.
In another embodiment, the preparation method specifically comprises:
s21, forming a grid line, a grid electrode, a grid insulation layer, an active layer and an ohmic contact layer on the substrate;
s22, forming a first transparent electrode on the gate insulating layer;
s23, depositing a source-drain metal film on the substrate with the patterns, coating a layer of photoresist on the source-drain metal film, and etching the source-drain metal film after exposing and developing the photoresist to form data line, source electrode and drain electrode patterns;
s24, performing plasma treatment to form metal compounds on two sides of the data line pattern and form metal compounds on the outer sides of the source electrode and the drain electrode;
s25, etching the ohmic contact layer between the source electrode and the drain electrode to expose the surface of the active layer;
s26, stripping the photoresist;
and S27, forming a passivation layer and a second transparent electrode.
Wherein, step S21 includes:
s211, forming a grid line and a grid electrode on the substrate;
s212, sequentially depositing a gate insulating layer, an active layer film and an ohmic contact layer film on the substrate on which the gate line and the gate electrode are formed, forming an active layer and an ohmic contact layer on the gate insulating layer through a composition process, wherein the ohmic contact layer is arranged on the active layer, and the patterns of the ohmic contact layer and the active layer are the same.
Wherein, step S24 includes:
by the use of O2、SF6/O2Or N2And forming metal compounds serving as insulating regions on the exposed outer sides of the data line, the source electrode and the drain electrode, wherein metal serving as a conductive region is arranged among the metal compounds, and the width of the single-side insulating region is 5-30% of that of the conductive region.
Fourth embodiment
The embodiment of the invention also provides a display device, which comprises a first substrate and a second substrate which are oppositely arranged, wherein the first substrate adopts the array substrate of the first embodiment or the second embodiment. The display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame or a navigator, etc.
In the description of the embodiments of the present invention, it should be understood that the terms "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, should not be construed as limiting the present invention.
In the description of the embodiments of the present invention, it should be noted that, unless explicitly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. An array substrate comprises a data line, wherein the data line is a composite structure composed of a conductive region and metal compounds positioned on two sides of the conductive region, the conductive region and the metal compounds are distributed along the width direction of the data line, the material of the conductive region comprises metal, the metal compounds are formed by carrying out plasma treatment on the metal, the effective area of a coupling capacitor is formed by reducing the data line so as to reduce the coupling capacitance between the data line and a common electrode, and meanwhile, the coupling capacitance between the data line and a pixel electrode is reduced by reducing charges accumulated on two sides of the data line.
2. The array substrate of claim 1, wherein the metal compound comprises a metal oxide or a metal nitride.
3. The array substrate of claim 1, further comprising a thin film transistor, wherein the source and drain electrodes of the thin film transistor comprise a conductive region and a metal compound.
4. The array substrate of any of claims 1 to 3, wherein the width of the metal compound is 5% to 30% of the width of the conductive region.
5. A display device, comprising a first substrate and a second substrate which are oppositely arranged, wherein the first substrate adopts the array substrate of any one of claims 1 to 4.
6. A preparation method of an array substrate is characterized by comprising the following steps:
forming a data line, wherein the data line is a composite structure consisting of a conductive region and metal compounds positioned on two sides of the conductive region, the conductive region and the metal compounds are distributed along the width direction of the data line, the material of the conductive region comprises metal, the metal compounds are formed by carrying out plasma treatment on the metal, the effective area of coupling capacitance is formed by reducing the data line so as to reduce the coupling capacitance between the data line and a common electrode, and meanwhile, the coupling capacitance between the data line and a pixel electrode is reduced by reducing charges accumulated on two sides of the data line.
7. The method of claim 6, wherein forming a data line comprises:
depositing a metal film, coating photoresist on the metal film, and forming a data line pattern through mask, exposure, development and etching processes;
forming the data lines into a conductive region and metal compounds located on both sides of the conductive region by plasma treatment;
and stripping the residual photoresist.
8. The method of claim 7, wherein the plasma treatment comprises one of: oxygen plasma treatment, nitrogen plasma treatment, sulfur hexafluoride and oxygen plasma treatment.
9. The manufacturing method according to claim 6, wherein when the data line is formed, a source electrode and a drain electrode of the thin film transistor are also simultaneously formed, the source electrode and the drain electrode including a conductive region and a metal compound.
10. The method according to any one of claims 6 to 9, wherein the width of the metal compound is 5% to 30% of the width of the conductive region.
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| CN111090204A (en) * | 2020-03-22 | 2020-05-01 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and display panel |
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