CN113740617A - 半导体检测器及其制造方法 - Google Patents

半导体检测器及其制造方法 Download PDF

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Publication number
CN113740617A
CN113740617A CN202110285017.6A CN202110285017A CN113740617A CN 113740617 A CN113740617 A CN 113740617A CN 202110285017 A CN202110285017 A CN 202110285017A CN 113740617 A CN113740617 A CN 113740617A
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semiconductor chip
semiconductor
electrode
detector
underfill
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CN202110285017.6A
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朴泽一幸
竹崎泰一
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Hitachi Ltd
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Hitachi Ltd
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Abstract

本发明提供能够提高半导体检测器的性能的技术。在半导体检测器中，将在以倒装芯片的方式连接后的半导体芯片(CHP1)与半导体芯片(CHP2)之间的间隙填充底部填充物(40)作为前提，在读取电极焊盘(PD1)与栅极端子(20)的经由凸块电极(BMP1)的连接构造的周围不形成底部填充物(40)。

Description

半导体检测器及其制造方法
技术领域
本发明涉及半导体检测器及其制造技术，例如，涉及在以下半导体检测器及其制造技术中应用并有效的技术：使通过向施加有漂移电场的耗尽层射入电磁波而生成的电荷载体在漂移电场中移动至读取电极并收集到电荷量，基于该电荷量来测定电磁波的能量。
背景技术
硅漂移检测器因在低能量时也具有较高的能量分辨率这一点和在冷却时能够使用珀尔帖元件而并非液态氮这一点等，广泛地用于X射线荧光分析装置。在该硅漂移检测器中，在对形成于半导体基板的pn结部施加反向偏置电压来使耗尽层扩大至半导体基板整体的状态下，使通过向耗尽层射入电磁波而生成的电荷载体在漂移电场中移动至读取电极。然后，在硅漂移检测器中，基于被收集在读取电极的电荷量来测定电磁波的能量。
在该硅漂移检测器中，由于读取电极的尺寸非常小，所以具有读取电极的静电电容(寄生电容)较小的优点。因此，在硅漂移检测器中，由寄生电容引起的噪声变小的结果，能够进行低能量的电磁波的测定，例如能够用于X射线荧光的测定。
例如，日本特开2019-190934号公报(专利文献1)中记载有与硅漂移检测器相关的技术。
现有技术文献
专利文献
专利文献1：日本特开2019-190934号公报
发明内容
发明所要解决的课题
基于硅漂移检测器的被收集在读取电极的电荷量的信号微弱。因此，将放大器与读取电极电连接，由该放大器根据基于被收集在读取电极的电荷量的信号来生成放大信号。然后，基于所生成的放大信号来测定电磁波的能量。
此处，包含读取电极的硅漂移检测器形成于第一半导体芯片，另一方面，放大器形成于与第一半导体芯片相独立的第二半导体芯片。而且，形成于第一半导体芯片的读取电极与形成于第二半导体芯片的放大器例如通过金属线电连接。
然而，在读取电极与放大器用金属线连接的情况下，金属线必然包含寄生电容、寄生电感。由此，由寄生电容、寄生电感引起的噪声会与从读取电极输出的信号重叠。尤其，由于基于被收集在读取电极的电荷量的信号微弱，所以即使是微小的噪声，也会带来较大的不良影响。因此，从提高包含硅漂移检测器和放大器的半导体检测器的电磁波能量的测定灵敏度的观点出发，期望能够抑制寄生电容、寄生电感的读取电极与放大器的电连接构造。
本发明的目的在于，提供能够提高半导体检测器的性能的技术。
通过本说明书的记载以及附图，其它的课题和新特征会变得清楚。
用于解决课题的方案
在一个实施方式的半导体检测器中，使通过向施加有漂移电场的耗尽层射入电磁波而生成的电荷载体在漂移电场中移动至读取电极并收集到电荷量，基于该电荷量来测定上述电磁波的能量。
此处，半导体检测器具备：第一半导体芯片，其形成有读取电极和与读取电极电连接的读取电极焊盘；以及第二半导体芯片，其具有与读取电极焊盘电连接的放大器，并且与第一半导体芯片以倒装芯片的方式连接。此时，除读取电极焊盘与放大器连接的第一连接部分以外，在第一半导体芯片与第二半导体芯片之间填充有底部填充物。
并且，一个实施方式的半导体检测器的制造方法具备以下各工序：准备第一半导体芯片的工序，该第一半导体芯片形成有读取电极和与读取电极电连接的读取电极焊盘；准备具有放大器的第二半导体芯片的工序；以读取电极焊盘与放大器电连接的方式将第一半导体芯片与第二半导体芯片以倒装芯片的方式连接的工序；以及除读取电极焊盘与放大器连接的第一连接部分以外，在第一半导体芯片与第二半导体芯片之间填充底部填充物的工序。
发明的效果如下。
根据一个实施方式，能够提高半导体检测器的性能。
附图说明
图1是示出半导体检测器的示意性结构的图。
图2是示出第一关联技术中的半导体检测器的安装结构的平面图。
图3是示出第一关联技术中的半导体检测器的安装结构的剖视图。
图4是示出第二关联技术中的半导体检测器的安装结构的平面图。
图5是示出第二关联技术中的半导体检测器的安装结构的剖视图。
图6是示出第一半导体芯片与第二半导体芯片的连接构造的放大图。
图7是说明实施方式1的基本思想的图。
图8是说明从基本思想派生出的思想的图。
图9是示出第一半导体芯片的结构的平面图。
图10是示出将第一半导体芯片与第二半导体芯片连接后的倒装芯片构造的剖视图。
图11是示出第一半导体芯片的结构的平面图。
图12是示出将第一半导体芯片与第二半导体芯片连接后的倒装芯片构造的剖视图。
图13是示出第一半导体芯片的结构的平面图。
图14是示出将第一半导体芯片与第二半导体芯片连接后的倒装芯片构造的剖视图。
图15是示出实施方式2中的半导体检测器的结构的剖视图。
图16是用于说明验证结果的图。
符号的说明
10—硅漂移检测器，11—p型半导体区域，12—读取电极，15—放大器，20—栅极端子，30—输出端子，40—底部填充物，50—粘接剂，60—粘接剂，100—半导体检测器，200—半导体检测器，300—半导体检测器，400—半导体检测器，BC—背接触面，BMP—凸块电极，BMP1—凸块电极，BMP2—凸块电极，BMP3—突起部，BMP4—突起部，CHP1—半导体芯片，CHP2—半导体芯片，GD1—导向部，GD2—导向部，GD3—导向部，OP1—开口部，PD—电极焊盘，PD1—读取电极焊盘，PD2—输出电极焊盘，PD3—焊盘部，PD4—焊盘部，R1—内电极，RX—外电极，SUB—半导体基板，W—金属线，WB—布线基板。
具体实施方式
在用于说明实施方式的所有图中，原则上对同一部件标注同一符号，并省略其重复的说明。此外，为了容易地理解附图，有时在平面图中也附加阴影线。
(实施方式1)
＜半导体检测器的结构＞
图1是示出半导体检测器的示意性结构的图。
图1中，半导体检测器100具有硅漂移检测器10和与硅漂移检测器10电连接的放大器(功放器)15。
硅漂移检测器10具有由例如添加有n型杂质(给予体)的硅构成的半导体基板SUB。作为硅漂移检测器10的构成要素的半导体基板SUB具有表面和背面，半导体基板SUB的表面被称作“窗口面”，而半导体基板SUB的背面被称作“环形面”。
如图1所示，在半导体基板SUB的表面侧，形成有与背接触面BC电连接的p型半导体区域11。由此，由添加有n型杂质的半导体基板SUB和p型半导体区域11形成pn结。然后，通过调整施加给背接触面BC的电压，来对pn结施加反偏压。其结果，耗尽层从pn结延伸，半导体基板SUB进行耗尽化。
接下来，如图1所示，在半导体基板SUB的背面的中心，形成有例如由n+型半导体区域构成的读取电极12。例如，读取电极12作为阳极电极发挥功能。而且，以呈同心圆状地包围读取电极12的方式形成有多个环形电极。尤其，环形电极包含形成于内周的内电极R1和形成于外周的外电极RX。此处，对内电极R1和外电极RX施加不同的电压。由此，会对具有耗尽化后的耗尽层的半导体基板SUB施加漂移电场。
接着，如图1所示，读取电极12电连接有放大器15。在该放大器15，例如形成有具有栅电极、源极以及漏极的场效应晶体管，场效应晶体管的栅电极与读取电极12电连接。
＜半导体检测器的工作＞
接下来，对半导体检测器100的工作进行说明。
首先，若从硅漂移检测器10的“窗口面”侧向半导体基板SUB的内部射入X射线(电磁波)，则存在于耗尽化后的半导体基板SUB的耗尽层射入X射线。这样，在耗尽层中，吸收X射线而形成电子·空穴对。即，由于X射线的能量比构成半导体基板SUB的硅的带隙大，所以X射线的能量用于使存在于硅的价带中的电子激发到硅的导带的能量。其结果，与X射线的能量对应地向导带激发多个电子。也就是说，X射线的能量越大，向导带激发的电子量(电荷量)越多。此时，在硅漂移检测器10中，由于在内电极R1与外电极RX之间施加有电位差，所以利用由该电位差生成的漂移电场，耗尽层所产生的电子朝向读取电极12移动。由此，电子累积在读取电极12。此处，读取电极12是阳极电极，假设电子作为被收集在读取电极12的电荷载体。而且，被收集在读取电极12的电子生成的微弱信号由与读取电极12电连接的放大器15放大，并从半导体检测器100输出放大信号。
之后，基于从半导体检测器100输出的放大信号来测定X射线的能量。例如，放大信号的大小与电子的电荷量成比例，并且根据X射线的能量，被收集在读取电极12的电荷量不同，因而通过对与电子的电荷量成比例的放大信号进行解析，能够测定所射入的X射线的能量。
＜第一关联技术的说明＞
安装构成上述的半导体检测器100。
以下，首先，对与半导体检测器的安装结构相关的第一关联技术进行说明。
此处，在本说明书中记载的“关联技术”不是公知技术，而是发明人发现的具有课题的技术，并且是成为本申请发明的前提的技术。
图2是示意性地示出第一关联技术中的半导体检测器的安装结构的平面图。
图2中，半导体检测器200具有形成有多个布线的布线基板WB。此处，图2是从布线基板WB的下表面侧观察的平面图。在该布线基板WB的上表面侧搭载有形成有硅漂移检测器10的半导体芯片CHP1，而在布线基板WB的下表面侧搭载有半导体芯片CHP2。图2中，从形成于布线基板WB的开口部OP1，能够看到搭载于布线基板WB的上表面侧的半导体芯片CHP1的背面(“环形面”)。
形成于半导体芯片CHP1的硅漂移检测器10具有读取电极12。另一方面，在半导体芯片CHP2形成有放大器。该放大器例如包括具有栅电极、源极以及漏极的场效应晶体管，半导体芯片CHP2具有与栅电极电连接的栅极端子20和用于输出由放大器生成的输出信号的输出端子30。而且，如图2所示，硅漂移检测器10的读取电极12与形成于半导体芯片CHP2的栅极端子20用金属线W电连接。此外，半导体芯片CHP2还具有DC电源供给端子、复位脉冲端子等。
图3是示意性地示出第一关联技术中的半导体检测器的安装结构的剖视图。
如图3所示，在布线基板的上表面搭载有形成有硅漂移检测器10的半导体芯片CHP1。另一方面，在布线基板WB的下表面搭载有形成有放大器的半导体芯片CHP2。而且，例如在第一关联技术中，形成于半导体芯片CHP1的读取电极12与形成于半导体芯片CHP2的栅极端子20用金属线W电连接。
＜第一关联技术存在的改良余地＞
然而，在读取电极12与栅极端子20用金属线W电连接的情况下，金属线W必然包含寄生电容、寄生电感。由此，由寄生电容、寄生电感引起的噪声会与从读取电极12输出的信号重叠。尤其，由于基于被收集在读取电极12的电荷量的信号微弱，所以即使是微小的噪声，也会带来较大的不良影响。因此，从提高包含硅漂移检测器10和放大器的半导体检测器200的X射线能量的测定灵敏度的观点出发，期望能够抑制寄生电容、寄生电感的读取电极12与栅极端子20的电连接构造。
＜第二关联技术的说明＞
关于这一点，有以下示出的第二关联技术。
图4是示意性地示出第二关联技术中的半导体检测器的安装结构的平面图。
图4中，半导体检测器300具有形成有多个布线的布线基板WB。此处，图4是从布线基板WB的下表面侧观察到的平面图。在该布线基板WB的上表面侧，搭载有形成有硅漂移检测器10的半导体芯片CHP1。图4中，从形成于布线基板WB的开口部OP1，能够看到搭载于布线基板WB的上表面侧的半导体芯片CHP1的背面(“环形面”)。
图4中，以与半导体芯片CHP1在平面上重叠的方式配置有半导体芯片CHP2。具体而言，以覆盖半导体芯片CHP1的“环形面”的方式形成有层间绝缘层(未图示)，并在该层间绝缘层上形成有多个焊盘PD。而且，以与形成有多个焊盘PD的焊盘层在平面上重叠的方式配置有半导体芯片CHP2。这样，在第二关联技术中的半导体检测器300中，半导体芯片CHP1与半导体芯片CHP2以在平面上重叠的方式层叠配置。
图5是示意性地示出第二关联技术中的半导体检测器的安装结构的剖视图。
如图5所示，在布线基板WB的上表面，搭载有形成有硅漂移检测器10的半导体芯片CHP1。而且，在半导体芯片CHP1的下表面，以与半导体芯片CHP1在平面上重叠的方式配置有形成有放大器的半导体芯片CHP2。即，在第二关联技术中，半导体芯片CHP1与半导体芯片CHP2以倒装芯片的方式连接。具体而言，如图5所示，形成于半导体芯片CHP1的读取电极焊盘PD1与形成于半导体芯片CHP2的栅极端子20经由凸块电极(突起电极)BMP1电连接。同样，形成于半导体芯片CHP1的输出电极焊盘PD2与形成于半导体芯片CHP2的输出端子30经由凸块电极BMP2电连接。
根据像这样构成的第二关联技术中的半导体检测器300，形成于半导体芯片CHP1的读取电极焊盘PD1与形成于半导体芯片CHP2的栅极端子20通过凸块电极BMP1电连接而不是金属线W。因此，能够抑制由金属线W引起的寄生电容、寄生电感所产生的噪声的増大。即，根据第二关联技术，半导体芯片CHP1与半导体芯片CHP2的电连接构造采用倒装芯片连接构造而不是金属线连接构造，由此能够减少寄生电容和寄生电感。
＜第二关联技术所存在的改良余地＞
这样，在第二关联技术中，由于读取电极12与栅极端子20的连接不使用金属线W，所以认为能够减少由金属线W引起的寄生电容和寄生电感。然而，根据发明人的研究，新发现：即使在倒装芯片连接构造中，从抑制由读取电极焊盘PD1与栅极端子20的连接构造引起的噪声的产生的观点出发，并不充分，需要改善的研究，因而以下对第二关联技术所存在的改良余地进行说明。
图6是示意性地示出半导体芯片CHP1与半导体芯片CHP2的连接构造的放大图。图6中，读取电极焊盘PD1与栅极端子20通过凸块电极BMP1电连接，并且输出电极焊盘PD2与输出端子30通过凸块电极BMP2电连接。这样，半导体芯片CHP1与半导体芯片CHP2以倒装芯片的方式连接。此处，如图6所示，在以倒装芯片的方式连接后的半导体芯片CHP1与半导体芯片CHP2之间的间隙，填充例如由绝缘树脂构成的底部填充物40。这是为了提高半导体芯片CHP1与半导体芯片CHP2的连接强度。
然而，底部填充物40由绝缘树脂构成，介电常数较高。因这一情况，发明人新发现：若以覆盖读取电极焊盘PD1与栅极端子20的经由凸块电极BMP1的连接构造的周围的方式填充底部填充物40，则无法忽视由底部填充物40引起的寄生电容，由此会引起噪声的増大。也就是说，在倒装芯片连接构造中，虽然能够减少由金属线W引起的寄生电容及寄生电感，而因由倒装芯片连接构造所不可欠缺的底部填充物40引起的寄生电容，难以抑制噪声。这一点是第二关联技术存在的改良余地。
因此，在本实施方式1中，对第二关联技术存在的改良余地进行了研究。以下，对该研究出的本实施方式1的技术思想进行说明。
＜实施方式1的基本思想＞
图7是说明本实施方式1的基本思想的图。
图7中，本实施方式1的基本思想是将在以倒装芯片的方式连接后的半导体芯片CHP1与半导体芯片CHP2之间的间隙填充底部填充物40作为前提，在读取电极焊盘PD1与栅极端子20的经由凸块电极BMP1的连接构造的周围不形成底部填充物40的思想。换言之，本实施方式1的基本思想是除读取电极焊盘PD1与栅极端子20的经由凸块电极BMP1的连接构造的周围以外，在以倒装芯片的方式连接后的半导体芯片CHP1与半导体芯片CHP2之间的间隙填充底部填充物40的思想。根据该本实施方式1的基本思想，能够利用底部填充物40确保以倒装芯片的方式连接后的半导体芯片CHP1与半导体芯片CHP2之间的连接强度，另一方面，由于在读取电极焊盘PD1与栅极端子20的经由凸块电极BMP1的连接构造的周围不存在底部填充物40，能够抑制由底部填充物40引起的寄生电容的増大。
也就是说，根据本实施方式1，通过使读取电极焊盘PD1与栅极端子20的经由凸块电极BMP1的连接构造的周围为介电常数较低的真空，能够抑制由介电常数较高的底部填充物40引起的寄生电容的増加。其结果，根据本实施方式1，能够抑制由寄生电容引起的噪声的増大，因而能够提高半导体检测器的X射线能量的测定灵敏度。
而且，图8是说明从基本思想派生出的思想的图。
如图8所示，从基本思想派生出的思想是如下的思想：不仅在读取电极焊盘PD1与栅极端子20的经由凸块电极BMP1的连接构造的周围不存在底部填充物40，在输出电极焊盘PD2与输出端子30的经由凸块电极BMP2的连接构造的周围也不存在底部填充物40。
根据该思想，不仅能够抑制由寄生电容引起的噪声与从读取电极焊盘PD1输出的微弱的信号重叠，还能够抑制由寄生电容引起的噪声与由形成于半导体芯片CHP2的放大器放大并从输出端子30输出的放大信号重叠。由此，根据从基本思想派生出的思想，能够更进一步提高X射线能量的测定灵敏度。
例如能够如下所示地实现本实施方式1的基本思想。
首先，准备形成有读取电极12以及与读取电极12电连接的读取电极焊盘PD1的半导体芯片CHP1，并且准备具有放大器的半导体芯片CHP2。接下来，以读取电极焊盘PD1与放大器电连接的方式以倒装芯片的方式连接半导体芯片CHP1与半导体芯片CHP2。之后，除读取电极焊盘PD1与放大器连接的第一连接部分之外，在半导体芯片CHP1与半导体芯片CHP2之间填充底部填充物40。这样，实现不在读取电极焊盘PD1与放大器连接的第一连接部分的周围形成底部填充物40这一基本思想。
以下，基于多个具体方案，来说明用于在除读取电极焊盘PD1与放大器连接的第一连接部分之外，在半导体芯片CHP1与半导体芯片CHP2之间填充底部填充物40的具体的研究方案。
＜具体方案1＞
接下来，对将上述的本实施方式1的基本思想具体化后的具体方案进行说明。
图9是示出半导体芯片CHP1的示意性结构的平面图。
图9中，在形成有硅漂移检测器10的半导体芯片CHP1的“环形面”，形成有呈同心圆状地配置的多个环形电极，并在形成有多个环形电极的层的上层配置有多个焊盘电极PD。而且，在多个焊盘电极PD的各个之上搭载有凸块电极BMP。具体而言，作为多个焊盘电极PD的一个，有与读取电极电连接的读取电极焊盘PD1，并在该读取电极焊盘PD1上搭载有凸块电极BMP1。并且，作为多个焊盘电极PD的另一个，有输出电极焊盘PD2，并在该输出电极焊盘PD2上搭载有凸块电极BMP2。
而且，如图9所示，在半导体芯片CHP1设有导向部GD1。该导向部GD1由焊盘部PD3和形成在焊盘部PD3上的突起部BMP3构成。此时，焊盘部PD3在形成有多个焊盘电极PD的焊盘层上形成。而且，突起部BMP3由与凸块电极BMP相同的材料构成。
接下来，图10是示意性地示出将半导体芯片CHP1与半导体芯片CHP2连接后的倒装芯片构造的剖视图。
图10中，形成于半导体芯片CHP1的读取电极焊盘PD1与形成于半导体芯片CHP2的栅极端子20用凸块电极BMP1连接。此处，将读取电极焊盘PD1与栅极端子20的经由凸块电极BMP1的连接构造称作“第一连接构造”。
图10中，形成于半导体芯片CHP1的输出电极焊盘PD2与形成于半导体芯片CHP2的输出端子30用凸块电极BMP2连接。此处，将输出电极焊盘PD2与输出端子30的经由凸块电极BMP2的连接构造称作“第二连接构造”。
这样，由“第一连接构造”和“第二连接构造”实现半导体芯片CHP1与半导体芯片CHP2的倒装芯片连接。而且，在具体方案1中，如图10所示，在“第一连接构造”与“第二连接构造”之间设有导向部GD1。该导向部GD1由焊盘部PD3和突起部BMP3构成。并且，通过在半导体芯片CHP1与半导体芯片CHP2之间设置导向部GD1，能够抑制“第一连接构造”被底部填充物40包围。也就是说，导向部GD1为了抑制“第一连接构造”被底部填充物40包围而设置。其结果，“第一连接构造”成为被介电常数比底部填充物40的介电常数较低的空隙包围。
根据以上内容，在具体方案1中将以下基本思想具体化：通过在“第一连接构造”与“第二连接构造”之间设置由焊盘部PD3和突起部BMP3构成的导向部GD1，而在“第一连接构造”的周围不形成底部填充物40。
例如，如下所示地实现具体方案1的结构。
首先，准备半导体芯片CHP1，该半导体芯片CHP1形成有读取电极、与读取电极电连接的读取电极焊盘PD1、输出电极焊盘PD2以及焊盘部PD3。接下来，准备半导体芯片CHP2，该半导体芯片CHP2形成有例如由具有栅电极、源极以及漏极的场效应晶体管构成的放大器。此时，半导体芯片CHP2具有与栅电极电连接的栅极端子20。
接着，在读取电极焊盘PD1上配置凸块电极BMP1，在输出电极焊盘PD2上配置凸块电极BMP2，并且在焊盘部PD3上配置突起部BMP3。然后，以经由凸块电极BMP1将读取电极焊盘PD1与栅极端子20连接，并且经由凸块电极BMP2将输出电极焊盘PD2与输出端子30连接的方式将半导体芯片CHP1与半导体芯片CHP2以倒装芯片的方式进行连接。由此，在半导体芯片CHP1与半导体芯片CHP2之间形成“第一连接构造”和“第二连接构造”，并且形成由焊盘部PD3和突起部BMP3构成的导向部GD1。
之后，在半导体芯片CHP1与半导体芯片CHP2之间填充底部填充物40。此处，从图10的箭头的方向将底部填充物40注入半导体芯片CHP1与半导体芯片CHP2之间。在该情况下，被注入到半导体芯片CHP1与半导体芯片CHP2之间的底部填充物40被导向部GD1拦截而不会到达“第一连接构造”的周围。由此，能够实现具体方案1的结构。
＜具体方案2＞
上述的具体方案1是设有包含突起部BMP3的导向部GD1的例子，该突起部BMP3由与凸块电极BMP相同的导电材料构成。相对于此，具体方案2是设有例如由以抗蚀材料为代表的绝缘材料构成的导向部GD2的例子。
图11是示出半导体芯片CHP1的示意性结构的平面图。图11中，设有例如由抗蚀材料等绝缘材料构成的导向部GD2，除此以外的结构与具体方案1的结构相同。
图12是示意性地示出将半导体芯片CHP1与半导体芯片CHP2连接后的倒装芯片构造的剖视图。
在具体方案2中，如图12所示，在“第一连接构造”与“第二连接构造”之间设有导向部GD2。该导向部GD2例如由抗蚀材料等绝缘材料构成。而且，在具体方案2中，也通过在半导体芯片CHP1与半导体芯片CHP2之间设置导向部GD2，能够抑制“第一连接构造”被底部填充物40包围。其结果，“第一连接构造”成为被介电常数比底部填充物40的介电常数较低的空隙包围。
根据以上内容，在具体方案2中将以下基本思想具体化：通过在“第一连接构造”与“第二连接构造”之间设置由绝缘材料构成的导向部GD2，而在“第一连接构造”的周围不形成底部填充物40。
例如，如下所示地实现具体方案2的结构。
首先，准备半导体芯片CHP1，该半导体芯片CHP1形成有读取电极、与读取电极电连接的读取电极焊盘PD1、输出电极焊盘PD2以及由抗蚀材料(抗蚀剂膜)构成的导向部GD2。此时，例如，在涂敷抗蚀材料后，通过使用光刻技术进行图案形成，能够形成由抗蚀剂膜构成的导向部GD2。
接下来，准备半导体芯片CHP2，该半导体芯片CHP2形成有例如由具有栅电极、源极以及漏极的场效应晶体管构成的放大器。此时，半导体芯片CHP2具有与栅电极电连接的栅极端子20。
接着，在读取电极焊盘PD1上配置凸块电极BMP1，在输出电极焊盘PD2上配置凸块电极BMP2，并且在焊盘部PD3上配置突起部BMP3。然后，以经由凸块电极BMP1将读取电极焊盘PD1与栅极端子20连接，并且经由凸块电极BMP2将输出电极焊盘PD2与输出端子30连接的方式将半导体芯片CHP1与半导体芯片CHP2以倒装芯片的方式进行连接。由此，在半导体芯片CHP1与半导体芯片CHP2之间形成“第一连接构造”和“第二连接构造”，并且形成由抗蚀材料构成的导向部GD2。
之后，在半导体芯片CHP1与半导体芯片CHP2之间填充底部填充物40。此处，从图12的箭头的方向将底部填充物40注入半导体芯片CHP1与半导体芯片CHP2之间。在该情况下，被注入到半导体芯片CHP1与半导体芯片CHP2之间的底部填充物40被导向部GD2拦截而不会到达“第一连接构造”的周围。由此，能够实现具体方案2的结构。
＜具体方案3＞
上述的具体方案1及具体方案2是为了在“第一连接构造”的周围不形成底部填充物40而设置导向部GD1(导向部GD2)的例子。相对于此，具体方案3是不仅为了在“第一连接构造”的周围不形成底部填充物40而设置导向部GD1、还为了也在“第二连接构造”的周围不形成底部填充物40而设置导向部GD3的例子。
图13是示出半导体芯片CHP1的示意性结构的平面图。图13中，例如，不仅设有导向部GD1，还设有导向部GD3，除此以外的结构与具体方案1的结构相同。
图14是示意性地示出将半导体芯片CHP1与半导体芯片CHP2连接后的倒装芯片构造的剖视图。
在具体方案3中，如图14所示，在“第一连接构造”与“第二连接构造”之间，不仅设有导向部GD1，还设有导向部GD3。该导向部GD3由焊盘部PD4和突起部BMP4构成。而且，在具体方案3中，通过在半导体芯片CHP1与半导体芯片CHP2之间设置导向部GD1和导向部GD3，能够抑制“第一连接构造”和“第二连接构造”双方被底部填充物40包围。其结果，“第一连接构造”及“第二连接构造”的各个连接构造被介电常数比底部填充物40的介电常数较低的空隙包围。
根据以上内容，在具体方案3中将以下基本思想具体化：通过在“第一连接构造”与“第二连接构造”之间设置导向部GD1和导向部GD3，而在“第一连接构造”的周围不形成底部填充物40，并且实现也在“第二连接构造”的周围不形成底部填充物40的结构。
例如，如下所示地实现具体方案3的结构。
首先，准备半导体芯片CHP1，该半导体芯片CHP1形成有读取电极、与读取电极电连接的读取电极焊盘PD1、输出电极焊盘PD2、焊盘部PD3以及焊盘部PD4。
接下来，准备半导体芯片CHP2，该半导体芯片CHP2形成有例如由具有栅电极、源极以及漏极的场效应晶体管构成的放大器。此时，半导体芯片CHP2具有与栅电极电连接的栅极端子20和输出放大信号的输出端子30。
接着，在读取电极焊盘PD1上配置凸块电极BMP1，并且，在输出电极焊盘PD2上配置凸块电极BMP2，并且，在焊盘部PD3上配置突起部BMP3，并且在焊盘部PD4上配置突起部BMP4。
然后，以经由凸块电极BMP1将读取电极焊盘PD1与栅极端子20连接，并且经由凸块电极BMP2将输出电极焊盘PD2与输出端子30连接的方式将半导体芯片CHP1与半导体芯片CHP2以倒装芯片的方式进行连接。由此，在半导体芯片CHP1与半导体芯片CHP2之间形成“第一连接构造”和“第二连接构造”。并且，在半导体芯片CHP1与半导体芯片CHP2之间形成由焊盘部PD3和突起部BMP3构成的导向部GD1、以及由焊盘部PD4和突起部BMP4构成的导向部GD3。
之后，在半导体芯片CHP1与半导体芯片CHP2之间填充底部填充物40。此时，被注入到半导体芯片CHP1与半导体芯片CHP2之间的底部填充物40被导向部GD1拦截而不会到达“第一连接构造”的周围，并且被导向部GD3拦截而不会到达“第二连接构造”的周围。由此，能够实现具体方案3的结构。
＜实施方式1的特征＞
接下来，对本实施方式1的特征点进行说明。
本实施方式1的特征点在于，为了将上述的基本思想具体化，在“第一连接构造”与“第二连接构造”之间形成有导向部GD1，以此来抑制“第一连接构造”被底部填充物40覆盖。由此，被注入到半导体芯片CHP1与半导体芯片CHP2之间的底部填充物40在到达“第一连接构造”之前被导向部GD1拦截。其结果，“第一连接构造”不会被底部填充物40覆盖，而成为被介电常数比底部填充物40的介电常数较低的空隙包围。由此，根据本实施方式1，能够抑制由底部填充物40引起的寄生电容的增大。即，根据本实施方式1，通过使读取电极焊盘PD1与栅极端子20的经由凸块电极BMP1的“第一连接构造”的周围为介电常数较低的空隙，能够抑制由介电常数较高的底部填充物40引起的寄生电容的增加。因此，根据本实施方式1，能够抑制由寄生电容引起的噪声的增大，因而能够提高半导体检测器100的X射线能量的测定灵敏度。
尤其，本实施方式1的特征点对于使“第一连接构造”的周围为空隙的结构具有很大的技术意义。这是因为，包含硅漂移检测器10的半导体检测器100在真空下使用。也就是说，在半导体检测器100中，使“第一连接构造”的周围为空隙的意思是使“第一连接构造”的周围为真空，由于真空的介电常数最低，所以从有效地减少寄生电容的观点出发，可以说真空是优选的。
此外，半导体检测器100在真空下使用的理由如下。在半导体检测器100中，需要减少成为噪声的原因的暗电流，温度越高，暗电流越大。由此，半导体检测器100例如使用珀尔帖元件进行冷却来减少成为噪声的暗电流。此时，若在空气中使用半导体检测器100，则因冷却后的半导体检测器100，有可能空气中的水分结露等而导致半导体检测器100的腐蚀或暗电流的增加。根据这样的理由，包括硅漂移检测器10的半导体检测器100在真空中使用。
本实施方式1的特征点例如通过上述的具体方案1、具体方案2以及具体方案3来实现。例如，作为具体方案1的优点，能够举出以下方面：由于导向部GD1的突起部BMP3由与凸块电极BMP相同的导电材料构成，所以容易进行高度调节，并且容易将导向部GD1的形成工序编入到“第一连接构造”的形成工序中。
并且，作为具体方案2的优点，能够举出以下方面：由于导向部GD2由以抗蚀材料为代表的绝缘材料构成，所以不用担心对接近配置的“第一连接构造”造成电的不良影响。再者，能够举出以下方面等：有效利用抗蚀剂能够同时形成多个微细图案的特征，不会对“第一连接构造”以外的其它端子(输出端子、DC电源端子、复位脉冲端子等)造成电的不良影响。
再有，作为具体方案3的优点，能够举出以下方面：不仅能够利用导向部GD1使“第一连接构造”的周围为介电常数较低的空隙，还能够利用导向部GD3使“第二连接构造”的周围也为介电常数较低的空隙。根据这样的具体方案3，不仅能够减少与从读取电极焊盘PD1输出的微弱的信号重叠的噪声，还能够减少在从输出端子30输出将微弱的信号放大后的放大信号时重叠的噪声。因此，能够实现半导体检测器100的X射线能量的测定灵敏度的进一步提高。
另外，作为具体方案3的应用，在放大器(功放器)15的栅极端子20和输出端子30以外的DC电源供给端子、复位脉冲端子等的周围还能够以不存在底部填充物的方式设置导向部。从进一步减少与微弱的信号重叠的噪声的观点出发，该结构是有效的。
(实施方式2)
＜实施方式2的基本思想＞
上述实施方式1的基本思想是将在以倒装芯片的方式连接后的半导体芯片CHP1与半导体芯片CHP2之间的间隙填充底部填充物40作为前提，并且在读取电极焊盘PD1与栅极端子20的经由凸块电极BMP1的“第一连接构造”的周围不形成底部填充物40的思想。
相对于此，本实施方式2的基本思想是在以倒装芯片的方式连接后的半导体芯片CHP1与半导体芯片CHP2之间的间隙不填充底部填充物40的思想。根据该基本思想，由于在“第一连接构造”的周围不夹有介电常数较高的底部填充物40，所以能够抑制由底部填充物40引起的寄生电容的增加。其结果，根据本实施方式2，能够减少与通过“第一连接构造”的微弱的信号重叠的噪声，因而能够提高半导体检测器100的X射线能量的测定灵敏度。
但是，在以倒装芯片的方式连接后的半导体芯片CHP1与半导体芯片CHP2之间的间隙不填充底部填充物40的情况下，半导体芯片CHP1与半导体芯片CHP2的连接强度降低的问题点变得明显。即，在实现本实施方式2的基本思想的情况下，需要进行研究来抑制半导体芯片CHP1与半导体芯片CHP2的连接强度降低。
因此，在本实施方式2中，为了抑制由底部填充物40引起的寄生电容的增加，在以倒装芯片的方式连接后的半导体芯片CHP1与半导体芯片CHP2之间的间隙不填充底部填充物40，将采用这样的基本思想作为前提，进行研究来抑制因采用该基本思想而引起的半导体芯片CHP1与半导体芯片CHP2的连接强度降低。以下，对该研究出的本实施方式2的技术思想进行说明。
＜实施方式2中的具体方案＞
图15是示出本实施方式2中的半导体检测器的示意性结构的剖视图。
图15中，半导体检测器400具有形成有硅漂移检测器10的半导体芯片CHP1。在半导体芯片CHP1形成读取电极焊盘PD1及输出电极焊盘PD2。而且，半导体检测器400具有与半导体芯片CHP1以倒装芯片的方式连接并具备开口部OP2的布线基板WB。布线基板WB与半导体芯片CHP1例如利用粘接剂50连接。而且，半导体检测器400具有与形成于半导体芯片CHP1的读取电极焊盘PD1电连接的放大器，并且具有配置于开口部OP2的内部且与半导体芯片CHP1以倒装芯片的方式连接的半导体芯片CHP2。在半导体芯片CHP2形成有由包含栅电极、源极以及漏极的场效应晶体管构成的放大器。此处，半导体芯片CHP2具有与栅电极电连接的栅极端子20和输出由放大器放大后的放大信号的输出端子30。
而且，如图15所示，形成于半导体芯片CHP1的读取电极焊盘PD1与形成于半导体芯片CHP2的栅极端子20用凸块电极BMP1连接(“第一连接构造”)。另一方面，如图15所示，形成于半导体芯片CHP1的输出电极焊盘PD2与形成于半导体芯片CHP2的输出端子30用凸块电极BMP2连接(“第二连接构造”)。
这样，由“第一连接构造”和“第二连接构造”实现半导体芯片CHP1与半导体芯片CHP2的倒装芯片连接。根据以上内容，在本实施方式2的半导体检测器400中，布线基板WB与半导体芯片CHP1以倒装芯片的方式连接，并且半导体芯片CHP1与半导体芯片CHP2也以倒装芯片的方式连接。但是，在本实施方式2中，在包含读取电极焊盘PD1与栅极端子20的经由凸块电极BMP1的“第一连接构造”和输出电极焊盘PD2与输出端子30的经由凸块电极BMP2的“第二连接构造”的半导体芯片CHP1与半导体芯片CHP2之间不存在底部填充物。由此，根据本实施方式2，在“第一连接构造”的周围不存在介电常数较高的底部填充物，因而能够抑制由底部填充物引起的寄生电容的增加。其结果，根据本实施方式2，能够减少与通过“第一连接构造”的微弱的信号重叠的噪声，因而能够提高半导体检测器400的X射线能量的测定灵敏度。
但是，如图15所示，在以倒装芯片的方式连接后的半导体芯片CHP1与半导体芯片CHP2之间的间隙不填充底部填充物的情况下，有半导体芯片CHP1与半导体芯片CHP2的连接强度降低的担忧。
关于这一点，在本实施方式2的半导体检测器400中，为了抑制半导体芯片CHP1与半导体芯片CHP2的连接强度降低，进行了以下所示的研究。即，如图15所示，半导体芯片CHP2由粘接剂60而固定在设于布线基板WB的开口部OP2的内部。由此，根据本实施方式2，即使不使用底部填充物，也能够利用粘接剂60将半导体芯片CHP2牢固地固定于布线基板WB，能够提高半导体芯片CHP1与半导体芯片CHP2的连接可靠性。
这样，根据本实施方式2中的半导体检测器400，由于在半导体芯片CHP1与半导体芯片CHP2之间不填充底部填充物，能够抑制由底部填充物引起的寄生电容的增加。而且，即使不使用底部填充物，通过研究利用粘接剂60将半导体芯片CHP2固定在设于布线基板WB的开口部OP2的内部，也能够抑制半导体芯片CHP1与半导体芯片CHP2的连接强度降低。因此，能够说本实施方式2中的半导体检测器400在兼顾抑制寄生电容的增加和抑制半导体芯片CHP1与半导体芯片CHP2的连接强度的降低这一点上优异。
＜效果的验证＞
最后，说明以下内容：根据实施方式1及实施方式2，例如与第一关联技术、第二关联技术相比，能够减少信号所含的噪声，其结果，能够提高半导体检测器的X射线能量的测定灵敏度。
图16是用于说明验证结果的图。
图16中，第一关联技术是读取电极与栅极端子用金属线连接的“引线接合连接构造”。在该第一关联技术中，“Mn-Ka半幅值(eV)”为130～135。
此处，“Mn-Ka半幅值(eV)”示出锰(Mn)的Kα线(5890eV)的峰值的半幅值，噪声越大则值越大。因此，“Mn-Ka半幅值(eV)”越小，则测定灵敏度越高且性能越好。
接下来，第二关联技术是读取电极焊盘与栅极端子通过凸块电极连接的“倒装芯片连接构造”。但是，在第二关联技术中，在形成有读取电极焊盘的第一半导体芯片与形成有栅极端子的第二半导体芯片之间填充有底部填充物。其结果，通过使用凸块电极来代替金属线，虽然金属线自身的寄生电容及寄生电感的影响消失，但由于由介电常数较高的底部填充物引起的寄生电容，第二关联技术与第一关联技术相比，“Mn-Ka半幅值(eV)”的值变大。
相对于此，在实施方式1(具体方案1)中，以“倒装芯片连接构造”为前提，在读取电极侧设置导向部。其结果，读取电极焊盘与栅极端子的经由凸块电极的“第一连接构造”被空隙包围，而不被底部填充物覆盖。根据该实施方式1(具体方案1)，“Mn-Ka半幅值(eV)”为127～132。这意味着，根据实施方式1(具体方案1)，由底部填充物引起的寄生电容的影响降低，信号所含的噪声减少。因此，可知：根据实施方式1(具体方案1)，与第一关联技术、第二关联技术相比，能够提高半导体检测器的X射线能量的测定灵敏度。
接着，在实施方式1(具体方案3)中，以“倒装芯片连接构造”为前提，在读取电极侧设置导向部，并且在输出端子侧也设置导向部。其结果，不仅读取电极焊盘与栅极端子的经由凸块电极的“第一连接构造”，输出电极焊盘与输出端子的经由凸块电极的“第二连接构造”也被空隙包围，而不被底部填充物覆盖。根据该实施方式1(具体方案3)，“Mn-Ka半幅值(eV)”为126～131。这意味着，不仅“第一连接构造”中的寄生电容的减少，“第二连接构造”中的寄生电容的减少也有效地作用于噪声的减少。因此，可知：根据实施方式1(具体方案3)，与第一关联技术、第二关联技术相比，也能够提高半导体检测器的X射线能量的测定灵敏度。
接着，在实施方式2中，以“倒装芯片连接构造”为前提，在形成有读取电极焊盘和输出电极焊盘的第一半导体芯片与形成有栅极端子和输出端子的第二半导体芯片之间不存在底部填充物。其结果，在实施方式2中，“第一连接构造”及“第二连接构造”也被空隙包围，而不被底部填充物覆盖。根据该实施方式2，“Mn-Ka半幅值(eV)”为127～132。因此，可知，通过实施方式2，与第一关联技术、第二关联技术相比，也能够提高半导体检测器的X射线能量的测定灵敏度。
根据以上内容，证实了：根据实施方式1及实施方式2，与第一关联技术、第二关联技术相比，能够减少信号所含的噪声，其结果，能够提高半导体检测器的X射线能量的测定灵敏度。
以上，基于上述实施方式具体地说明了由发明人完成的发明，但本发明并不限定于上述实施方式，当然能够在不脱离其主旨的范围内进行各种变更。
上述实施方式包含以下的方式。
(附记1)
一种半导体检测器，使通过向施加有漂移电场的耗尽层射入电磁波而生成的电荷载体在上述漂移电场中移动至读取电极并收集到电荷量，基于该电荷量来测定上述电磁波的能量，上述半导体检测器具备：
第一半导体芯片，其形成有上述读取电极和与上述读取电极电连接的读取电极焊盘；
布线基板，其与上述第一半导体芯片以倒装芯片的方式连接，并且具有开口部；以及
第二半导体芯片，其具有与上述读取电极焊盘电连接的放大器，并且配置在上述开口部内，且与上述第一半导体芯片以倒装芯片的方式连接，
上述第二半导体芯片利用粘接剂而固定于上述开口部的内部，
在包含上述读取电极焊盘与上述放大器连接的第一连接部分的上述第一半导体芯片与上述第二半导体芯片之间不存在底部填充物。

Claims (15)

1.一种半导体检测器，使通过向施加有漂移电场的耗尽层射入电磁波而生成的电荷载体在上述漂移电场中移动至读取电极并收集到电荷量，基于该电荷量来测定上述电磁波的能量，上述半导体检测器的特征在于，具备：
第一半导体芯片，其形成有上述读取电极和与上述读取电极电连接的读取电极焊盘；以及
第二半导体芯片，其具有与上述读取电极焊盘电连接的放大器，并且与上述第一半导体芯片以倒装芯片的方式连接，
除上述读取电极焊盘与上述放大器连接的第一连接部分以外，在上述第一半导体芯片与上述第二半导体芯片之间填充有底部填充物。
2.根据权利要求1所述的半导体检测器，其特征在于，
上述第一连接部分被介电常数比上述底部填充物的介电常数低的空隙包围。
3.根据权利要求1所述的半导体检测器，其特征在于，
上述放大器包含具有栅电极的场效应晶体管，
上述第二半导体芯片具有与上述栅电极电连接的栅极端子，
上述第一连接部分由上述读取电极焊盘与上述栅极端子的经由凸块电极的第一连接构造构成。
4.根据权利要求3所述的半导体检测器，其特征在于，
在上述第一半导体芯片设有用于抑制上述第一连接构造被上述底部填充物包围的第一导向部。
5.根据权利要求4所述的半导体检测器，其特征在于，
上述第一导向部由焊盘部和形成在上述焊盘部上的突起部构成。
6.根据权利要求5所述的半导体检测器，其特征在于，
上述突起部由与上述凸块电极相同的材料构成。
7.根据权利要求4所述的半导体检测器，其特征在于，
上述第一导向部由绝缘材料构成。
8.根据权利要求1所述的半导体检测器，其特征在于，
上述第二半导体芯片具有输出由上述放大器放大后的放大信号的输出端子，
上述第一半导体芯片具有与上述输出端子电连接的输出电极焊盘，
除上述读取电极焊盘与上述放大器连接的第一连接部分以及上述输出电极焊盘与上述输出端子连接的第二连接部分以外，在上述第一半导体芯片与上述第二半导体芯片之间填充有上述底部填充物。
9.根据权利要求8所述的半导体检测器，其特征在于，
上述第二连接部分也被介电常数比上述底部填充物的介电常数低的空隙包围。
10.根据权利要求8所述的半导体检测器，其特征在于，
上述第二连接部分由上述输出电极焊盘与上述输出端子的经由凸块电极的第二连接构造构成。
11.根据权利要求10所述的半导体检测器，其特征在于，
在上述第一半导体芯片设有用于抑制上述第二连接构造被上述底部填充物包围的第二导向部。
12.根据权利要求1所述的半导体检测器，其特征在于，
上述第一半导体芯片构成硅漂移检测器。
13.根据权利要求1所述的半导体检测器，其特征在于，
上述电磁波是X射线。
14.根据权利要求1所述的半导体检测器，其特征在于，
上述读取电极是阳极电极，
上述电荷载体是电子。
15.一种半导体检测器的制造方法，使通过向施加有漂移电场的耗尽层射入电磁波而生成的电荷载体在上述漂移电场中移动至读取电极并收集到电荷量，基于该电荷量来测定上述电磁波的能量，
上述半导体检测器的制造方法的特征在于，包含以下各工序：
(a)准备第一半导体芯片的工序，该第一半导体芯片形成有上述读取电极和与上述读取电极电连接的读取电极焊盘；
(b)准备具有放大器的第二半导体芯片的工序；
(c)以上述读取电极焊盘与上述放大器电连接的方式将上述第一半导体芯片与上述第二半导体芯片以倒装芯片的方式连接的工序；以及
(d)除上述读取电极焊盘与上述放大器连接的第一连接部分以外，在上述第一半导体芯片与上述第二半导体芯片之间填充底部填充物的工序。
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