CN113725280A - 一种低开启电压的超结rb-igbt器件 - Google Patents

一种低开启电压的超结rb-igbt器件 Download PDF

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CN113725280A
CN113725280A CN202111042571.8A CN202111042571A CN113725280A CN 113725280 A CN113725280 A CN 113725280A CN 202111042571 A CN202111042571 A CN 202111042571A CN 113725280 A CN113725280 A CN 113725280A
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吴玉舟
李菲
李欣
刘铁川
禹久赢
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Super Semiconductor Shanghai Co ltd
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Abstract

本发明公开了一种低开启电压的超结RB‑IGBT器件，包括：金属化集电极层；重掺杂多晶硅，所述重掺杂多晶硅设置于金属化集电极层的上方；氧化层，所述氧化层设置于掺杂多晶硅的上方；P型集电区，所述P型集电区关于金属化集电极层对称设置有两个P型集电区，P型集电区与金属化集电极层相邻设置；每个所述P型集电区相邻设置有N型重掺杂区，每个N型重掺杂区之间间隔设置；每个所述P型集电区与N型重掺杂区的上方设置有P型埋层。根据本发明，结构简单合理，器件背面通过P型埋层设计可将超结IGBT器件的开启电压降至0.1V，大大降低了器件的导通电压，从而降低了器件的导通损耗。

Description

一种低开启电压的超结RB-IGBT器件
技术领域
本发明涉及功率半导体技术领域，特别涉及一种低开启电压的超结RB-IGBT器件。
背景技术
绝缘栅双极晶体管(Insulated Gate Bipolar Transistor,IGBT)具有击穿电压高、电流密度大、导通电压低、开关频率较高、功率损耗较低等性能优势，IGBT已在变频器、UPS、汽车电子、轨道交通和智能电网等领域有广泛的应用。
超结IGBT器件是在是在传统IGBT器件结构基础上在漂移区增加重复排列的PN柱的新型功率半导体器件。PN柱的形成对器件耐压和正向导通压降等参数的优化与超结MOS有类似的效果。PN柱的引入使得超结IGBT器件在正向耐压时，除了Pbody-N-Drift结的纵向电场外，PN柱的相互耗尽产生横向电场，将传统IGBT器件三角形电场分布调制成近似于矩形分布，大大提高了超结IGBT器件的耐压能力。在保证器件一定击穿电压的前提下，就可以显著增大N-Drift层的浓度，使得器件在正向导通时，正向压降显著降低。高掺杂的N-Drift区可以使得器件工作在电导调制状态下时，注入外延层中电子空穴总量小于传统IGBT器件，从而在关断时需要抽取的空穴总量降低，同时P柱的辅助作用，使得超结IGBT器件可以迅速关断，大大减小拖尾电流时间，降低器件的关断损耗。
超结RB-IGBT(Reverse Blocking Insulated Gate Bipolar Transistor,逆阻型绝缘栅双极晶体管)是一种具有反向阻断能力的IGBT器件，正反向具有同等水平的耐压能力。受现代数字交流系统驱动和电能转换模块的发展和需求，超结RB-IGBT对于电能转换效率、能源利用率、系统可靠性等至关重要。两个超结RB-IGBT反并联可以形成双向开关，能对双向流动的电流进行控制。相比于传统的两个普通IGBT和两个FRD构成的双向开关，使用超结RB-IGBT不需要额外的FRD，节省元器件数量，同时减小了封装体积。因此超结RB-IGBT适合在矩阵变换器、交流斩波器等AC-AC变换装置中应用。
超结RB-IGBT器件背面存在由P型集电区和N型漂移区形成的PN结，因此在器件开启时集电极电压必须超过PN结的开启电压，一般为0.7V左右，超结IGBT器件的导通电压就是0.7V加上漂移区部分和顶层MOS部分的电压降。因此超结RB-IGBT器件的导通电压必然大于0.7V，由此产生的导通损耗必不可少。
发明内容
针对现有技术中存在的不足之处，本发明的目的是提供一种低开启电压的超结RB-IGBT器件，器件背面通过P型埋层设计可将超结IGBT器件的开启电压降至0.1V，大大降低了器件的导通电压，从而降低了器件的导通损耗。为了实现根据本发明的上述目的和其他优点，提供了一种低开启电压的超结RB-IGBT器件，包括：
金属化集电极层；
重掺杂多晶硅，所述重掺杂多晶硅设置于金属化集电极层的上方；
氧化层，所述氧化层设置于掺杂多晶硅的上方；
P型集电区，所述P型集电区关于金属化集电极层对称设置有两个P型集电区，P型集电区与金属化集电极层相邻设置；
每个所述P型集电区相邻设置有N型重掺杂区，每个N型重掺杂区之间间隔设置；
每个所述P型集电区与N型重掺杂区的上方设置有P型埋层。
优选的，所述P型埋层相邻设置有N型漂移区，所述N型漂移区中对称设置有P柱。
优选的，所述N型漂移区的上方设置有N型外延层，所述N型外延层中通过反应离子刻蚀形成有槽栅。
优选的，所述槽栅表面通过热生长形成有栅氧化层，且槽栅内淀积有重掺杂多晶硅形成的栅极，位于槽栅的两侧通过自对准工艺离子注入高温退火形成的P型体区。
优选的，所述槽栅的顶部两侧设置有重掺杂N型发射区，且所述N型外延层相邻的一侧设置有硼磷硅玻璃，所述硼磷硅玻璃的上方设置有上表面金属化发射极。
优选的，所述P型埋层的掺杂浓度与宽度和P型埋层4之间的间距根据器件击穿电压、漏电水平和要求的开启电压决定。
优选的，所述P型埋层与P柱不相连。
优选的，所述N型漂移区中的P柱与N型外延层中的P型体区不相连。
优选的，所述P柱通过多次外延与离子注入技术、高温扩散工艺或者通过深槽刻蚀和填充工艺形成。
本发明与现有技术相比，其有益效果是：利用P型埋层与N型漂移区的本征耗尽区形成阻挡层，在反向耐压时保证器件处于截止状态，控制漏电流在较低水平。正向导通时，较低的集电极电压就可减小耗尽区宽度形成电子通路，大大降低了超结RB-IGBT器件的开启电压，降低了正向导通压降，进而降低器件工作时的导通损耗。
附图说明
图1为根据本发明的低开启电压的超结RB-IGBT器件的结构示意图；
图2为根据本发明的低开启电压的超结RB-IGBT器件的一个实施例结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
参照图1-2，一种低开启电压的超结RB-IGBT器件，包括：金属化集电极层1；重掺杂多晶硅31，所述重掺杂多晶硅31设置于金属化集电极层1的上方；氧化层32，所述氧化层32设置于掺杂多晶硅31的上方；P型集电区2，所述P型集电区2关于金属化集电极层1对称设置有两个P型集电区2，P型集电区2与金属化集电极层1相邻设置；每个所述P型集电区2相邻设置有N型重掺杂区3，每个N型重掺杂区3之间间隔设置；每个所述P型集电区2与N型重掺杂区3的上方设置有P型埋层4，器件背面由单一的P型集电区4变化成类似MOS结构，两个P型埋层4与N型漂移区5在未加外部电压时本身会相互耗尽，N型漂移区5电阻率由超结RB-IGBT器件的击穿电压决定，仔细设计P型埋层4的掺杂浓度和两个P型埋层4之间的间距使得在未加外部电压时，两个P型埋层4之间的区域已完全耗尽，因此从集电极1到发射极14之间是关断的，保证超结RB-IGBT器件的反向耐压能力。当栅极10电压大于器件阈值电压，集电极开始加电压时，P型埋层4与N型漂移区5之间的耗尽区宽度减小，当两侧耗尽区宽度小于P型埋层4间距时便会形成电子通路，超结RB-IGBT器件正向导通。在控制器件的反向漏电水平情况下，集电极电压在低至0.1V时器件就可开启，大大降低超结RB-IGBT器件的开启电压。
进一步的，所述P型埋层4相邻设置有N型漂移区5，所述N型漂移区5中对称设置有P柱6。
进一步的，所述N型漂移区5的上方设置有N型外延层7，所述N型外延层7中通过反应离子刻蚀形成有槽栅8。
进一步的，所述槽栅8表面通过热生长形成有栅氧化层9，且槽栅8内淀积有重掺杂多晶硅形成的栅极10，位于槽栅8的两侧通过自对准工艺离子注入高温退火形成的P型体区11。
进一步的，所述槽栅8的顶部两侧设置有重掺杂N型发射区12，且所述N型外延层7相邻的一侧设置有硼磷硅玻璃13，所述硼磷硅玻璃13的上方设置有上表面金属化发射极14。
进一步的，所述P型埋层4的掺杂浓度与宽度和P型埋层4之间的间距根据器件击穿电压、漏电水平和要求的开启电压决定。
进一步的，所述P型埋层4与P柱6不相连。
进一步的，所述N型漂移区5中的P柱6与N型外延层7中的P型体区不相连。
进一步的，所述P柱6通过多次外延与离子注入技术、高温扩散工艺或者通过深槽刻蚀和填充工艺形成。
器件材料可采用体硅、碳化硅、砷化镓、或锗硅，且该器件背面不做重掺杂多晶硅和氧化层，结构和制造工艺更简单。但需要仔细设计P型埋层的浓度、宽度和间距以控制反向耐压时的漏电。
这里说明的设备数量和处理规模是用来简化本发明的说明的，对本发明的应用、修改和变化对本领域的技术人员来说是显而易见的。
尽管本发明的实施方案已公开如上，但其并不仅限于说明书和实施方式中所列运用，它完全可以被适用于各种适合本发明的领域，对于熟悉本领域的人员而言，可容易地实现另外的修改，因此在不背离权利要求及等同范围所限定的一般概念下，本发明并不限于特定的细节和这里示出与描述的图例。

Claims (9)

1.一种低开启电压的超结RB-IGBT器件，其特征在于，包括：
金属化集电极层(1)；
重掺杂多晶硅(31)，所述重掺杂多晶硅(31)设置于金属化集电极层(1)的上方；
氧化层(32)，所述氧化层(32)设置于掺杂多晶硅(31)的上方；
P型集电区(2)，所述P型集电区(2)关于金属化集电极层(1)对称设置有两个P型集电区(2)，P型集电区(2)与金属化集电极层(1)相邻设置；
每个所述P型集电区(2)相邻设置有N型重掺杂区(3)，每个N型重掺杂区(3)之间间隔设置；
每个所述P型集电区(2)与N型重掺杂区(3)的上方设置有P型埋层(4)。
2.如权利要求1所述的一种低开启电压的超结RB-IGBT器件，其特征在于，所述P型埋层(4)相邻设置有N型漂移区(5)，所述N型漂移区(5)中对称设置有P柱(6)。
3.如权利要求2所述的一种低开启电压的超结RB-IGBT器件，其特征在于，所述N型漂移区(5)的上方设置有N型外延层(7)，所述N型外延层(7)中通过反应离子刻蚀形成有槽栅(8)。
4.如权利要求3所述的一种低开启电压的超结RB-IGBT器件，其特征在于，所述槽栅(8)表面通过热生长形成有栅氧化层(9)，且槽栅(8)内淀积有重掺杂多晶硅形成的栅极(10)，位于槽栅(8)的两侧通过自对准工艺离子注入高温退火形成的P型体区(11)。
5.如权利要求3所述的一种低开启电压的超结RB-IGBT器件，其特征在于，所述槽栅(8)的顶部两侧设置有重掺杂N型发射区(12)，且所述N型外延层(7)相邻的一侧设置有硼磷硅玻璃(13)，所述硼磷硅玻璃(13)的上方设置有上表面金属化发射极(14)。
6.如权利要求1所述的一种低开启电压的超结RB-IGBT器件，其特征在于，所述P型埋层(4)的掺杂浓度与宽度和P型埋层4之间的间距根据器件击穿电压、漏电水平和要求的开启电压决定。
7.如权利要求1所述的一种低开启电压的超结RB-IGBT器件，其特征在于，所述P型埋层(4)与P柱(6)不相连。
8.如权利要求2所述的一种低开启电压的超结RB-IGBT器件，其特征在于，所述N型漂移区(5)中的P柱(6)与N型外延层(7)中的P型体区不相连。
9.如权利要求2所述的一种低开启电压的超结RB-IGBT器件，其特征在于，所述P柱(6)通过多次外延与离子注入技术、高温扩散工艺或者通过深槽刻蚀和填充工艺形成。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2622268A (en) * 2022-09-09 2024-03-13 Univ Warwick Silicon carbide lateral power semiconductor device

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