CN113724604A

CN113724604A - Display substrate and electronic equipment

Info

Publication number: CN113724604A
Application number: CN202111075268.8A
Authority: CN
Inventors: 先建波; 江亮亮; 周茂秀; 程敏; 李必奇; 乔勇
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Technology Development Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Technology Development Co Ltd
Priority date: 2021-09-14
Filing date: 2021-09-14
Publication date: 2021-11-30
Anticipated expiration: 2041-09-14
Also published as: CN113724604B

Abstract

The invention provides a display substrate and an electronic device. The display substrate comprises a substrate and, located on the substrate: a plurality of first scanning lines arranged in sequence in the column direction; a plurality of second scanning lines arranged in sequence in the row direction; the plurality of first scanning lines are connected with the grid driving circuit; the display substrate comprises at least three display sub-regions arranged along the row direction; the first scanning lines are electrically connected with the corresponding second scanning lines, and the connecting points of the first scanning lines and the second scanning lines are arranged along the diagonal line of the display sub-area where the connecting points are located. The embodiment can provide uniformity of RC of each display sub-region, and is beneficial to improving uniformity of charging rates of pixels at different positions, thereby being beneficial to improving display effect.

Description

Display substrate and electronic equipment

Technical Field

The invention relates to the field of display, in particular to a display substrate and electronic equipment.

Background

With the popularization of the full-screen concept in medium and small-sized display products, extremely fashionable appearances are also pursued for large-sized display products (such as televisions). For such a large-sized display device, the influence of in-plane resistance capacitance (RC for short) on the charging rate is increased due to its large size, and the charging rate uniformity is poor.

Disclosure of Invention

The embodiment of the invention provides a display substrate and an electronic device, and aims to solve the problem that the charging rate uniformity of a large-size display substrate is poor.

In a first aspect, an embodiment of the present invention provides a display substrate, including a substrate and, on the substrate:

a plurality of first scanning lines arranged in sequence in the column direction;

a plurality of second scanning lines arranged in sequence in the row direction;

the plurality of first scanning lines are connected with the grid driving circuit;

the display substrate comprises at least three display sub-regions arranged along the row direction;

the first scanning lines are electrically connected with the corresponding second scanning lines, and the connection points of the first scanning lines and the second scanning lines are arranged along the diagonal lines of the display sub-area where the connection points are located;

in at least one display sub-area, the distance from the connecting point of at least part of the first scanning line and the second scanning line to the diagonal of the display sub-area is H, the range of H is 0 to H,

where H = M2 × sin (arctan (L1/M1)), L1 is the length of the display sub-region in the column direction, M1 is the width of the display sub-region in the row direction, M2 is the sum of the widths of N-1 columns of pixels in the row direction, and the value of N is equal to the number of clock cycles of the gate driving circuit or half the number of clock cycles of the gate driving circuit.

In some embodiments, H ranges from 800 to 1800 microns; or 1200 and 1500 microns.

In some embodiments, h of the connection point of at least a part of the first scan line and the second scan line ranges from 180 to 500 micrometers.

In some embodiments, the sine of the angle between the diagonal and the row direction is K, the value of K being 1.6 to 3.5.

In some embodiments, the sine of the angle between the diagonal and the row direction is K, the value of K being 1.7 to 2.4.

In some embodiments, at least one of the display sub-regions comprises a local position, the slope K2 of said connection point of the local position around a fluctuating straight line.

The absolute value of the difference K-K2 is in the range of 0.05-0.2.

In some embodiments, the display substrate includes display sub-regions having the same size, and diagonals of the display sub-regions are parallel to each other.

In some embodiments, the number of display sub-regions is 4 to 6.

In some embodiments, at least a part of the second scan lines include a first portion and a second portion insulated from each other, wherein the first portion is electrically connected to the corresponding gate driving circuit, and the second portion is located on a side of the connection point away from the gate driving circuit.

In some embodiments, there are at least two adjacent second scan lines, the lengths of the second portions of the two adjacent second scan lines are not equal, and the difference between the lengths of the second portions of the two adjacent second scan lines is 1 to 9 sub-pixels in length.

In some embodiments, the length difference of the second portions of two adjacent second scan lines is 110-; or 120-.

In some embodiments, the sum of the lengths of the first and second portions of each of the second scan lines along the column direction is equal.

In some embodiments, the second portion of the second scan line is configured to act as a first common electrode line electrically connected to a common signal source.

In some embodiments, the display substrate includes a second common electrode line extending in the row direction, the second common electrode line includes a third portion and a fourth portion separated from each other, and a spacer is formed between the third portion and the fourth portion of the same second common electrode line;

the third part and the fourth part of the second common electrode line have a first orthographic projection on the substrate, the interval area of the second common electrode line has a second orthographic projection on the substrate, and the first part of the second scanning line has a third orthographic projection on the substrate;

the first orthographic projection and the third orthographic projection corresponding to the same pixel are separated, and the second orthographic projection and the third orthographic projection corresponding to the same pixel are overlapped.

In some embodiments, the distribution position of the connection points relative to the diagonal line along the row direction varies periodically.

In some embodiments, a period of change in the distribution positions of the connection points is equal to a clock period of the gate driving circuit or equal to one-half of the clock period of the gate driving circuit.

In some embodiments, the plurality of connection points corresponding to at least one of the gate driving circuits are symmetrically distributed about the diagonal line.

In some embodiments, in the case where J is an even number, a connection point corresponding to the J-th gate driving sub-circuit in the gate driving circuits cascaded in the Q column overlaps the diagonal line;

in the case that J is an odd number, a connection point corresponding to the jth gate driving sub-circuit in the gate driving circuits cascaded in the Q column is separated from the diagonal line;

wherein J is an integer, and Q is not less than J not less than 1.

In some embodiments, in the case where J is an even number, a connection point corresponding to the J-th gate driving sub-circuit in the gate driving circuits cascaded to the Q column is separated from the diagonal line;

in the case that J is an odd number, a connection point corresponding to the jth gate driving sub-circuit in the gate driving circuits cascaded in the Q column overlaps the diagonal line;

wherein J is an integer, and Q is not less than J not less than 1.

In some embodiments, each of the gate driving circuits includes 6 columns of cascaded gate driving sub-circuits, wherein connection points corresponding to the 1 st and 6 th gate driving sub-circuits overlap the diagonal line, connection points corresponding to the 2 nd and 3 rd gate driving sub-circuits are separated from and symmetrically distributed about the diagonal line, and connection points corresponding to the 4 th and 5 th gate driving sub-circuits are separated from and symmetrically distributed about the diagonal line.

In some embodiments, each of the gate driving circuits includes 7 columns of cascaded gate driving sub-circuits, wherein connection points corresponding to the 3 rd, 4 th and 5 th gate driving sub-circuits overlap the diagonal line, connection points corresponding to the 1 st and 2 nd gate driving sub-circuits are separated from and symmetrically distributed about the diagonal line, and connection points corresponding to the 6 th and 7 th gate driving sub-circuits are separated from and symmetrically distributed about the diagonal line.

In some embodiments, the display substrate further includes a third electrode line extending in the column direction, the third electrode line being used as one or more of a dummy electrode line and a first common electrode line, the third electrode line and the first scan line being manufactured by a single patterning process, and the third electrode line being insulated from both the first scan line and the second scan line.

In some embodiments, each of the gate driving circuits includes a plurality of gate driving sub-circuits, the gate driving sub-circuits of each of the gate driving circuits have equal number, each of the gate driving circuits corresponds to a plurality of second electrode lines and at least one third electrode line, the number of the second electrode lines of each of the gate driving circuits is equal, and the number of the third electrode lines of each of the gate driving circuits is equal.

In some embodiments, the display substrate includes a plurality of pixels, each pixel includes a plurality of sub-pixels arranged along the row direction, a region corresponding to each sub-pixel includes a color resistance region and a driving circuit region arranged along the column direction, and the first common electrode line includes fifth portions and sixth portions alternately arranged along the column direction;

the fifth part is positioned between two color resistance areas adjacent along the row direction, and the sixth part is positioned between two driving circuit areas adjacent along the row direction;

the size of the fifth portion is larger than the size of the sixth portion in the row direction.

In some embodiments, the second scan line includes seventh portions and eighth portions alternately arranged in the column direction, wherein the seventh portions are located between the color-resist regions of two sub-pixels adjacent in the row direction, and the eighth portions are located between two adjacent seventh portions;

the seventh portion has a size larger than that of the eighth portion in the row direction.

In some embodiments, the display substrate further includes a plurality of data lines extending along the column direction, at least two data lines are included between two adjacent second scan lines, and each data line includes a first segment extending along the column direction, a second segment extending along the column direction, and a bending segment connecting the first segment and the second segment;

in the row direction, the first segment corresponds to a seventh portion of an adjacent data line, the second segment corresponds to an eighth portion of an adjacent data line, and a distance between the first segment and the seventh portion is equal to a distance between the second segment and the eighth portion.

In some embodiments, two data lines adjacent to each of the second scan lines are symmetrically disposed about the second scan line.

In some embodiments, the first scan line and the second scan line are connected at the connection point by a via, and the via penetrates an insulating layer between the first scan line and the second scan line in a direction perpendicular to the substrate.

In some embodiments, in a cross section along the row direction and perpendicular to the substrate in a region corresponding to the via hole, a slope angle of the insulating layer is smaller than a slope angle of the first scan line, and a width of the second scan line is larger than a width of the first scan line.

In some embodiments, the insulating layer includes a first sub-layer and a second sub-layer stacked in a direction away from the substrate, and a thickness ratio of the first sub-layer to the second sub-layer is 2.1 to 4.7.

In some embodiments, each pixel of the display substrate comprises a plurality of sub-pixels arranged along the row direction, and each pixel at least comprises a red sub-pixel, a blue sub-pixel and a green sub-pixel;

the second scanning line is positioned between the red sub-pixel and the blue sub-pixel in an adjacent column, and the distance between the second scanning line and the red sub-pixel is greater than the distance between the second scanning line and the blue sub-pixel.

In some embodiments, in a case where the first scan line and the second scan line are connected through a via at the connection point, a portion of the via overlaps with a region corresponding to the red sub-pixel, and a portion of the via overlaps with a region corresponding to the blue sub-pixel.

In some embodiments, the distance between the via hole and the color filter of the red sub-pixel is less than the distance between the via hole and the color filter of the blue sub-pixel.

In some embodiments, the display substrate comprises a plurality of spacers, and the distance between the orthographic projection of the spacers on the substrate and the orthographic projection of the connection points on the substrate is not less than 1.2 times the maximum width of the orthographic projection of the spacers on the substrate.

In some embodiments, the display substrate comprises a plurality of groups of spacers arranged in an array, each group of spacers comprises a main spacer and a plurality of auxiliary spacers, wherein the size of the main spacer is larger than that of the auxiliary spacers;

the orthographic projection of the connecting points on the substrate is separated from the orthographic projection of the main spacer on the substrate, and the orthographic projection of each connecting point on the substrate is overlapped with the orthographic projection of at most one auxiliary spacer on the substrate.

In some embodiments, the liquid crystal display further comprises a plurality of main spacers and a plurality of sub spacers, and the number of connection points of the first scan line and the second scan line in one spacer cycle is greater than or equal to 2 and less than or equal to 6.

In some embodiments, the mat further comprises a plurality of main mats and a plurality of auxiliary mats, and the number ratio of the connecting points to the auxiliary mats in one mat period is R1, and R1 is 1/20-1/8.

In some embodiments, the mat further comprises a plurality of main mats and a plurality of auxiliary mats, and in one mat period, the number ratio of the main mats to the connecting points is R2, and R1 ranges from 1/6 to 1/4.

In some embodiments, two rows of pixels are disposed between the first scan line corresponding to the k-1 th row and the first scan line corresponding to the k-th row, and k is an integer greater than or equal to 2.

In some embodiments, the liquid crystal display further comprises a common electrode and a pixel electrode, and the common electrode and/or the pixel electrode are slit-shaped.

In a second aspect, an embodiment of the present invention provides an electronic device, including the display substrate described in any one of the above.

In the technical solution of this embodiment, the first scan lines along the column direction and the second scan lines along the row direction are arranged to transmit the gate driving signals, so that the gate driving unit providing the gate driving signals can be arranged on the DP side of the display substrate to reduce the width of the frame, which is beneficial to realizing a narrow frame. Furthermore, the display substrate is divided into a plurality of display sub-regions, so that the uniformity of the RC of each display sub-region can be improved, the uniformity of the charging rates of the pixels at different positions can be improved, and the display effect can be improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the description of the embodiments of the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.

Fig. 1 is a schematic structural view of a conventional display substrate in the related art;

FIG. 2 is a schematic view of a V-shaped display substrate according to the related art;

FIG. 3 is a schematic view of a display substrate according to an embodiment of the present invention;

FIG. 4 is a schematic view of a structure of another display substrate according to an embodiment of the present invention;

FIG. 5 is a schematic view of a structure of another display substrate according to an embodiment of the present invention;

FIG. 6 is a schematic view of a structure of another display substrate according to an embodiment of the present invention;

FIG. 7 is a schematic view of a structure of another display substrate according to an embodiment of the present invention;

FIG. 8 is a schematic view of a structure of another display substrate according to an embodiment of the present invention;

FIG. 9 is a schematic view of a structure of another display substrate according to an embodiment of the present invention;

FIG. 10 is a schematic view of a structure of another display substrate according to an embodiment of the present invention;

FIG. 11 is a schematic view of a structure of another display substrate according to an embodiment of the present invention;

FIG. 12 is a schematic view of a structure of another display substrate according to an embodiment of the present invention;

FIG. 13 is a schematic view of a structure of another display substrate according to an embodiment of the present invention;

FIG. 14 is a schematic view of a structure of another display substrate according to an embodiment of the present invention;

FIG. 15 is a schematic view of an arrangement of spacers according to an embodiment of the present invention;

FIG. 16 is a schematic view of a structure of another display substrate according to an embodiment of the present invention;

FIG. 17 is a schematic view of a structure of another display substrate according to an embodiment of the present invention;

FIG. 18 is a schematic structural diagram of another display substrate according to an embodiment of the invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the drawings, the size of each component, the thickness of a layer, or a region may be schematically illustrated for clarity. Therefore, one aspect of the present disclosure is not necessarily limited to the dimensions, and the shapes and sizes of the respective components in the drawings do not reflect a true scale. Further, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes, numerical values, and the like shown in the drawings.

At present, as the size of a display substrate increases, the influence of in-plane Resistance Capacitance (RC) on the charging rate is increased, and the uniformity of the charging rate is poor; this is particularly true for full-screen displays, which have complicated internal wiring and a large number of RC's. Specifically, the RC that affects the uniformity of the in-plane charging rate mainly includes at least one of: RC (abbreviated as CLK RC) brought by a clock signal line and RC (abbreviated as Gate RC) brought by a scanning line; RC (Data RC) brought by the Data line.

As shown in FIG. 1, for a conventional large-sized display substrate (i.e., a Normal panel), a clock signal (CLK signal) is introduced from a side COF (chip on film) on a DP (generally, the side where a source driver is disposed is called a DP side) and enters the panel along a column direction Y, that is: from the DP side to the DPO side (the side opposite to the DP side in the column direction Y), the influence of CLK RC is gradually increased, and the influence on the charging rate appears as the DP side to the DPO side, the charging rate is gradually decreased; and the large-sized display substrate is usually dual-driven, as shown in fig. 1, the Gate driving circuit (usually referred to as GOA circuit when the Gate driving circuit is located on the array substrate) is distributed on two opposite sides of the panel in the row direction X (i.e. the left and right sides shown in fig. 1), and the scanning signal (Gate signal) in each row is transmitted from two opposite sides of the panel in the row direction X to the center of the panel, that is: the Gate signals in each row start at opposite sides of the panel in the row direction X and end at the center of the panel, so that the charging rate of the pixels (pixels) gradually decreases from both sides in the row direction X toward the center thereof under the influence of the Gate RC. The Data signal (Data signal) is inputted from the COF terminal on the DP side, extends to the DPO side, and its Pixel charging rate gradually decreases under the influence of the Data RC.

Based on the foregoing, the position CLK RC shown in fig. 1 is small, the Gate RC is large, and the Data RC is small, the comprehensive influence of the position is small, and the position charging rate is excellent through simulation test; the position CLK RC is large, the Gate RC is large, the Data RC is large, the comprehensive influence of the position is large, and the charging rate of the position is poor through simulation test; the third position shown in fig. 1 is large in CLK RC, small in Gate RC and large in Data RC, and the third position has a large comprehensive influence, and is tested to be good in charging rate through simulation, as shown in table 1 below; that is, in position shown in fig. 1, the influences of CLK RC, Gate RC, and Data RC are all the largest, making it the point of the worst charging rate; in the in-plane design of the Normal panel, the RC distribution is extremely uneven, which makes the charging rate difference of the in-plane pixels large, and seriously affects the image quality of the panel, especially for the full-plane screen, because the charging rate is poor, the difference is more obvious.

As shown in fig. 2, in order to further improve the full-screen, in the related art, a super-narrow frame display substrate is proposed, in which a GOA circuit is disposed on the DP side of the panel, and compared to the Normal panel mentioned above, one more vertical scan line vgate extending in the column direction Y passes through a pixel of the display region, and is switched by a via structure (usually, the position of the via structure is a connection point a shown in fig. 2) to be connected with a horizontal scan line hgate extending in the row direction X, so as to implement row driving, thereby implementing super-narrow frames on both opposite sides in the row direction X and the DPO side; for the panel, the CLK signal is introduced from COFs on two opposite sides of the panel in the row direction X and introduced into the panel by a DP-side GOA circuit, the GOA scanning direction is scanned from the DP side to the DPO side, and for the Data signal, the Data signal is accessed from the DP-side COF terminal and extended to the DPO side, it should be understood that the Gate signal access method is an access method using a V-shaped line (a thin single-dot chain line as shown in fig. 2), the ultra-narrow frame display substrate may be defined as a V-shaped panel, and it should be noted that the V-shaped line refers to a line sequentially connecting the connection points a in the panel. As shown in fig. 2, Data RC appears to gradually increase from DP side to DPO side, CLK RC appears to gradually increase from opposite sides in the row direction X toward the center, and vgate RC appears to gradually increase from the junction toward opposite sides in the row direction X.

Based on the foregoing, the position CLK RC is small, the H Gate RC is small, the V Gate RC is large, and the Data RC is small as shown in fig. 2, the comprehensive influence of the position is small, and the charging rate of the position is good through simulation test; the position CLK RC shown in the figure 1 is large, the H Gate RC is large, the V Gate RC is small, the Data RC is large, the comprehensive influence of the position is large, and the position charging rate is good through simulation test; position CLK RC shown in FIG. 1 is large, H Gate RC is large, V Gate RC is large, Data RC is large, comprehensive influence of the position is large, and the position charging rate is poor through simulation test, which is shown in the following table 1; that is, in the design of the V-type panel shown in fig. 2, although the charging rate of the pixel at position (c) is improved, the position (c) has the greatest RC influence, and the charging rate is the worst point, which seriously affects the image quality of the panel, and the phenomena such as Mura (uneven brightness) and Crosstalk (Crosstalk) become more serious.

TABLE 1

In summary, the difference of the Pixel charging rates of the Normal panel and the V-type panel is large due to the different sizes of the resistive capacitors such as CLK, Gate and Data at different positions in the panel, and the difference has a greater influence on the large-size full-screen and seriously affects the image quality of the panel.

The embodiment of the invention provides a display substrate.

As shown in fig. 3, in some embodiments, the display substrate includes a substrate and a plurality of first scan lines H Gate and a plurality of second scan lines V Gate on the substrate, wherein the plurality of first scan lines H Gate are sequentially arranged in a column direction Y and extend along a row direction X, and the plurality of second scan lines V Gate are sequentially arranged in the row direction X and extend along the column direction Y. The first scanning line hgate and the corresponding second scanning line vgate are electrically connected at a connection point cp (connect point).

As shown in fig. 3, in some embodiments, the display substrate includes at least three display sub-regions arranged along the row direction X, and the display sub-regions have equal heights along the column direction Y and extend from the DP side to the DPO side of the display substrate.

Referring to fig. 3, in the present embodiment, the display area AA of the display substrate includes four display sub-areas AA1 to AA4, but the actual number of the display sub-areas is not limited thereto.

It should be noted that if fewer display sub-regions are provided, the number of correspondingly arranged gate driving circuits is smaller, which helps to reduce the cost, and if more display sub-regions are provided, the driving and controlling effect on the display substrate is better, and the pixel charging rate difference is lower.

In this embodiment, a gate driving circuit is taken as a GOA circuit disposed on an array substrate for an exemplary illustration, the gate driving circuit includes a plurality of gate driving sub-circuits, and in some exemplary embodiments, the gate driving circuit is specifically a GOA unit. Of course, the gate driving circuit may also be a driving IC (abbreviated as COG) bound on the array substrate or a driving IC (abbreviated as COF) disposed on the PCB.

In some embodiments, the display substrate may include display sub-regions having different sizes, and in other embodiments, the display substrate includes display sub-regions having the same size, and the diagonals DI of the display sub-regions are parallel to each other, which is helpful to further improve the uniformity of the display substrate.

In some of these embodiments, the number of display sub-regions is 3 to 6, which helps balance control effects and costs.

It should be understood that the state shown in fig. 3 does not represent the actual number and the actual position relationship of the first scan line hgate, the second scan line vgate and the connection point CP of the display substrate, and for convenience of understanding and clearer representation, in the embodiment, only a part of the first scan line hgate and the second scan line vgate and the corresponding connection point CP are exemplarily shown in fig. 3, and a part of the first scan line hgate, the second scan line vgate and the connection point CP are also omitted in fig. 3.

As shown in fig. 3, the connection point CP of the first scanning line hgate and the second scanning line vgate is arranged along the diagonal DI of the display sub-region where the connection point CP is located.

In some of these embodiments, each connection point CP overlaps the diagonal DI; in other embodiments, the position of each connection point CP may be offset from the diagonal DI of the display sub-area, and it is understood that the position of each connection point CP is located near the diagonal DI, and the positions of each connection point CP are distributed along the diagonal DI, but some of the connection points CP are not coincident with the diagonal DI.

In the technical solution of this embodiment, the Gate driving signal is transmitted by setting the first scan line H Gate along the column direction Y and the second scan line V Gate along the row direction X, so that the GOA unit providing the Gate driving signal can be disposed on the DP side of the display substrate to reduce the width of the frame, which is helpful for realizing a narrow frame. Furthermore, the display substrate is divided into a plurality of display sub-regions, so that the uniformity of the RC of each display sub-region can be improved, the uniformity of the charging rates of the pixels at different positions can be improved, and the display effect can be improved.

As shown in fig. 4, in some embodiments, the distance H from the connection point CP of the first and second scan lines hgate and vgate to the diagonal DI ranges from 0 to H.

The GOA circuit of each display sub-region comprises a plurality of GOA unit groups which are cascaded in a multi-stage mode, each GOA unit group comprises a plurality of GOA units, and the number of the GOA units included in each GOA unit group is equal.

Referring to fig. 4, a p-th group of GOA cell groups in the multistage cascade of GOA cell groups is shown, where a plurality of second scan lines V Gate connected to each GOA cell of the p-th group of GOA cell groups jointly form a p-th row second scan line group (V Gtae group), and a plurality of corresponding first scan lines H Gate form a corresponding p-th row first scan line group (H Gtae group). It should be noted that, in this embodiment, in order to conveniently illustrate the connection relationship between the GOA units and the second scan line vgate, the sequence of the GOA units shown in the figure does not represent the actual cascade sequence of the GOA units in the GOA unit group, and the cascade sequence is based on the text in fig. 4.

In this embodiment, a clock period (CLK period) of one GOA unit group is 8 for illustration, that is, one GOA unit group includes 8 GOA units, and accordingly, the GOA unit group corresponds to 8 second scan lines vgate arranged along the column direction Y and 8 first scan lines hgate arranged along the row direction X, and each first scan line hgate is electrically connected to a corresponding second scan line vgate at a connection point CP.

With continued reference to fig. 4, the position of each connection point CP fluctuates within a certain range of the diagonal DI of the display sub-area. The minimum distance between the connection point CP and the diagonal DI is 0, i.e. the positions of some connection points CP may coincide with the diagonal DI, e.g. the connection points corresponding to the 3 rd grade GOA unit.

The maximum distance between the connection point CP and the diagonal DI is H. H = M2 × sin (arctan (L1/M1)). L1 is the length of the display sub-area in the column direction Y, M1 is the width of the display sub-area in the row direction X, so L1/M1 corresponds to the sine value K = sin (arctan (L1/M1)) of the angle between the direction of the diagonal DI of the display sub-area and the row direction X, and can also be understood as the slope K of the diagonal DI of the display sub-area, such that arctan (L1/M1) is the size of the angle between the diagonal DI and the row direction X.

In some of these embodiments, the sine of the angle between the diagonal DI and the row direction X is 1.6 to 3.5, and correspondingly, arctan (L1/M1) ranges from about 57.9 ° to 74.1 °.

Optionally, in some preferred embodiments, the sine of the angle between the diagonal DI and the row direction X is 1.7 to 2.4, and correspondingly, the range of arctan (L1/M1) is about 59.5 ° to 67.3 °.

M2 is the sum of the widths of N-1 columns of pixels in the row direction X, and by way of example, a group of GOA cells comprising 8 GOA cells occupies a width of 7 pixels in the row direction X.

In the case of a display substrate of a fixed size, sin (arctan (L1/M1)) is constant, while the width of the pixels in the row direction X is also constant, for example: l1=800 microns, M1 =480 microns. Therefore, it can be understood that the distance between the connection point CP and the diagonal DI is controlled by controlling the value of K in the present embodiment.

In this embodiment, the value of K is equal to the number of clock cycles of the group of GOA cells or half of the number of clock cycles of the group of GOA cells. In this embodiment, the connection point CP fluctuates in a local range according to the clock cycle of the GOA unit group or half of the clock cycle, so that the difference between signals output by the GOA units in the same GOA unit group is smaller, which is helpful for improving the display uniformity of the display substrate.

Taking a display substrate as an example, for example, an 8K × 4K or 4K × 2K panel, the clock period of the display substrate is 8, K is selected to be equal to 8, the width of the pixels along the row direction X is about 372 μ M, sin (arctanL1/M1) =0.86, then H =7 × 372 × sin (arctanL1/M1) =2239 μ M can be obtained by calculating according to the above formula, and in practice, the value of K can be adjusted, for example, K is equal to 4, and the corresponding H value can be obtained.

In some embodiments, H = M2 × sin (arctan (L1/M1)), L1 is the length of the display sub-region in the column direction, M1 is the width of the display sub-region in the row direction, and M2 is the sum of the widths of the 3-5 columns of pixels in the row direction.

In some embodiments, the distance from the connecting point of at least part of the first scanning line and the second scanning line to the diagonal of the display sub-region is H, and H ranges from H/6 to H/2.

Alternatively, H can be controlled in the range of 500 to 2500 microns. Alternatively, H ranges from 800 to 1800 microns; or 1200 and 1500 microns, the charging rate of the display substrate can have higher uniformity.

Optionally, h of a connection point of at least a part of the first scan line and the second scan line ranges from 180 to 500 micrometers. h ranges from 200 to 400 microns; or 300-380 microns, the charging rate of the display substrate can have higher uniformity.

It will be appreciated that fig. 4 is a partial view of the sub-regions shown in fig. 3, for example: FIG. 4 is an AA region of AA4 of FIG. 3, and is described by taking the example that the slope K2 of the AA region is equal to the slope K = sin of display sub-region AA4 (arctan (L1/M1). in other words, the directions of the diagonals DI and K2 of display sub-region AA4 are parallel to each other.

Optionally, the slope K2 of the line around the undulation of the connection points of the local position of the display sub-region is not exactly equal to the slope K = sin of the display sub-region (arctan (L1/M1) — it is understood that in some embodiments the diagonals DI and K2 of the display sub-region AA4 may not be parallel.

Illustratively, the absolute value of the difference K-K2 is in the range of 0.05-0.2, preferably 0.07-0.12.

Illustratively, each connection point of the display sub-area is as far as possible from the maximum fluctuation range H of the straight line and is smaller than the H value. The absolute value of the difference H-H is in the range of 5-200 microns, preferably 10-50 microns.

In one embodiment, the distribution position of the connection points CP with respect to the diagonal DI varies periodically along the row direction X. It is understood that the relative positions of the connection points CP and the diagonal DI are periodically different, for example, the relative positions of the mth connection point CP in the pth-order GOA cell group and the mth connection point CP in the p + 1-th GOA cell group and the diagonal DI are the same in the row direction X.

In one embodiment, the period of variation of the distribution positions of the connection points CP is equal to or equal to half the clock period of the group of GOA cells. Illustratively, the clock period of each group of GOA cells is 8, the position distribution period of the connection point CP may be set to 4 or 8. In this way, the difference between the signals output by the GOA cells in the same GOA cell group is smaller, which contributes to improving the charging rate uniformity of the pixels of the display substrate.

In some embodiments, the plurality of connection points CP corresponding to each group of GOA units are symmetrically distributed about the diagonal DI.

Illustratively, as shown in fig. 4, the 1 st-level GOA unit is connected to the 1 st row first scan line hgate through the 8 th column second scan line vgate, the 2 nd-level GOA unit is connected to the 4 th row first scan line hgate through the 4 th column second scan line vgate, the 3 rd-level GOA unit is connected to the 3 rd row first scan line hgate through the 3 rd column second scan line vgate, the 4 th-level GOA unit is connected to the 2 nd row first scan line hgate through the 22 nd column second scan line vgate, the 5 th-level GOA unit is connected to the 5 th row first scan line hgate through the 5 th column second scan line vgate, the 6 th-level GOA unit is connected to the 6 th row first scan line hgate through the 1 st column second scan line vgate, the 7 th-level GOA unit is connected to the 7 th row first scan line hgate through the 7 th column second scan line vgate, and the 8 th row first scan line is connected to the 6 th row first scan line hgate through the 6 th column second scan line vgate.

With reference to fig. 4, different GOA units have different distances from the GOA unit groups, and different signal transmission delays, for example, the distance between the connection point corresponding to the GOA unit in level 1 and the GOA unit group is the largest, and accordingly, the signal delay is the largest, and the distance between the connection point corresponding to the GOA unit in level 8 and the GOA unit group is the smallest, and accordingly, the signal delay is the smallest. Therefore, by adjusting the sequence of the GOA units and the corresponding sequence of the connection points, the signal delay between adjacent scanning lines is balanced.

As shown in fig. 5, in some of the embodiments, in the case where J is even, the connection point CP corresponding to the J-th GOA cell among the GOA cells cascaded in the Q column overlaps the diagonal DI, and in the case where J is odd, the connection point CP corresponding to the J-th GOA cell among the GOA cells cascaded in the Q column is separated from the diagonal DI.

Similar to the embodiment shown in fig. 4, in fig. 5, the distance between the connection point corresponding to the GOA unit in level 1 and the GOA unit group is the largest, and accordingly, the signal delay is the largest, and the distance between the connection point corresponding to the GOA unit in level 8 and the GOA unit group is the smallest, and accordingly, the signal delay is the smallest. The local area takes a certain connecting point as the center, and the adjacent connecting points on two sides are distributed by taking the diagonal DI as the symmetry axis, so that the signal difference of the local area is favorably reduced, and the mura is reduced. For example: the corresponding connection points of the 2 nd and 4 th grade GOA units are distributed approximately along the diagonal DI as a symmetry axis with the 3 rd grade GOA unit as the center.

Similar to the embodiment shown in fig. 5, in some further embodiments, the connection point CP corresponding to the J-th GOA cell of the Q-column cascaded GOA cells is separated from the diagonal DI in case J is even, and the connection point CP corresponding to the J-th GOA cell of the Q-column cascaded GOA cells overlaps the diagonal DI in case J is odd. For example, in the local area, 2 connection points are taken as symmetry axes, and adjacent connection points on one side or two sides of the 2 connection points are approximately distributed in the symmetry axes, so that the signal difference in the local area is favorably reduced, and the mura is reduced. For example: the connecting points corresponding to the 1 st and 6 th-level GOA units are used as symmetry axes, and the connecting points corresponding to the 2 nd to 5 th-level GOA units are distributed by using a diagonal DI as a symmetry axis or using the symmetry axis as a symmetry axis.

In the above embodiment, J is an integer, and Q is greater than or equal to J and is greater than or equal to 1, it can be understood that the positions of the connection points CP are controlled to enable the connection points CP to be symmetrically distributed about the diagonal DI, so that the difference of signals output by each GOA unit is smaller, and the display uniformity of the display substrate is improved.

Exemplarily, in one embodiment, each group of GOA units includes 6 columns of cascaded GOA units, it is understood that K is equal to 6.

As shown in fig. 6, where the connection points CP corresponding to the 1 st and 6 th GOA cells overlap the diagonal DI, the connection points CP corresponding to the 2 nd and 3 rd GOA cells are separated from and symmetrically distributed about the diagonal DI, and the connection points CP corresponding to the 4 th and 5 th GOA cells are separated from and symmetrically distributed about the diagonal DI.

Illustratively, in yet another embodiment, as shown in fig. 7, each group of GOA cells includes 8 columns of cascaded GOA cells, wherein the connection points CP corresponding to the 3 rd, 4 th and 5 th GOA cells overlap with the diagonal DI, the connection points CP corresponding to the 1 st and 2 nd GOA cells are separated from and symmetrically distributed about the diagonal DI, and the connection points CP corresponding to the 6 th and 7 th GOA cells are separated from and symmetrically distributed about the diagonal DI.

In some of the embodiments, at least some of the second scanning lines vgate comprise a first portion 801 and a second portion 802 insulated from each other, wherein the first portion 801 is electrically connected to the corresponding GOA cell, and the second portion 802 is located at a side of the connection point CP away from the group of GOA cells.

It is understood that, along the column direction Y, each second scanning line vgate is disconnected at a connection point CP, wherein the first portion 801 is used for connecting the GOA unit and the first scanning line hgate, and the second portion 802 is insulated from the first portion 801 and the first scanning line hgate of the same second scanning line vgate. In implementation, the first portion 801 and the second portion 802 of the same second scan line vgate are manufactured by a one-time patterning process, and the first portion 801 and the second portion 802 can form a gap by adjusting a mask.

In some embodiments, there are at least two adjacent second scan lines vgate, and the lengths of the second portions 802 thereof are not equal, which can be understood as that the distances between the connecting points CP of the two adjacent second scan lines vgate and the DP side of the display substrate are not equal. By adjusting the lengths of the second portions 802 of the different second scan lines vgate, the difference of the signals output by the GOA units can be adjusted, which is helpful for improving the charging rate uniformity of the pixels of the display substrate.

In some embodiments, along the row direction X, lengths of the second portions 802 of the plurality of second scanning lines V Gate corresponding to the same GOA unit group sequentially change, where the sequentially changing may be sequentially increasing in length or sequentially decreasing in length. As shown in fig. 8, in one embodiment, the lengths of the second portions 802 of the second scanning lines vgate in each group of GOA units decrease sequentially along the row direction X, specifically, along the left-to-right direction. By adjusting the lengths of the second portions 802 of the second scan lines vgate to be sequentially changed, the difference of the signals output by the GOA units can be adjusted, so that the influence caused by the RC is reduced, and the charging rate uniformity of the pixels of the display substrate is improved.

Illustratively, in a case where the lengths of the second portions 802 of the second scan lines vgate are sequentially changed, the difference between the lengths of the second portions 802 of two adjacent second scan lines vgate is the smallest, and the difference between the lengths of the second portions 802 of the first and last second scan lines vgate is the largest.

Illustratively, the difference between the lengths of the second portions 802 of two adjacent second scan lines vgate is 1-9 sub-pixel lengths. For example: differing by 6 sub-pixel lengths.

Illustratively, the length difference of the second portions 802 of two adjacent second scan lines vgate is 100um to 2700 um. Preferably, the length difference of the second portions 802 of the two adjacent second scan lines V Gate is 110-.

For example, the second scanning line vgate may be further divided into a plurality of second portions, i.e., the second scanning line vgate excludes the portion connected to the GOA unit, and the remaining portion may be further divided into at least 2 independent line segments. These individual line segments may be equal or unequal. For example: the second portion of the second scan line vgate is divided into 3 unequal line segments that can be used as a repair line for repairing defective pixels. For example: the grid lines in the Nth row (N is an integer larger than or equal to 1) have flaws or are damaged, and the adjacent grid lines in the N + P (N, P is an integer larger than or equal to 1) are connected through the second part of the second scanning line V Gate.

In some embodiments, the sum of the lengths of the first portion 801 and the second portion 802 of each second scan line vgate in the column direction Y is substantially equal, which is to be understood that the total lengths of the second scan lines vgate are all equal, which is helpful for improving the uniformity of the thicknesses of different areas of the display substrate, but the positions of the connection points CP corresponding to the second scan lines vgate are different, and accordingly, each second scan line vgate is disconnected at different positions to form the first portion 801 and the second portion 802, and the lengths of the first portions 801 of the second scan lines vgate may not be equal.

In some embodiments, the second portion 802 of the second scan line V Gate may be used as a dummy electrode line to balance different thicknesses of the display substrate, and in other embodiments, the second portion 802 of the second scan line V Gate is used as a first common electrode line COM1, and the first common electrode line COM1 is electrically connected to a common signal source, so as to balance different thicknesses of the display substrate and provide a common signal.

As shown in fig. 9, in some embodiments, the display substrate further includes a second common electrode line COM2 extending along the row direction X, the second common electrode line COM2 includes a third portion COM2-1 and a fourth portion COM2-2 separated from each other, and a space 901 is formed between the third portion COM2-1 and the fourth portion COM2-2 of the same second common electrode line COM 2.

The third portion COM2-1 and the fourth portion COM2-2 of the second common electrode line COM2 have a first orthographic projection on the substrate, the spacer regions 901 of the second common electrode line COM2 have a second orthographic projection on the substrate, and the first portion 801 of the second scan line V Gate has a third orthographic projection on the substrate.

Referring to fig. 9, an upper one of the two second common electrode lines COM2 shown in fig. 9 is the second common electrode line COM2 of the sub-pixel corresponding to the second scan line V Gate labeled in the figure, and a lower one is the second common electrode line COM2 corresponding to the sub-pixel not shown in the figure. The upper one of the second common electrode lines COM2 is disconnected at the second scanning line V Gate, while the lower one of the second common electrode lines COM2 is still continuous at the overlapping with the second scanning line V Gate noted in the drawing. When viewed in a direction perpendicular to the display substrate, the corresponding second common electrode line COM2 and the second scan line V Gate do not overlap, so that mutual interference possibly generated between the second scan line V Gate and the second common electrode line COM2 can be reduced, which is helpful for improving the display effect.

As shown in fig. 10, in some embodiments, the display substrate further includes a third electrode line extending in the column direction Y, the third electrode line is used as a dummy electrode line, and the third electrode line may also be used as a common electrode line, which may be, for example, the first common electrode line COM1, and the third electrode line is insulated from both the first scan line H Gate and the second scan line V Gate. The third electrode line and the first scan line hgate or the pixel electrode can be manufactured by one-time composition process, so that the process is saved, and the cost is saved.

In some embodiments, each of the GOA cell groups includes a plurality of GOA cell groups, each of the GOA cell groups includes a plurality of GOA cells, the number of the GOA cells included in each of the GOA cell groups is equal, each of the GOA cell groups corresponds to a plurality of second electrode lines and at least one third electrode line, the number of the second electrode lines corresponding to each of the GOA cell groups is equal, and the number of the third electrode lines corresponding to each of the GOA cell groups is equal.

As shown in fig. 10, in an exemplary embodiment, each GOA cell group includes 8 GOA cells, and the display substrate further includes one third electrode line corresponding to each GOA cell group, and accordingly, in one period, 8 second scan lines vgate and one third electrode line are included.

In other embodiments, the number of third electrode lines in each fluctuation period may be set as needed, for example, 1 to 4 third electrode lines may be set in one fluctuation period, or 3 to 6 third electrode lines may be set in 2 fluctuation periods.

For example, two third electrode lines, eight second scanning lines vgate, and the like may be disposed in one fluctuation period, and the number collocation thereof is not further limited and described herein. Here, the fluctuation period refers to a period of fluctuation of the position of the above-mentioned connection point CP, and may be, for example, the above-mentioned clock period or half of the clock period.

In some embodiments, the display substrate includes a plurality of pixels, each including a plurality of sub-pixels, which may include, for example, a red sub-pixel R, a blue sub-pixel B, and a green sub-pixel G. In each pixel unit, the number of the same-color sub-pixels may be one or multiple, and for example, a certain display substrate includes one red sub-pixel R, one blue sub-pixel B, and two green sub-pixels G.

It is understood that in some embodiments, one or more of the third electrode lines and the first common electrode lines COM1 may be used for the touch electrode leads. For example: when the common electrode is reused as a touch electrode, one or more of the third electrode line and the first common electrode line COM1 may be used for a touch electrode lead.

It will be appreciated that in some embodiments, there may be one second scan line for each column of sub-pixels; alternatively, one or more pixels may correspond to one second scanning line in the row direction. For example: the red sub-pixel R, the blue sub-pixel B, and the green sub-pixel G correspond to one second scan line.

In some embodiments, the third electrode line corresponds to a column of sub-pixels; or the third electrode lines correspond to one or more pixels. For example: and 3 pixel units correspond to one second scanning line.

In some embodiments, the first common electrode line COM1 corresponds to a column of sub-pixels; or the first common electrode line COM1 corresponds to one or more pixels. The red sub-pixel R, the blue sub-pixel B, and the green sub-pixel G correspond to one second scan line.

In some embodiments, the sub-pixels of each pixel are arranged along a row direction X, and the sub-pixels of the same color in the corresponding different pixels are arranged along a column direction Y.

As shown in fig. 11, a region corresponding to each sub-pixel is referred to as a sub-pixel region 1101, each sub-pixel region 1101 includes a color resistance region 11011 and a driving circuit region 11012 arranged along a column direction Y, it can be understood that the color resistance region 11011 corresponds to a light emitting region of the sub-pixel, and driving circuits required by the sub-pixel are mainly distributed in the driving circuit region 11012 of the sub-pixel. For example, one or more thin film transistors corresponding to the sub-pixels may be disposed in the driving circuit region 11012.

As shown in fig. 9, in some embodiments, the display substrate further includes a first common electrode line COM1 disposed along the column direction Y, and it should be noted that the first common electrode line COM1 may be the second portion 802 of the second scan line V Gate, or may be a first common electrode line COM1 disposed independently.

The first common electrode line COM1 includes fifth sections 905 and sixth sections 906 alternately arranged in the column direction Y, the fifth sections 905 being located between two color resistance regions 11011 adjacent in the row direction X, the sixth sections 906 being located between two drive circuit regions 11012 adjacent in the row direction X, the size of the fifth sections 905 being larger than that of the sixth sections 906 in the row direction X.

Referring to fig. 9 and also referring to the relative positions of the color resistance regions 11011 and the driving circuit regions 11012 shown in fig. 11, it can be understood that the line widths of the portions of the first common electrode line COM1 located between the color resistance regions 11011 of two adjacent sub-pixels along the row direction X are relatively wide, and the line widths located between the driving circuit regions 11012 of two adjacent sub-pixels along the row direction X are relatively narrow.

As shown in fig. 11, in some embodiments, the second scan line V Gate includes seventh portions 1107 and eighth portions 1108 alternately arranged in the column direction Y, the seventh portions 1107 are located between the color resistance regions 11011 of two adjacent sub-pixels in the row direction X, the eighth portions 1108 are located between two adjacent seventh portions 1107, and the size of the seventh portions 1107 in the row direction X is larger than that of the seventh portions 1107.

Referring to fig. 11, it can be understood that, in the row direction X, a portion of the second scan line vgate between two adjacent sub-pixels has a relatively wide line width, and a portion of the second scan line vgate between the driving circuit regions 11012 has a relatively narrow line width.

In this embodiment, the two line width adjustment modes can be implemented separately or applied simultaneously. The purpose of adjusting the line width is to play a light-blocking role of the trace between the color-blocking regions 11011 of the sub-pixels, for example: when the display device is not provided with a Black Matrix (BM), a certain shielding effect is achieved; or, when the display device has a black matrix, the light blocking can be enhanced in cooperation with the black matrix. Therefore, the line width of the second scanning line V Gate or the first common electrode line COM1 is increased between the adjacent color resistance regions 11011, so that a certain shading effect can be achieved, the color crosstalk phenomenon of sub-pixels with different colors can be avoided, and the display effect can be improved. And some traces along the row direction X may be further included between the two driving circuit regions, which may include, for example and without limitation, the second common electrode line COM2, and the like, and by reducing the trace width of the first common electrode line COM1 and the second scan line vgate between the driving circuit regions, the overlapping area of the first common electrode line COM1 and the second scan line vgate with these transverse traces can be reduced, thereby helping to reduce RC and improving the display effect. The overlapping area can be understood as the overlapping area of the orthographic projection of the traces on the substrate.

Illustratively, in some embodiments, the line widths of the fifth portion 905 and the seventh portion 1107 can be controlled to be about 12.3 microns, and the line widths of the sixth portion 906 and the eighth portion 1108 can be controlled to be about 6.5 microns. In some embodiments, in order to further reduce the overlapping area with the transverse traces, the line width of the area overlapping with the transverse traces may be further reduced, for example, adjusted to about 5.5 micrometers, which can further reduce signal interference that may be generated between these traces and other traces.

Obviously, the line width is only an exemplary setting manner in one embodiment, and the specific size and relative width size of the line width can be set according to the requirement, and are not further limited and described herein.

As shown in fig. 11, in some embodiments, the display substrate further includes a plurality of Data lines Data extending in the column direction Y, at least two Data lines Data are included between two adjacent second scan lines V Gate, and the Data lines Data include a first segment Data1 extending in the column direction Y, a second segment Data2 extending in the column direction Y, and a bent segment Data3 connecting the first segment Data1 and the second segment Data 2.

In the row direction X, the first segment Data1 corresponds to the seventh part 1107 of the adjacent Data line Data, the second segment Data2 corresponds to the eighth part 1108 of the adjacent Data line Data, and the distance between the first segment Data1 and the seventh part 1107 is equal to the distance between the second segment Data2 and the eighth part 1108.

In this embodiment, the routing manner of the Data lines Data is also adjusted, so that the intervals between the Data lines Data and the second scanning lines V Gate are kept relatively consistent.

Referring to fig. 11, it can be understood that the overall extending direction of the Data lines Data is along the column direction Y, but the Data lines Data do not extend along a straight line, but have a certain bend, in the area where the line width of the second scan line vgate varies, the Data line Data is provided with a bending section Data3, so that the Data line Data extends in a direction away from the second scan line vgate, in a region where the line width of the second Data line Data is constant, the Data line Data extends in a direction substantially parallel to the second Data line Data, and thus, in the area where the second Data line Data has different line width, the spacing between the Data line Data and the second scanning line V Gate is kept basically consistent, therefore, the consistency of the parasitic capacitance between the second scanning line V Gate and the Data line Data in different areas is improved, and the interference of the second scanning line V Gate on the Data signal is reduced.

With reference to fig. 11, in some embodiments, the two Data lines Data adjacent to each second scan line vgate are symmetrically disposed about the second scan line vgate, which is helpful to further improve the consistency of the parasitic capacitance between the second scan line vgate and the Data lines Data in different areas, and is helpful to reduce the interference of the second scan line vgate on the Data signal.

In some embodiments, the first scan line hgate and the second scan line vgate are connected at a connection point CP through a Via, the Via penetrates through the insulating layer GI between the first scan line hgate and the second scan line vgate in a direction perpendicular to the substrate. It will be appreciated that the location of the Via and the location of the connection point CP coincide.

In some embodiments, in a cross section along the row direction X and perpendicular to the substrate in a region corresponding to the Via, a slope angle of the insulating layer is smaller than a slope angle of the first scan line hgate, and a width of the second scan line vgate is larger than a width of the first scan line hgate.

Exemplarily, as shown in fig. 12 to 13, fig. 12 is a schematic cross-sectional view showing a connection point of a substrate, and it should be understood that dimensions, angles, and the like in fig. 12 do not represent actual size relationships of the respective structures, and fig. 12 is only used for explaining positional relationships of the respective structures.

As shown in fig. 13, fig. 13 is a cross-sectional view of the CP position along a-a' of fig. 9, the second scan line vgate and the first scan line hgate are connected by a Via penetrating through the insulating layer GI, in one embodiment, a line width of the second scan line vgate is 12 micrometers, a line width of the first scan line hgate is 7 micrometers, a slope angle a of the first scan line hgate is 43 degrees, a slope angle c of the second scan line vgate is 35 degrees, a width of the Via is about 5 micrometers, and a slope angle b of the insulating layer GI is about 30 degrees. Of course, the common electrode line of the same layer as the second scan line vgate and the first scan line hgate may also adopt such a via/CP connection manner.

Here, the slope angle refers to an angle between a surface of a side away from the substrate and the substrate, and may be understood as an angle between an upper surface of each structure shown in fig. 12 and a horizontal direction.

In this embodiment, the slope angle b of the insulating layer is smaller than the slope angle a of the first scan line hgate and the slope angle c of the second scan line vgate, and meanwhile, the slope angle a of the first scan line hgate is smaller than the slope angle c of the second scan line vgate, so that the possibility of the first scan line hgate or the second scan line vgate peeling off from the insulating layer GI can be reduced.

The width of the second scanning line V Gate is larger than that of the first scanning line H Gate, the line width difference is about 4.07 micrometers, the line width difference between the second scanning line V Gate and the first scanning line H Gate is larger than that of the pixel region, about 5 micrometers is formed, the second scanning line V Gate can completely cover the first scanning line H Gate, and the electric connection effect is guaranteed.

As shown in fig. 12, in some embodiments, the insulating layer GI includes a first sub-layer GI1 and a second sub-layer GI2 stacked in a substrate-away direction, and a thickness ratio of the first sub-layer GI1 to the second sub-layer GI2 is 2.1 to 4.7. The purpose of providing the insulating layer GI as two stacked sub-layers is to increase the thickness of the insulating layer GI by two processes, and as can be seen from the capacitance formula, the larger the distance between the plates of the capacitor is, the smaller the capacitor is, therefore, increasing the thickness of the insulating layer GI can reduce the capacitance generated between the first scan line hgate and the second scan line vgate, which is helpful for improving the interface characteristics of the thin film transistor, and at the same time, is also helpful for reducing the possibility that the subsequent etching step damages the first scan line hgate.

As shown in fig. 14, in some embodiments, the second scan line vgate is located between the red sub-pixel R and the blue sub-pixel B in an adjacent column, and a distance between the second scan line vgate and the red sub-pixel R is greater than a distance between the second scan line vgate and the blue sub-pixel B.

It is understood that the Via is more biased toward the blue sub-pixel B at the boundary of the red sub-pixel R and the blue sub-pixel B, and for example, in one embodiment, the Via is located at a position between the red sub-pixel R and the blue sub-pixel B and biased toward the blue sub-pixel B by about 1.5 micrometers. It is understood that the positions of the Via and the connection point CP coincide, that is, the position of the connection point CP is biased toward the blue subpixel B.

As shown in fig. 14, in some embodiments, a portion of the Via overlaps a region corresponding to the red sub-pixel R, and a portion of the Via overlaps a region corresponding to the blue sub-pixel B, which helps to reduce the possibility of light leakage, thereby helping to improve the display effect.

As shown in fig. 14, in some embodiments, the distance between the Via and the color filter of the red sub-pixel R is smaller than the distance between the Via and the color filter of the blue sub-pixel B, so that the Via can avoid the spacer PS near the driving circuit region of the blue sub-pixel B.

The circles at the pixel electrodes of the red and blue sub-pixels R and B in fig. 14 represent the connection points of the second common electrode lines COM2 with the pixel electrodes.

In some embodiments, the display substrate includes a plurality of spacers PS. It should be understood that the Via holes Via are not distributed in a straight line along the column direction Y, and therefore, the relative positions of other positions are low, if the periodic spacers PS are provided, the periodic spacers PS may not be effectively abutted against the display substrate and form a supporting effect, and therefore, the design of avoiding the positions of the spacers PS and the Via holes Via is controlled in the present embodiment. Specifically, the distance between the orthographic projection of the spacer PS on the substrate and the orthographic projection of the connecting point CP on the substrate is controlled to be not less than 1.2 times of the maximum width of the orthographic projection of the spacer PS on the substrate, so that the spacer PS can have a high supporting effect, and the reliability of the display substrate is improved.

As shown in fig. 15, in some embodiments, the display substrate includes a plurality of sets of spacers PS arranged in an array, each set of spacers includes a main spacer M and a plurality of sub spacers S, wherein the size of the main spacer M is larger than that of the sub spacers S.

Illustratively, as shown in fig. 15, in one embodiment, a spacer cycle includes a primary spacer M and 48 secondary spacers S, the primary spacer M having a size of about 23 microns by 24 microns and the secondary spacer S having a size of about 20 microns by 19 microns.

In the embodiment, the orthographic projection of the control connection points CP on the substrate is separated from the orthographic projection of the main spacer M on the substrate, and the orthographic projection of each connection point CP on the substrate is overlapped with the orthographic projection of at most one auxiliary spacer S on the substrate. In one cycle, due to size and distribution position limitations, each connection point CP is controlled to be separated from the main spacer M in the present embodiment, and the overlap between the connection point CP and the sub spacer S is minimized.

As shown in fig. 15, the dotted line frame may be understood as a spacer period, and the actual size of the spacer period corresponds to six rows of the first scan lines hgate, and accordingly, the number and the ratio of the connection points CP in the spacer period may be controlled. For example: in one spacer period, the number of the connection points CP is more than or equal to 2 and less than or equal to 6; for example: the number of connection points CP is 4. Or the number ratio of the connecting points CP to the auxiliary shock insulators S is R1, and R1 is 1/20-1/8. Or the number ratio of the main shock insulator M to the connecting points CP is R2, and R1 is 1/6-1/4. Therefore, the overlapping probability of the spacers PS and the connection points CP can be reduced, the supporting effect of the spacers PS can be improved, and the reliability of the display substrate can be improved. Here, overlapping means that there is an overlap in their orthographic projections on the substrate.

It should be understood that the embodiments and features of the embodiments may be combined with each other in the present application without conflict. Moreover, the technical solutions of the embodiments of the present application can be applied to different types of display substrates.

Illustratively, as shown in fig. 16, in an embodiment, the technical solution of the embodiment of the present application is applied to a display substrate of a dual Gate structure, where the display substrate of the dual Gate structure refers to two adjacent Gate lines extending along a row direction X and arranged along a column direction Y, two rows of pixels are disposed, that is, two rows of pixels are disposed between a first scan line H Gate k-1 of a k-1 th row and a first scan line H Gate k of a k-th row, and the two rows of pixels specifically include a first row of pixels where a sub-pixel P1 is located and a second row of pixels where the sub-pixel P2 is located.

In other embodiments, the technical solution of the embodiment of the present application may also be applied to different types of display substrates such as an ADS (Advanced Super Dimension Switch), an IPS (In-Plane Switching) display panel, and a VA (vertical alignment) display panel, and can achieve the same or similar technical effects.

For example: as shown in fig. 17, the technical solution of the embodiment of the present application is also applied to an ADS display substrate, where the common electrode and the pixel electrode are not in the same layer; optionally, the common electrode and/or the pixel electrode are slit-shaped.

For example, in fig. 17, in one sub-pixel 1101, the first scanning line H Gate and the second scanning line VGate are connected by CP, the source of the transistor is connected to the data line data, the drain of the transistor is connected to a pixel electrode pixel, which is a different layer from the common electrode COM1, the pixel is plate-shaped, and the common electrode COM1 is slit-shaped, and can cover a plurality of sub-pixels 1101; common electrodes COM1 are overlapped between adjacent data to play a role in shielding; the common electrode COM2 is connected to a common electrode line COM 2.

Of course, the pixel electrode may be slit-shaped and the common electrode may be plate-shaped. The pixel electrode may be located on a side of the common electrode away from or close to the array substrate.

The technical solution of the embodiment of the present application can also be applied to IPS, as shown in fig. 18, in which the common electrode and the pixel electrode are in the same layer. Optionally, the common electrode and the pixel electrode are slit-shaped.

Alternatively, for example, as shown in fig. 18, in one sub-pixel, the first scan line H Gate and the second scan line VGate are connected through CP, the source of the transistor is connected to the data line data, the drain of the transistor is connected to the pixel electrode pixel, the pixel electrode pixel is on the same layer as the common electrode COM1, and a common electrode branch COM12 is arranged between adjacent data to play a role of shielding. The common electrode branch COM12 is on the same layer as the common electrode COM1, and the common electrode branch COM12 is connected to the common electrode line COM2 through a via CP 2.

The invention also provides electronic equipment comprising any one of the display substrates.

Alternatively, the electronic device may be a liquid crystal display LCD or an organic light emitting display OLED, or the like.

Since the display device of this embodiment includes the technical solution of at least one of the above display substrates, at least the corresponding technical effects can be achieved, and details are not repeated herein.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A display substrate, comprising a substrate and, located on the substrate:

a plurality of second scanning lines arranged in sequence in the row direction;

in at least one display sub-area, the distance from the connecting point of at least part of the first scanning line and the second scanning line to the diagonal line of the display sub-area is H, and the range of H is 0 to H;

2. The display substrate of claim 1, wherein H = M2 × sin (arctan (L1/M1)), L1 is a length of the display sub-region in the column direction, M1 is a width of the display sub-region in the row direction, and M2 is a sum of widths of 3-5 columns of pixels in the row direction.

3. The display substrate according to claim 1 or 2, wherein a distance H from a connecting point of at least a part of the first scanning lines and the second scanning lines to a diagonal line of the display sub-region is in a range of H/6 or more and H/2 or less.

4. A display substrate according to claim 1, wherein the sine of the angle between the diagonal and the row direction is K, the value of K being from 1.6 to 3.5.

5. A display substrate according to claim 1, wherein the sine of the angle between the diagonal and the row direction is K, the value of K being from 1.7 to 2.4.

6. A display substrate according to claim 4 or 5, wherein at least one of the display sub-areas comprises a local position, the slope K2 of the line around which the connection point of the local position undulates;

the absolute value of the difference K-K2 is in the range of 0.05-0.2.

7. The display substrate of any one of claims 4 to 6, wherein the display substrate comprises display sub-regions having the same size, and wherein diagonals of the display sub-regions are parallel to each other.

8. A display substrate according to any one of claims 4 to 6, wherein the number of display sub-regions is from 4 to 6.

9. The display substrate according to claim 1, wherein at least a part of the second scanning lines comprise a first portion and a second portion insulated from each other, wherein the first portion is electrically connected to a corresponding gate driving circuit, and the second portion is located on a side of the connection point away from the gate driving circuit.

10. The display substrate of claim 9, wherein at least two adjacent second scan lines have different lengths of the second portions, and the difference between the lengths of the second portions of the two adjacent second scan lines is between 1 and 9 sub-pixels.

11. The display substrate of claim 10, wherein the length difference of the second portion of two adjacent second scan lines is 110-180 um; or 120-.

12. The display substrate according to claim 11, wherein the sum of the lengths of the first portions and the lengths of the second portions of at least two of the second scan lines in the column direction are equal to each other.

13. The display substrate according to any one of claims 9 to 12, wherein the second portion of the second scan line is configured to serve as a first common electrode line, and the first common electrode line is electrically connected to a common signal source.

14. The display substrate according to claim 1, wherein the display substrate comprises a second common electrode line extending along the row direction, the second common electrode line comprises a third portion and a fourth portion separated from each other, and a spacer is formed between the third portion and the fourth portion of the same second common electrode line;

15. The display substrate according to claim 1, wherein the distribution position of the connection points with respect to the diagonal line in the row direction changes periodically.

16. The display substrate according to claim 15, wherein a period of change in the distribution positions of the connection points is equal to a clock period of a gate driver circuit or equal to one-half of the clock period of the gate driver circuit.

17. The display substrate of claim 1, 13 or 14, wherein the plurality of connection points corresponding to at least one of the gate driving circuits are symmetrically distributed about the diagonal line.

18. The display substrate according to claim 15, wherein in a case where J is an even number, a connection point corresponding to a jth gate driver sub-circuit in the gate driver circuits cascaded in Q columns overlaps with the diagonal line;

wherein J is an integer, and Q is not less than J not less than 1.

19. The display substrate according to claim 15, wherein in a case where J is an even number, a connection point corresponding to a jth gate driver sub-circuit in the gate driver circuits cascaded in Q columns is separated from the diagonal line;

wherein J is an integer, and Q is not less than J not less than 1.

20. The display substrate of claim 15, wherein each of the gate driving circuits comprises 6 columns of cascaded gate driving sub-circuits, wherein the connecting points corresponding to the 1 st and 6 th gate driving sub-circuits overlap the diagonal line, the connecting points corresponding to the 2 nd and 3 rd gate driving sub-circuits are separated from and symmetrically distributed about the diagonal line, and the connecting points corresponding to the 4 th and 5 th gate driving sub-circuits are separated from and symmetrically distributed about the diagonal line.

21. The display substrate of claim 15, wherein each of the gate driving circuits comprises 7 columns of cascaded gate driving sub-circuits, wherein connection points corresponding to the 3 rd, 4 th and 5 th gate driving sub-circuits overlap the diagonal line, connection points corresponding to the 1 st and 2 nd gate driving sub-circuits are separated from and symmetrically distributed about the diagonal line, and connection points corresponding to the 6 th and 7 th gate driving sub-circuits are separated from and symmetrically distributed about the diagonal line.

22. The display substrate according to claim 1, further comprising a third electrode line extending in the column direction, the third electrode line being used as one or more of a dummy electrode line and a first common electrode line, the third electrode line being formed by a single patterning process with respect to the first scan line, and the third electrode line being insulated from both the first scan line and the second scan line.

23. The display substrate according to claim 20, wherein each of the gate driving circuits comprises a plurality of gate driving sub-circuits, the gate driving sub-circuits comprise equal number of gate driving sub-circuits, each of the gate driving circuits corresponds to a plurality of second electrode lines and at least one third electrode line, the number of the second electrode lines corresponding to each of the gate driving circuits is equal, and the number of the third electrode lines corresponding to each of the gate driving circuits is equal.

24. The display substrate according to claim 1, wherein the display substrate comprises a plurality of pixels, each pixel comprises a plurality of sub-pixels arranged along the row direction, the area corresponding to each sub-pixel comprises a color resistance area and a driving circuit area arranged along the column direction, and the first common electrode line comprises fifth portions and sixth portions alternately arranged along the column direction;

25. The display substrate according to claim 1 or 22, wherein the second scanning line comprises a seventh portion and an eighth portion alternately arranged along the column direction, wherein the seventh portion is located between color-resist regions of two sub-pixels adjacent to each other along the row direction, and the eighth portion is located between two adjacent seventh portions;

26. The display substrate according to claim 25, wherein the display substrate further comprises a plurality of data lines extending along the column direction, at least two data lines are included between two adjacent second scanning lines, and each data line comprises a first segment extending along the column direction, a second segment extending along the column direction, and a bending segment connecting the first segment and the second segment;

27. The display substrate according to claim 26, wherein two data lines adjacent to each of the second scan lines are symmetrically disposed about the second scan line.

28. The display substrate according to claim 1, wherein the first scanning line and the second scanning line are connected at the connection point by a via hole, and the via hole penetrates an insulating layer between the first scanning line and the second scanning line in a direction perpendicular to the substrate.

29. The display substrate according to claim 28, wherein in a region corresponding to the via hole, in a cross section in the row direction and perpendicular to the substrate, a slope angle of the insulating layer is smaller than a slope angle of the first scan line, and a width of the second scan line is larger than a width of the first scan line.

30. The display substrate of claim 28, wherein the insulating layer comprises a first sub-layer and a second sub-layer stacked in a direction away from the substrate, and a thickness ratio of the first sub-layer to the second sub-layer is 2.1 to 4.7.

31. The display substrate according to claim 1 or 28, wherein each pixel of the display substrate comprises a plurality of sub-pixels arranged along the row direction, and each pixel comprises at least a red sub-pixel, a blue sub-pixel and a green sub-pixel;

32. The display substrate according to claim 31, wherein when the first scanning line and the second scanning line are connected at the connection point via a via, a portion of the via overlaps with a region corresponding to the red sub-pixel, and a portion of the via overlaps with a region corresponding to the blue sub-pixel.

33. The display substrate of claim 32, wherein a distance between the via hole and the color filter of the red sub-pixel is smaller than a distance between the via hole and the color filter of the blue sub-pixel.

34. The display substrate according to claim 1, wherein the display substrate comprises a plurality of spacers, and a distance between an orthographic projection of the spacers on the substrate and an orthographic projection of the connection points on the substrate is not less than 1.2 times a maximum width of the orthographic projection of the spacers on the substrate.

35. The display substrate according to claim 1, wherein the display substrate comprises a plurality of groups of spacers arranged in an array, each group of spacers comprising a main spacer and a plurality of sub spacers, wherein the size of the main spacer is larger than that of the sub spacers;

36. The display substrate according to claim 1, further comprising a plurality of main spacers and a plurality of sub spacers, wherein the number of connection points of the first scan line and the second scan line is greater than or equal to 2 and less than or equal to 6 in one spacer period.

37. The display substrate according to claim 1, further comprising a plurality of main spacers and a plurality of sub spacers, wherein the ratio of the number of the connecting points to the number of the sub spacers in one spacer cycle is R1, and R1 is 1/20 to 1/8.

38. The display substrate according to claim 1, further comprising a plurality of main spacers and a plurality of sub spacers, wherein the ratio of the number of the main spacers to the number of the connection points in one spacer cycle is R2, and R1 is 1/6 to 1/4.

39. The display substrate according to claim 1, wherein two rows of pixels are provided between the first scanning line corresponding to the k-1 th row and the first scanning line corresponding to the k-th row, and k is an integer of 2 or more.

40. The display substrate of claim 1, wherein: the liquid crystal display further comprises a common electrode and a pixel electrode, wherein the common electrode and/or the pixel electrode are in a slit shape.

41. The display substrate of claim 2, wherein H is in the range of 800 to 1800 microns; or 1200 and 1500 microns.

42. The display substrate according to claim 3, wherein h of a connection point of at least a part of the first scanning line and the second scanning line ranges from 180 to 500 μm.

43. An electronic device comprising the display substrate according to any one of claims 1 to 42.