CN110531557B - Array substrate, liquid crystal display panel and display device - Google Patents

Array substrate, liquid crystal display panel and display device Download PDF

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Publication number
CN110531557B
CN110531557B CN201910820617.0A CN201910820617A CN110531557B CN 110531557 B CN110531557 B CN 110531557B CN 201910820617 A CN201910820617 A CN 201910820617A CN 110531557 B CN110531557 B CN 110531557B
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sub
pixels
same
array substrate
pixel
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CN110531557A (en
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傅炯樑
简守甫
孙丽娜
秦丹丹
秦锋
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Shanghai AVIC Optoelectronics Co Ltd
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Shanghai AVIC Optoelectronics Co Ltd
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs

Abstract

The invention discloses an array substrate, a liquid crystal display panel and a display device, wherein each sub-pixel comprises two sub-pixels which are arranged along a second direction, and a switch transistor corresponding to each sub-pixel is positioned between the two sub-pixels and is connected with the two sub-pixels; each sub-pixel corresponds to two grid lines, the two grid lines are both positioned between the two sub-pixels in the sub-pixel, and the sub-pixel is connected with one of the two corresponding grid lines. The switching transistor and the two gate lines corresponding to each row of sub-pixels are located between two rows of sub-pixels, and for the black matrix, the black matrix is arranged between the two rows of sub-pixels in an equal width mode to cover the switching transistor corresponding to each sub-pixel and the two corresponding gate lines, so that the black matrix extending along the first direction is arranged in an equal width mode when viewed from the whole array substrate, and therefore pocking marks cannot be caused.

Description

Array substrate, liquid crystal display panel and display device
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a liquid crystal display panel and a display device.
Background
Thin Film Transistor Liquid Crystal Display (TFT-LCD) panels are widely used in mobile products such as mobile phones and tablet computers. At present, in order to improve the vertical stripes of the display, a double-gate design as shown in fig. 1 is adopted, two gate lines Gn ' are arranged between two adjacent rows of sub-pixels Pix ', transistors 01 ' of four adjacent sub-pixels Pix ' are arranged adjacently, a black matrix for shielding the transistors 01 ' is wide, and a pocky feeling is generated visually when the display is performed. Although the width difference of the black matrix can be reduced by widening the width of the narrow black matrix, the aperture ratio of the sub-pixel Pix' is greatly influenced, and the aperture ratio is lost by more than 10%, thereby reducing the transmittance of the display panel.
Disclosure of Invention
In view of the above, embodiments of the present invention provide an array substrate, a liquid crystal display panel and a display device to solve the problem of the pockmarks in the prior art.
The array substrate provided by the embodiment of the invention comprises a substrate, a plurality of sub-pixels arranged on the substrate in a matrix manner, switch transistors connected with the sub-pixels in a one-to-one correspondence manner, a plurality of grid lines extending along a first direction, and a plurality of data lines extending along a second direction, wherein the first direction and the second direction are arranged in a crossed manner; wherein:
each sub-pixel comprises two sub-pixels arranged along a second direction, and a switch transistor corresponding to each sub-pixel is positioned between the two sub-pixels and is connected with the two sub-pixels;
one side of each column of sub-pixels is provided with one data line, and each column of sub-pixels is respectively connected with the same data line positioned on one side of the sub-pixels through a corresponding switch transistor;
each sub-pixel corresponds to two grid lines, the two grid lines corresponding to the sub-pixel are both positioned between the two sub-pixels in the sub-pixel, and the sub-pixel is connected with one of the two corresponding grid lines through the corresponding switch transistor;
every two adjacent columns of sub-pixels along the first direction are taken as a unit group, the sub-pixels in the same row in the same unit group are respectively connected with the same grid line, and the sub-pixels in the same row in the two adjacent unit groups are respectively connected with different grid lines.
Optionally, in the array substrate provided in the embodiment of the present invention, in the same sub-pixel, the domain directions of the two sub-pixels are different.
Optionally, in the array substrate provided in the embodiment of the present invention, for a same column of sub-pixels along the second direction, in any two adjacent sub-pixels, one of the sub-pixels is connected to a gate line in an odd-numbered row, and the other sub-pixel is connected to a gate line in an even-numbered row.
Optionally, in the array substrate provided in the embodiment of the present invention, the array substrate further includes a plurality of connection traces, each of the connection traces connects two different data lines, and one of the data lines is connected to only one of the connection traces;
the polarities of the sub-pixels in the same row in the same frame are the same, the polarities of the sub-pixels in two adjacent rows are different, the polarities of the sub-pixels in two rows corresponding to the two data lines connected with the same connecting routing are the same, and the connected grid lines are different.
Optionally, in the array substrate provided in the embodiment of the present invention, the two data lines connected to the same connecting trace are respectively an nth data line and an n +2 th data line.
Optionally, in the array substrate provided in the embodiment of the present invention, the sub-pixels in the same column have the same color;
and the two columns of sub-pixels corresponding to the two data lines connected with the same connecting wiring have the same color.
Optionally, in the array substrate provided in the embodiment of the present invention, along the first direction, the sub-pixels are repeatedly arranged according to the arrangement rule of R, G and B;
the nth data line and the (n + 6) th data line are connected with the same connecting wiring.
Optionally, in the array substrate provided in the embodiment of the present invention, along the first direction, the sub-pixels are repeatedly arranged according to an arrangement rule of R, G, B and W;
the nth data line and the (n + 8) th data line are connected with the same connecting wiring.
Correspondingly, the embodiment of the invention also provides a liquid crystal display panel which comprises any one of the array substrates provided by the embodiment of the invention.
Correspondingly, the embodiment of the invention also provides a display device which comprises the liquid crystal display panel provided by the embodiment of the invention.
The invention has the following beneficial effects:
according to the array substrate, the liquid crystal display panel and the display device provided by the embodiment of the invention, each sub-pixel comprises two sub-pixels which are arranged along the second direction, and the switch transistor corresponding to each sub-pixel is positioned between the two sub-pixels and is connected with both the two sub-pixels; each sub-pixel corresponds to two grid lines, the two grid lines are both positioned between the two sub-pixels in the sub-pixel, and the sub-pixel is connected with one of the two corresponding grid lines. The switching transistor and the two gate lines corresponding to each row of sub-pixels are located between two rows of sub-pixels, and for the black matrix, the black matrix is arranged between the two rows of sub-pixels in an equal width mode to cover the switching transistor corresponding to each sub-pixel and the two corresponding gate lines, so that the black matrix extending along the first direction is arranged in an equal width mode when viewed from the whole array substrate, and therefore pocking marks cannot be caused. And the grid line correspondingly connected with each switching transistor is positioned between two sub-pixels in each sub-pixel, so that in one sub-pixel, the difference of the capacitance Cpg between the pixel electrode and the grid line caused by the process alignment can be self-compensated by using the two sub-pixels.
Drawings
FIG. 1 is a schematic structural diagram of a conventional dual-gate display panel;
fig. 2 is a schematic structural diagram of an array substrate according to an embodiment of the invention;
fig. 3 is a schematic structural diagram of an array substrate according to another embodiment of the invention;
fig. 4 is a schematic structural diagram of an array substrate according to another embodiment of the present invention;
fig. 5 is a schematic structural diagram of an array substrate according to another embodiment of the present invention;
fig. 6 is a schematic structural diagram of an array substrate according to yet another embodiment of the present invention;
fig. 7 is a schematic structural diagram of an array substrate according to yet another embodiment of the present invention;
FIG. 8 is a schematic structural diagram of a conventional subpixel with a dual-domain structure;
fig. 9 is a schematic structural diagram of an array substrate according to yet another embodiment of the present invention;
fig. 10 is a schematic structural diagram of a liquid crystal display panel according to an embodiment of the invention;
fig. 11 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, the present invention is further described with reference to the accompanying drawings and examples. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their repetitive description will be omitted. The words expressing the position and direction described in the present invention are illustrated in the accompanying drawings, but may be changed as required and still be within the scope of the present invention. The drawings of the present invention are for illustrative purposes only and do not represent true scale.
It should be noted that in the following description, specific details are set forth in order to provide a thorough understanding of the present invention. The invention can be implemented in a number of ways different from those described herein and similar generalizations can be made by those skilled in the art without departing from the spirit of the invention. Therefore, the present invention is not limited to the specific embodiments disclosed below. The description which follows is a preferred embodiment of the present application, but is made for the purpose of illustrating the general principles of the application and not for the purpose of limiting the scope of the application. The protection scope of the present application shall be subject to the definitions of the appended claims.
The array substrate, the liquid crystal display panel and the display device provided by the embodiment of the invention are specifically described below with reference to the accompanying drawings.
An array substrate according to an embodiment of the present invention, as shown in fig. 2, includes a substrate, a plurality of sub-pixels Pix arranged in a matrix on the substrate, switching transistors 01 connected to the sub-pixels Pix in a one-to-one correspondence, a plurality of gate lines Gn (for example, n is 1 to 6 in fig. 2) extending along a first direction X, and a plurality of data lines Dm (for example, m is 1 to 12 in fig. 2) extending along a second direction Y, where the first direction X and the second direction Y are arranged in a crossing manner; wherein:
each subpixel Pix includes two sub-subpixels Pix1 arranged in the second direction Y, and the switching transistor 01 corresponding to each subpixel Pix is located between the two sub-subpixels Pix1 and connected to both the two sub-subpixels Pix 1;
one side of each row of sub-pixels Pix is provided with a data line Dm, and each row of sub-pixels Pix is respectively connected with the same data line Dm on one side through the corresponding switching transistor 01;
each sub-pixel corresponds to two grid lines Gn, the two grid lines Gn corresponding to the sub-pixel are both positioned between two sub-pixels Pix1 in the sub-pixel Pix, and the sub-pixel Pix is connected with one of the two corresponding grid lines Gn through a corresponding switching transistor 01;
every two adjacent columns of sub-pixels Pix along the first direction X are taken as a unit group 100, the sub-pixels Pix in the same row in the same unit group 100 are respectively connected with the same grid line Gn, and the sub-pixels Pix in the same row in the two adjacent unit groups 100 are respectively connected with different grid lines Gn.
In the array substrate provided by the embodiment of the invention, each sub-pixel comprises two sub-pixels arranged along the second direction, and the switch transistor corresponding to each sub-pixel is positioned between the two sub-pixels and is connected with both the two sub-pixels; each sub-pixel corresponds to two grid lines, the two grid lines are both positioned between the two sub-pixels in the sub-pixel, and the sub-pixel is connected with one of the two corresponding grid lines. The switching transistor and the two gate lines corresponding to each row of sub-pixels are located between two rows of sub-pixels, and for the black matrix, the black matrix is arranged between the two rows of sub-pixels in an equal width mode to cover the switching transistor corresponding to each sub-pixel and the two corresponding gate lines, so that the black matrix extending along the first direction is arranged in an equal width mode when viewed from the whole array substrate, and therefore pocking marks cannot be caused. And the grid line correspondingly connected with each switching transistor is positioned between two sub-pixels in each sub-pixel, so that in one sub-pixel, the difference of the capacitance Cpg between the pixel electrode and the grid line caused by the process alignment can be self-compensated by using the two sub-pixels.
It should be noted that, in the array substrate provided in the embodiment of the present invention, the switch transistors in the same row are ideally located in the same row, and in practical applications, a position difference in processes such as alignment is allowed, which is not limited herein.
Optionally, in the array substrate provided in the embodiment of the present invention, the first direction and the second direction may be perpendicular to each other, which is not limited herein.
Further, in the array substrate provided in the embodiment of the present invention, the first direction may be a row direction and the second direction is a column direction, or the first direction is a column direction and the second direction is a row direction, which is not limited herein. In the drawings, the first direction is taken as a row direction, and the second direction is taken as a column direction for illustration.
Optionally, in the array substrate provided in the embodiment of the present invention, as shown in fig. 3, fig. 3 is a schematic structural diagram of an array substrate provided in another embodiment of the present invention; for the same column of sub-pixels Pix along the second direction Y, one of any two adjacent sub-pixels Pix is connected to the odd-numbered row gate line Gn, and the other sub-pixel Pix is connected to the even-numbered row gate line Gn.
When the process alignment is misaligned, for the same column of sub-pixels Pix, because the gate lines connected to the two adjacent sub-pixels Pix are the odd-numbered gate line Gn and the even-numbered gate line Gn, the capacitance Cpg between the pixel electrode and the gate line of the sub-pixel Pix at the odd-numbered position and the capacitance Cpg between the pixel electrode and the gate line of the sub-pixel Pix at the even-numbered position can compensate each other.
Optionally, in the array substrate provided in the embodiment of the present invention, as shown in fig. 4 to 7, fig. 4 is a schematic structural diagram of an array substrate provided in another embodiment of the present invention; fig. 5 is a schematic structural diagram of an array substrate according to another embodiment of the present invention; fig. 6 is a schematic structural diagram of an array substrate according to yet another embodiment of the present invention; fig. 7 is a schematic structural diagram of an array substrate according to yet another embodiment of the present invention; the data line system further comprises a plurality of connecting lines Sk (fig. 4 and 5 schematically illustrate by taking k as 1-6, and fig. 6 and 7 schematically illustrate by taking k as 1-8), wherein each connecting line Sk is connected with two different data lines Dm, and one data line Dm is connected with only one connecting line Sk;
the polarities of the subpixels Pix in the same row in the same frame are the same, the polarities of the subpixels Pix in two adjacent rows are different, the polarities of the subpixels Pix in two rows corresponding to the two data lines connected with the same connecting trace Sk are the same, and the connected gate lines Gn are different. In this way, when data signals are provided to the two data lines Dm connected to the same connection trace Sk, the corresponding sub-pixels Pix can receive the data signals only when the gate line Gn opens the corresponding sub-pixels Pix, so as to ensure that no signal crosstalk occurs between the two columns of sub-pixels Pix corresponding to the two data lines Dm connected to the same connection trace Sk. In addition, two different data lines Dm share one connection trace Sk, so that data output ports of a source driving circuit for providing data signals can be reduced, the source driving circuit is simplified, and production cost is reduced.
Optionally, in the array substrate provided in the embodiment of the present invention, as shown in fig. 4 and fig. 6, two data lines Dm connected to the same connecting trace Sk are an nth data line Dn and an n +2 th data line Dn +2, respectively. I.e. two data lines Dn and Dn +2 connected to the same connection trace Sk are separated by one data line Dn +1, so that the connection trace is as short as possible and the number of overlapping connection traces Sk is reduced as much as possible. Because the number of the overlapped connecting lines Sk is more, the number of the connecting lines arranged side by side is more, the risk of short circuit of the connecting lines Sk is higher, and the width of the side edge of the array substrate is increased, namely the narrow frame design of the display panel is not facilitated. Therefore, according to the array substrate provided by the embodiment of the present invention, the distance between the two data lines Dm connected to the same connecting trace Sk is as short as possible, the number of the connecting traces Sk arranged side by side can be reduced, the risk of short circuit of the connecting traces Sk is reduced, and the width of the side of the array substrate is reduced.
Optionally, in the array substrate provided in the embodiment of the present invention, as shown in fig. 5 and fig. 7, the sub-pixels Pix in the same column have the same color;
the two columns of sub-pixels Pix corresponding to the two data lines Dm connected to the same connecting trace Sk have the same color. Thus, when a pure color picture is displayed, the data signals on the two columns of sub-pixels Pix corresponding to the two data lines Dm connected with the same connecting trace Sk are the same, that is, the data signals received by the same connecting trace Sk are always kept unchanged in one frame of picture, so that the power consumption can be saved.
Optionally, in the array substrate provided in the embodiment of the present invention, as shown in fig. 5, along the first direction X, the sub-pixels Pix are repeatedly arranged according to the arrangement rule of R, G and B;
the nth data line Dn and the (n + 6) th data line Dn +6 are connected with the same connecting line Sk, so that two columns of sub-pixels Pix corresponding to the two data lines Dm connected with the same connecting line Sk are same in color.
Alternatively, in the array substrate provided in the embodiment of the invention, as shown in fig. 7, along the first direction X, the sub-pixels Pix are repeatedly arranged according to the arrangement rule of R, G, B and W;
the nth data line Dn and the (n + 8) th data line Dn +8 are connected with the same connecting trace Sk. Therefore, the two columns of sub-pixels Pix corresponding to the two data lines Dm connected with the same connecting line Sk are same in color.
In specific implementation, in the array substrate provided in the embodiment of the present invention, in order to implement a narrow frame, two rows of sub-pixels may share one data line, so as to reduce the number of data lines on the array substrate.
As is well known, the liquid crystal display panel mainly controls the transmittance of liquid crystal by controlling the rotation of the liquid crystal using an electric field between a pixel electrode and a common electrode. The liquid crystal display panel mainly includes a longitudinal electric field mode and a transverse electric field mode according to an operation mode. The transverse electric field mode liquid crystal display panel has the characteristics of small color cast, high color reduction, high response speed, high contrast, wide viewing angle and the like, and is more and more widely applied in practical application. In a conventional lateral electric field mode liquid crystal display panel, a common electrode is a planar electrode, and a pixel electrode is provided to face the common electrode with an insulating layer interposed therebetween. In order to increase the viewing angle, a dual-domain structure as shown in fig. 8 is usually adopted, i.e. the pixel electrode 11 has two extending directions symmetrically arranged. However, in the two-domain structure, since the liquid crystal molecules are abnormally inverted between two domains, a black matrix is required to shield the liquid crystal molecules, and a part of the aperture ratio is lost.
In the array substrate provided by the embodiment of the invention, since the switching transistor and the gate line are arranged between the two sub-pixels of each sub-pixel, and the black matrix is exactly arranged between the two sub-pixels in each sub-pixel, in view of this, the array substrate provided by the embodiment of the invention can be arranged in a double-domain structure.
Optionally, in the array substrate provided in the embodiment of the present invention, as shown in fig. 9, fig. 9 is a schematic structural diagram of an array substrate provided in another embodiment of the present invention; the domains of the two sub-pixels Pix1 in each sub-pixel Pix are different, that is, the extending directions of the pixel electrodes 11 of the two sub-pixels Pix1 are different, which is equivalent to setting the sub-pixels to be a dual domain structure, so that the light transmittance of the display panel is improved by using the dual domain structure, and compared with a single domain, the viewing angle can be improved, that is, the light transmittance is not reduced in a certain viewing range. In addition, the switching transistor and the grid line are arranged between two adjacent sub-pixels, and the black matrix is arranged between the two adjacent sub-pixels, so that the black matrix can just shield the abnormal area displayed between the two sub-pixels while shielding the switching transistor, and the display dark area generated by the abnormal liquid crystal molecule turnover between the two domains in the double-domain structure does not need to be considered.
Optionally, in the array substrate provided in the embodiment of the present invention, as shown in fig. 10, in the same sub-pixel Pix, two sub-pixels Pix1 are symmetrically disposed. And the domains of the sub-pixels Pix1 located in the same row have the same direction, which is not limited herein.
Of course, in practical implementation, the domains of the two sub-pixels in each sub-pixel may be set to be the same, and are not limited herein.
Based on the same inventive concept, an embodiment of the present invention further provides a liquid crystal display panel, as shown in fig. 10, fig. 10 is a schematic structural diagram of the liquid crystal display panel provided in the embodiment of the present invention; the array substrate 10 includes any one of the array substrates provided by the embodiments of the present invention. Since the principle of solving the problems of the liquid crystal display panel is similar to that of the array substrate, the implementation of the liquid crystal display panel can refer to the implementation of the array substrate, and repeated details are not repeated.
In specific implementation, as shown in fig. 10, a color filter substrate 20 disposed opposite to the array substrate 10 and a liquid crystal layer 30 disposed between the color filter substrate 20 and the array substrate 10 are further disposed in the liquid crystal display panel.
In specific implementation, the color filter substrate is generally provided with a black matrix and a color filter layer, the common electrode may be disposed on the color filter substrate or on the array substrate, and each sub-pixel of the array substrate generally includes a pixel electrode. Specifically, other film layers and structures of the lcd panel can refer to the prior art, and are not described herein.
Based on the same inventive concept, embodiments of the present invention further provide a display device, including any one of the display devices provided in embodiments of the present invention. The display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like shown in fig. 11. The display device can be implemented by referring to the above embodiments of the display panel, and repeated descriptions are omitted.
According to the array substrate, the liquid crystal display panel and the display device provided by the embodiment of the invention, each sub-pixel comprises two sub-pixels which are arranged along the second direction, and the switching transistor corresponding to each sub-pixel is positioned between the two sub-pixels and is connected with both the two sub-pixels; each sub-pixel corresponds to two grid lines, the two grid lines are both positioned between the two sub-pixels in the sub-pixel, and the sub-pixel is connected with one of the two corresponding grid lines. The switching transistor and the two gate lines corresponding to each row of sub-pixels are located between two rows of sub-pixels, and for the black matrix, the black matrix is arranged between the two rows of sub-pixels in an equal width mode to cover the switching transistor corresponding to each sub-pixel and the two corresponding gate lines, so that the black matrix extending along the first direction is arranged in an equal width mode when viewed from the whole array substrate, and therefore pocking marks cannot be caused. And the grid line correspondingly connected with each switching transistor is positioned between two sub-pixels in each sub-pixel, so that in one sub-pixel, the difference of the capacitance Cpg between the pixel electrode and the grid line caused by the process alignment can be self-compensated by using the two sub-pixels.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (10)

1. An array substrate is characterized by comprising a substrate base plate, a plurality of sub-pixels, switching transistors, a plurality of grid lines and a plurality of data lines, wherein the sub-pixels are arranged on the substrate base plate in a matrix mode, the switching transistors are connected with the sub-pixels in a one-to-one correspondence mode, the grid lines extend along a first direction, the data lines extend along a second direction, and the first direction and the second direction are arranged in a crossed mode; wherein:
each sub-pixel comprises two sub-pixels arranged along a second direction, and a switch transistor corresponding to each sub-pixel is positioned between the two sub-pixels and is connected with the two sub-pixels;
one side of each column of sub-pixels is provided with one data line, and each column of sub-pixels is respectively connected with the same data line positioned on one side of the sub-pixels through a corresponding switch transistor;
each sub-pixel corresponds to two grid lines, the two grid lines corresponding to the sub-pixel are both positioned between the two sub-pixels in the sub-pixel, and the sub-pixel is connected with one of the two corresponding grid lines through the corresponding switch transistor;
every two adjacent columns of sub-pixels along the first direction are taken as a unit group, the sub-pixels in the same row in the same unit group are respectively connected with the same grid line, and the sub-pixels in the same row in two adjacent unit groups are respectively connected with different grid lines;
the driving mode of the array substrate is a column inversion driving mode.
2. The array substrate of claim 1, wherein the two sub-pixels have different domain directions in the same sub-pixel.
3. The array substrate of claim 2, wherein for the same column of sub-pixels along the second direction, one of the sub-pixels is connected to the odd-numbered gate lines and the other sub-pixel is connected to the even-numbered gate lines.
4. The array substrate according to any one of claims 1 to 3, further comprising a plurality of connection traces, each of the connection traces connecting two different data lines, and one of the data lines being connected to only one of the connection traces;
the polarities of the sub-pixels in the same row in the same frame are the same, the polarities of the sub-pixels in two adjacent rows are different, the polarities of the sub-pixels in two rows corresponding to the two data lines connected with the same connecting routing are the same, and the connected grid lines are different.
5. The array substrate according to claim 4, wherein the two data lines connected to the same connecting trace are respectively an nth data line and an n +2 th data line.
6. The array substrate of claim 4, wherein the sub-pixels in a same column are the same color;
and the two columns of sub-pixels corresponding to the two data lines connected with the same connecting wiring have the same color.
7. The array substrate of claim 5, wherein along the first direction, the sub-pixels are repeatedly arranged according to an arrangement rule of R, G and B;
the nth data line and the (n + 6) th data line are connected with the same connecting wiring.
8. The array substrate of claim 5, wherein along the first direction, the sub-pixels are repeatedly arranged according to an arrangement rule of R, G, B and W;
the nth data line and the (n + 8) th data line are connected with the same connecting wiring.
9. A liquid crystal display panel comprising the array substrate according to any one of claims 1 to 8.
10. A display device comprising the liquid crystal display panel according to claim 9.
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