CN113724604B

CN113724604B - Display substrate and electronic equipment

Info

Publication number: CN113724604B
Application number: CN202111075268.8A
Authority: CN
Inventors: 先建波; 江亮亮; 周茂秀; 程敏; 李必奇; 乔勇
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Technology Development Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Technology Development Co Ltd
Priority date: 2021-09-14
Filing date: 2021-09-14
Publication date: 2023-08-15
Anticipated expiration: 2041-09-14
Also published as: CN113724604A

Abstract

The invention provides a display substrate and an electronic device. The display substrate comprises a substrate and a display element arranged on the substrate: a plurality of first scanning lines sequentially arranged in a column direction; a plurality of second scanning lines sequentially arranged in a row direction; wherein the plurality of first scanning lines are connected with the grid driving circuit; the display substrate comprises at least three display subareas arranged along the row direction; the first scanning lines are electrically connected with the corresponding second scanning lines, and connection points of the first scanning lines and the second scanning lines are distributed along diagonal lines of the display subareas where the connection points are located. The embodiment can provide uniformity of RC of each display subarea, and helps to improve uniformity of charging rates of pixels located at different positions, so that display effect is improved.

Description

Display substrate and electronic equipment

Technical Field

The present invention relates to the field of display, and in particular, to a display substrate and an electronic device.

Background

With the popularity of the full screen concept for use on medium and small size display products, a very fashionable look is being pursued for large size display products (e.g., televisions). With such a large-sized display device, the in-plane resistance capacitance (abbreviated as RC) has an increased influence on the charging rate due to its large size, and the charging rate uniformity thereof is poor.

Disclosure of Invention

The embodiment of the invention provides a display substrate and electronic equipment, which are used for solving the problem of poor charging rate uniformity of a large-size display substrate.

In a first aspect, an embodiment of the present invention provides a display substrate, including a substrate and a substrate disposed on the substrate:

a plurality of first scanning lines sequentially arranged in a column direction;

a plurality of second scanning lines sequentially arranged in a row direction;

wherein the plurality of first scanning lines are connected with the grid driving circuit;

the display substrate comprises at least three display subareas arranged along the row direction;

the first scanning lines are electrically connected with the corresponding second scanning lines, and connection points of the first scanning lines and the second scanning lines are distributed along diagonal lines of display subareas where the connection points are located;

in at least one display sub-area, there is at least part of the distance H from the connection point of the first scan line and the second scan line to the diagonal of the display sub-area, H being in the range of 0 to H,

where h=m2×sin (arctan (L1/M1)), L1 is the length of the display sub-region in the column direction, M1 is the width of the display sub-region in the row direction, M2 is the sum of the widths of N-1 columns of pixels in the row direction, and the value of N is equal to half the number of clock cycles of the gate driving circuit or the number of clock cycles of the gate driving circuit.

In some embodiments, H ranges from 800 to 1800 microns; or 1200-1500 microns.

In some embodiments, the h range of the connection point of at least part of the first scan line and the second scan line is 180 to 500 micrometers.

In some embodiments, the angle between the diagonal and the row direction has a sine value of K, which is 1.6 to 3.5.

In some embodiments, the angle between the diagonal and the row direction has a sine value of K, which is 1.7 to 2.4.

In some embodiments, the at least one display sub-area comprises a local position, the connection point of which local position is around the slope K2 of the fluctuating straight line.

The absolute value of the difference of K-K2 is in the range of 0.05-0.2.

In some embodiments, the display substrate includes display sub-regions that are all the same size, and the diagonals of the display sub-regions are parallel to each other.

In some embodiments, the number of display sub-regions is 4 to 6.

In some embodiments, at least a portion of the second scan line includes a first portion and a second portion insulated from each other, wherein the first portion is electrically connected to a corresponding gate driving circuit, and the second portion is located on a side of the connection point away from the gate driving circuit.

In some embodiments, there are at least two adjacent second scan lines, the lengths of the second portions of which are unequal, and the lengths of the second portions of the two adjacent second scan lines differ by 1 to 9 sub-pixel lengths.

In some embodiments, the difference in length between the second portions of two adjacent second scan lines is 110-180um; or 120-170um.

In some embodiments, the sum of the length of the first portion and the length of the second portion of each of the second scan lines is equal along the column direction.

In some embodiments, the second portion of the second scan line is configured to serve as a first common electrode line, the first common electrode line being electrically connected to a common signal source.

In some embodiments, the display substrate includes a second common electrode line extending in the row direction, the second common electrode line including a third portion and a fourth portion separated from each other, a spacer being formed between the third portion and the fourth portion of the same second common electrode line;

the third and fourth portions of the second common electrode line have a first orthographic projection on the substrate, the spacer of the second common electrode line has a second orthographic projection on the substrate, and the first portion of the second scan line has a third orthographic projection on the substrate;

The first orthographic projection and the third orthographic projection corresponding to the same pixel are separated, and the second orthographic projection and the third orthographic projection corresponding to the same pixel are overlapped.

In some embodiments, the location of the connection points relative to the diagonal varies periodically along the row direction.

In some embodiments, the period of variation in the distribution position of the connection points is equal to the clock period of the gate driving circuit or equal to one half of the clock period of the gate driving circuit.

In some embodiments, the plurality of connection points corresponding to at least one of the gate driving circuits are symmetrically distributed about the diagonal line.

In some embodiments, where J is even, the connection point corresponding to the J-th gate drive sub-circuit in the gate drive circuit cascaded with Q columns overlaps the diagonal;

in the case where J is an odd number, a connection point corresponding to a J-th gate driving sub-circuit in the gate driving circuits cascaded with Q columns is separated from the diagonal line;

wherein J is an integer, and Q is more than or equal to J is more than or equal to 1.

In some embodiments, where J is even, the connection point corresponding to the J-th gate drive sub-circuit in the gate drive circuit cascaded with Q columns is separated from the diagonal;

In the case where J is an odd number, a connection point corresponding to a J-th gate driving sub-circuit in the gate driving circuits cascaded with Q columns overlaps the diagonal line;

In some embodiments, each of the gate driving circuits includes 6 columns of cascaded gate driving sub-circuits, wherein connection points corresponding to the 1 st and 6 th gate driving sub-circuits overlap the diagonal, connection points corresponding to the 2 nd and 3 rd gate driving sub-circuits are separated from the diagonal and symmetrically distributed about the diagonal, and connection points corresponding to the 4 th and 5 th gate driving sub-circuits are separated from the diagonal and symmetrically distributed about the diagonal.

In some embodiments, each of the gate driving circuits includes 7 columns of cascaded gate driving sub-circuits, wherein connection points corresponding to the 3 rd, 4 th and 5 th gate driving sub-circuits overlap the diagonal, connection points corresponding to the 1 st and 2 nd gate driving sub-circuits are separated from the diagonal and symmetrically distributed about the diagonal, and connection points corresponding to the 6 th and 7 th gate driving sub-circuits are separated from the diagonal and symmetrically distributed about the diagonal.

In some embodiments, the display substrate further includes a third electrode line extending along the column direction, the third electrode line being used as one or more of a dummy electrode line and a first common electrode line, the third electrode line being fabricated with the first scan line through a patterning process, the third electrode line being insulated from both the first scan line and the second scan line.

In some embodiments, each of the gate driving circuits includes a plurality of gate driving sub-circuits, the number of gate driving sub-circuits included in each of the gate driving circuits is equal, each of the gate driving circuits corresponds to a plurality of second electrode lines and at least one third electrode line, the number of second electrode lines corresponding to each of the gate driving circuits is equal, and the number of third electrode lines corresponding to each of the gate driving circuits is equal.

In some embodiments, the display substrate includes a plurality of pixels, each pixel including a plurality of sub-pixels arranged in the row direction, each region corresponding to the sub-pixel including a color resist region and a driving circuit region arranged in the column direction, the first common electrode line including fifth and sixth portions alternately arranged in the column direction;

The fifth part is positioned between two adjacent color resistance regions along the row direction, and the sixth part is positioned between two adjacent driving circuit regions along the row direction;

the fifth portion has a size greater than that of the sixth portion in the row direction.

In some embodiments, the second scan line includes seventh portions and eighth portions alternately arranged along the column direction, wherein the seventh portions are located between the color resist regions of two sub-pixels adjacent along the row direction, and the eighth portions are located between the adjacent two seventh portions;

the seventh portion has a size greater than that of the eighth portion in the row direction.

In some embodiments, the display substrate further includes a plurality of data lines extending along the column direction, at least two data lines are included between two adjacent second scan lines, the data lines include a first segment extending along the column direction, a second segment extending along the column direction, and a bending segment connecting the first segment and the second segment;

along the row direction, the first segment corresponds to a seventh portion of an adjacent data line, the second segment corresponds to an eighth portion of an adjacent data line, and a distance between the first segment and the seventh portion is equal to a distance between the second segment and the eighth portion.

In some embodiments, two data lines adjacent to each of the second scan lines are symmetrically disposed about the second scan line.

In some embodiments, the first scan line and the second scan line are connected at the connection point by a via penetrating through an insulating layer between the first scan line and the second scan line in a direction perpendicular to the substrate.

In some embodiments, in a region corresponding to the via hole, in a cross section along the row direction and perpendicular to the substrate, a slope angle of the insulating layer is smaller than a slope angle of the first scan line, and a width of the second scan line is larger than a width of the first scan line.

In some embodiments, the insulating layer includes a first sub-layer and a second sub-layer stacked in a direction away from the substrate, the first sub-layer and the second sub-layer having a thickness ratio of 2.1 to 4.7.

In some embodiments, each pixel of the display substrate includes a plurality of sub-pixels arranged along the row direction, each of the pixels including at least a red sub-pixel, a blue sub-pixel, and a green sub-pixel;

the second scanning line is positioned between an adjacent column of red sub-pixels and blue sub-pixels, and the distance between the second scanning line and the red sub-pixels is larger than the distance between the second scanning line and the blue sub-pixels.

In some embodiments, when the first scan line and the second scan line are connected at the connection point through a via, a portion of the via overlaps a region corresponding to the red subpixel, and a portion of the via overlaps a region corresponding to the blue subpixel.

In some embodiments, a distance between the via and the color filter of the red subpixel is less than a distance between the via and the color filter of the blue subpixel.

In some embodiments, the display substrate includes a plurality of spacers, a distance between an orthographic projection of the spacers on the substrate and an orthographic projection of the connection point on the substrate is not less than 1.2 times a maximum width of the orthographic projection of the spacers on the substrate.

In some embodiments, the display substrate includes a plurality of groups of spacers arranged in an array, each group of spacers including a main spacer and a plurality of auxiliary spacers, wherein the size of the main spacer is larger than the size of the auxiliary spacers;

the orthographic projection of the connection point on the substrate is separated from the orthographic projection of the main spacer on the substrate, and the orthographic projection of each connection point on the substrate overlaps with the orthographic projection of at most one auxiliary spacer on the substrate.

In some embodiments, the method further comprises a plurality of primary spacers and a plurality of secondary spacers, wherein in one spacer cycle, the number of connection points of the first scan line and the second scan line is greater than or equal to 2 and less than or equal to 6.

In some embodiments, the method further comprises a plurality of main spacers and a plurality of auxiliary spacers, wherein in one spacer period, the number ratio of the connection point to the auxiliary spacers is R1, and R1 is 1/20-1/8.

In some embodiments, the method further comprises a plurality of main spacers and a plurality of auxiliary spacers, wherein in one spacer period, the ratio of the number of the main spacers to the number of the connection points is R2, and R1 is 1/6-1/4.

In some embodiments, two rows of pixels are disposed between a first scan line corresponding to a k-1 th row and a first scan line corresponding to a k-1 th row, where k is an integer greater than or equal to 2.

In some embodiments, the pixel electrode is formed by a plurality of electrodes, and the common electrode and/or the pixel electrode are formed by a plurality of electrodes.

In some embodiments, H ranges from 800 to 1800 microns; or 1200-1500 microns.

In a second aspect, an embodiment of the present invention provides an electronic device, including a display substrate as described in any one of the above.

In the technical solution of this embodiment, the first scan line along the column direction and the second scan line along the row direction are provided to transmit the gate driving signal, so that the gate driving unit that provides the gate driving signal may be disposed on the DP side of the display substrate, so as to reduce the width of the frame, and facilitate the realization of a narrow frame. Further, by dividing the display substrate into a plurality of display sub-regions, uniformity of RC of each display sub-region can be provided, which contributes to improving uniformity of charging rate of pixels located at different positions, thereby contributing to improving display effect.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments of the present invention will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic view of a conventional display substrate in the related art;

FIG. 2 is a schematic view of a structure of a V-type display substrate according to the related art;

FIG. 3 is a schematic diagram of a display substrate according to an embodiment of the invention;

FIG. 4 is a schematic view of a structure of a display substrate according to another embodiment of the invention;

FIG. 5 is a schematic view of a structure of a display substrate according to another embodiment of the invention;

FIG. 6 is a schematic diagram of a structure of a display substrate according to another embodiment of the invention;

FIG. 7 is a schematic view of a structure of a display substrate according to another embodiment of the invention;

FIG. 8 is a schematic diagram of a structure of a display substrate according to another embodiment of the invention;

FIG. 9 is a schematic diagram of a structure of a display substrate according to another embodiment of the invention;

FIG. 10 is a schematic view of a structure of a display substrate according to another embodiment of the invention;

FIG. 11 is a schematic view of a structure of a display substrate according to another embodiment of the invention;

FIG. 12 is a schematic view of a structure of a display substrate according to another embodiment of the invention;

FIG. 13 is a schematic view of a structure of a display substrate according to another embodiment of the invention;

FIG. 14 is a schematic view of a structure of a display substrate according to another embodiment of the invention;

FIG. 15 is a schematic view of an arrangement of spacers in accordance with an embodiment of the present invention;

FIG. 16 is a schematic view of a structure of a display substrate according to another embodiment of the invention;

FIG. 17 is a schematic view of a structure of a display substrate according to another embodiment of the invention;

fig. 18 is a schematic structural diagram of a display substrate according to another embodiment of the invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

In the drawings, the size of each component, the thickness of a layer, or a region may be schematically shown for clarity. Accordingly, one aspect of the present disclosure is not necessarily limited to this dimension, and the shapes and sizes of the various components in the drawings do not reflect actual proportions. Further, the drawings schematically show ideal examples, and one mode of the present disclosure is not limited to the shapes or numerical values shown in the drawings, and the like.

At present, as the size of a display substrate increases, the influence of in-plane resistance and capacitance (RC for short) on the charging rate increases, and the charging rate uniformity is poor; this is especially true for full-face screens, where the internal wiring is complex and the RC is more. Specifically, RC that affects in-plane charge rate uniformity mainly includes at least one of: RC (abbreviated as CLK RC) brought by a clock signal line and RC (abbreviated as Gate RC) brought by a scan line; RC (Data RC) brought by Data lines.

As shown in fig. 1, for a conventional large-sized display substrate (i.e., normal panel), its clock signal (CLK signal) is introduced from the DP (the side where the source driver is usually to be disposed is called DP side) side COF (flip chip film) and enters the panel along the column direction Y, i.e.: from the DP side to the DPO side (the side opposite to the DP side in the column direction Y), the effect of CLK RC thereof gradually increases, and the effect on the charging rate appears from the DP side to the DPO side, and the charging rate gradually decreases; and the large-sized display substrate is usually dual-driven, as shown in fig. 1, the Gate driving circuits (which may be simply referred to as GOA circuits when the Gate driving circuits are located on the array substrate) are distributed on opposite sides of the panel in the row direction X (i.e., the left and right sides shown in fig. 1), and the scan signals (Gate signals) in each row are transmitted from the opposite sides of the panel in the row direction X to the center of the panel, i.e.: the start of the Gate signal in each row is located at opposite sides of the panel in the row direction X and the end is located at the center of the panel, so that the charge rate of the Pixel (Pixel) gradually decreases from both sides in the row direction X to the center thereof under the influence of the Gate RC. While for the Data signal (Data signal), it is accessed from the COF terminal on the DP side, and extends to the DPO side, and its Pixel charging rate gradually decreases under the influence of the Data RC.

Based on the foregoing, the (1) position shown in fig. 1 has small CLK RC, large Gate RC, and small Data RC, the (1) position has small comprehensive influence, and the (1) position has an excellent charging rate through simulation test; the (2) position shown in fig. 1 is large in CLK RC, gate RC, data RC, and the (2) position has a large comprehensive influence, and the (2) position has a poor charging rate through simulation test; the (3) position shown in fig. 1 has large CLK RC, small Gate RC and large Data RC, the (3) position has large comprehensive influence, and the (3) position has good charging rate through simulation test, as shown in table 1 below; that is, at the (2) position shown in fig. 1, CLK RC, gate RC, and Data RC are all the most affected, making it the point of the worst charging rate; in-plane design of the Normal panel, RC distribution is extremely uneven, so that the charging rate difference of in-plane pixels is large, the image quality of the panel is seriously affected, and the difference is more obvious due to the poor charging rate of the full-face screen.

As shown in fig. 2, in order to further improve the overall screen, in the related art, an ultra-narrow frame display substrate is proposed, and a GOA circuit is placed on the DP side of the panel, and compared with the Normal panel mentioned above, one more vertical scan line V Gate extending in the column direction Y passes through the pixels of the display area, and is switched through a via structure (typically, the position of the via structure is the connection point a shown in fig. 2) to be connected with a horizontal scan line H Gate extending in the row direction X, so as to realize row driving, and further realize that ultra-narrow frames can be realized on both opposite sides and the DPO side in the row direction X; for this panel, the CLK signal is introduced by COF on opposite sides in the row direction X of the panel and introduced in the plane by GOA circuit on DP side, the GOA scanning direction is scanned from DP side to DPO side, while for the Data signal, the COF terminal on DP side is accessed and extends to DPO side, it should be understood that this Gate signal access mode can be understood as adopting V-shaped line (thin single-dot and dash line as shown in fig. 2) access mode, this ultra-narrow frame display substrate can be defined as V-shaped panel, and it should be noted that V-shaped line refers to line connecting each connection point a in the panel sequentially. As shown in fig. 2, data RC appears to gradually increase from DP side to DPO side, and CLK RC appears to gradually increase from opposite sides in the row direction X toward the center, and V Gate RC appears to gradually increase from the junction toward opposite sides in the row direction X.

Based on the foregoing, the (1) position shown in fig. 2 has small CLK RC, small H Gate RC, large V Gate RC, and small Data RC, the (1) position has small comprehensive influence, and the (1) position has good charging rate through simulation test; the (2) position shown in fig. 1 has large CLK RC, large H Gate RC, small V Gate RC, large Data RC, and large comprehensive influence of the (2) position, and the (2) position has good charging rate through simulation test; the (3) position shown in fig. 1 is large in CLK RC, H Gate RC, V Gate RC, data RC, and the (3) position has a large comprehensive influence, and the (3) position is poor in charging rate by simulation test, as shown in table 1 below; that is, with the V-shaped panel design shown in fig. 2, although the pixel charging rate at the (2) position is improved, the (3) position becomes the point where the RC is most affected, and becomes the point where the charging rate is the worst, which seriously affects the panel image quality, and the phenomena such as Mura (luminance unevenness) and cross talk become more serious.

TABLE 1

In summary, the difference of Pixel charging rates is larger due to the difference of resistance and capacitance of CLK, gate, data and the like in different positions in the plane in the Normal panel and the V-shaped panel, and the difference affects the large-size overall screen more, which seriously affects the image quality of the panel.

The embodiment of the invention provides a display substrate.

As shown in fig. 3, in some embodiments, the display substrate includes a substrate, and a plurality of first scan lines H Gate and second scan lines V Gate disposed on the substrate, where the plurality of first scan lines H Gate are sequentially arranged in a column direction Y and extend along a row direction X, and the plurality of second scan lines V Gate are sequentially arranged in the row direction X and extend along the column direction Y. The first scan line hgate and the corresponding second scan line V Gate are electrically connected at a connection point CP (Connect Point).

As shown in fig. 3, in some of these embodiments, the display substrate includes at least three display sub-regions arranged in the row direction X, each of which has an equal height in the column direction Y, and each extends from the DP side to the DPO side of the display substrate.

With continued reference to fig. 3, in this embodiment, the display area AA of the display substrate includes four display sub-areas AA1 to AA4, and the actual number of the display sub-areas is not limited thereto.

It should be noted that if fewer display sub-regions are provided, the number of gate driving circuits that are required to be correspondingly provided is smaller, contributing to cost reduction, and if more display sub-regions are provided, the driving and control effects on the display substrate are better, and the pixel charging rate difference is lower.

In this embodiment, a gate driving circuit is exemplified as a GOA circuit disposed on an array substrate, and the gate driving circuit includes a plurality of gate driving sub-circuits, and in some exemplary embodiments, the gate driving circuit is embodied as a GOA unit. Of course, the gate driving circuit may be a driving IC (COG) bound to the array substrate or a driving IC (COF) provided on the PCB.

In some embodiments, the display substrate may include display sub-regions having different sizes, and in other embodiments, the display substrate may include display sub-regions having the same size, and the diagonal lines DI of the display sub-regions are parallel to each other, which helps to further improve the uniformity of the display substrate.

In some of these embodiments, the number of display sub-areas is 3 to 6, helping to balance control effects and costs.

It should be understood that the state shown in fig. 3 does not represent the actual number and the actual positional relationship of the first scan line H Gate, the second scan line V Gate, and the connection point CP of the display substrate, and only a portion of the first scan line H Gate, the second scan line V Gate, and the corresponding connection point CP are exemplarily shown in fig. 3 for ease of understanding and better illustration in this embodiment, and a portion of the first scan line H Gate, the second scan line V Gate, and the connection point CP are omitted in fig. 3.

As shown in fig. 3, the connection point CP of the first scan line H Gate and the second scan line V Gate is arranged along the diagonal line DI of the display sub-area where the connection point CP is located.

In some of these embodiments, each connection point CP overlaps a diagonal DI; in other embodiments, the location of each connection point CP may be offset from the diagonal DI of the display sub-area in which it is located, and it is understood that each connection point CP is located near the diagonal DI, and each connection point CP is distributed along the diagonal DI, but some connection points CP do not coincide with the diagonal DI.

In the technical solution of this embodiment, the Gate driving signal is transmitted by setting the first scanning line H Gate along the column direction Y and the second scanning line V Gate along the row direction X, so that the GOA unit for providing the Gate driving signal can be set on the DP side of the display substrate, so as to reduce the width of the frame, and facilitate the realization of a narrow frame. Further, by dividing the display substrate into a plurality of display sub-regions, uniformity of RC of each display sub-region can be provided, which contributes to improving uniformity of charging rate of pixels located at different positions, thereby contributing to improving display effect.

As shown in fig. 4, in some of the embodiments, a distance H from a connection point CP of the first scan line H Gate and the second scan line V Gate to a diagonal line DI ranges from 0 to H.

The GOA circuit of each display subarea comprises a plurality of GOA unit groups which are cascaded in multiple stages, each GOA unit group comprises a plurality of GOA units, and the quantity of the GOA units included in each GOA unit group is equal.

Referring to fig. 4, a p-th group of GOA unit groups of the multiple cascade-connected GOA unit groups are shown, a plurality of second scan lines V Gate connected to each GOA unit of the p-th group of GOA unit groups form a p-th column of second scan line groups (V Gtae groups), and a plurality of first scan lines H Gate corresponding to the p-th column of second scan line groups (H Gtae groups) form a corresponding p-th row of first scan line groups. It should be noted that, in this embodiment, in order to facilitate illustrating the connection relationship between the GOA units and the second scan line V Gate, the order of GOA units is not represented by the actual cascade order of GOA units in the GOA unit group, and the cascade order is as shown in fig. 4.

In this embodiment, a clock period (CLK period) of one GOA unit group is taken as 8 for illustration, that is, one GOA unit group includes 8 GOA units, and the GOA unit group corresponds to 8 second scan lines V Gate arranged along the column direction Y and 8 first scan lines H Gate arranged along the row direction X, and each first scan line H Gate is electrically connected to a corresponding second scan line V Gate at a connection point CP.

With continued reference to fig. 4, the position of each connection point CP fluctuates within a certain range of the diagonal DI of the display sub-area. The minimum distance between the connection point CP and the diagonal DI is 0, that is, the positions of some connection points CP may coincide with the diagonal DI, for example, the connection point corresponding to the 3 rd level GOA unit.

The maximum distance between the connection point CP and the diagonal DI is H. H=m2×sin (arctan (L1/M1)). L1 is the length of the display sub-area in the column direction Y, and M1 is the width of the display sub-area in the row direction X, so that L1/M1 corresponds to the sine value k=sin (arctan (L1/M1)) of the angle between the direction of the diagonal DI of the display sub-area and the row direction X, and can be understood as the slope K of the diagonal DI of the display sub-area, that is, the magnitude of the angle between the diagonal DI and the row direction X.

In some of these embodiments, the angle between the diagonal DI and the row direction X has a sine value of 1.6 to 3.5, and correspondingly, arctan (L1/M1) has a value in the range of about 57.9 ° to 74.1 °.

Alternatively, in some preferred embodiments, the angle between the diagonal DI and the row direction X has a sine value of 1.7 to 2.4, and correspondingly, the arctan (L1/M1) has a value in the range of about 59.5 to 67.3.

M2 is the sum of the widths of N-1 columns of pixels in the row direction X, and an exemplary group of GOA cells includes 8 GOA cells, which occupy a width of 7 pixels in the row direction X.

When the display substrate has a constant size, sin (arctan (L1/M1)) is a constant value, and the width of the pixel in the row direction X is also a constant value, for example: l1=800 micrometers, m1=480 micrometers. Therefore, it can be understood that the distance between the connection point CP and the diagonal line DI is controlled by controlling the value of K in the present embodiment.

In this embodiment, the value of K is equal to the number of clock cycles of the GOA unit group or half the number of clock cycles of the GOA unit group. In this embodiment, the connection point CP fluctuates in a local range according to the clock cycle or half of the clock cycle of the GOA unit group, so that the difference of signals output by the GOA units in the same GOA unit group is smaller, which is helpful for improving the display uniformity of the display substrate.

For example, a display substrate, for example, an 8K 4K or 4K 2K panel, has a clock period of 8, K is selected to be equal to 8, the pixel width along the row direction X is about 372 micrometers, sin (arctanL 1/M1) =0.86, and h=7x372 sin (arctanL 1/M1) =2239 micrometers can be calculated according to the above formula, and when implemented, the value of K can be adjusted, for example, K is equal to 4, so as to obtain the corresponding H value.

In some embodiments, h=m2×sin (arctan (L1/M1)), L1 is the length of the display sub-area in the column direction, M1 is the width of the display sub-area in the row direction, and M2 is the sum of the widths of 3-5 columns of pixels in the row direction.

In some embodiments, a distance from a connection point of at least part of the first scan line and the second scan line to a diagonal line of the display sub-area is H, and H ranges from H/6 to H/2.

Alternatively, H may be controlled in the range of 500 to 2500 microns. Alternatively, H ranges from 800 to 1800 microns; or 1200-1500 micrometers, can make the charging rate of the display substrate have higher uniformity.

Optionally, at least part of the connection points of the first scan line and the second scan line have an h range of 180 to 500 micrometers. h ranges from 200 to 400 microns; or 300-380 microns, can make the charging rate of the display substrate have higher uniformity.

It will be appreciated that fig. 4 is a partial position of the sub-area shown in fig. 3, for example: fig. 4 is an AA area in AA4 of fig. 3, and is described by taking the example that the slope K2 of AA area is equal to the slope k=sin (arctan (L1/M1)) of the display sub-area AA4, in other words, the directions of the diagonals DI and K2 of the display sub-area AA4 are parallel to each other.

Alternatively, the slope K2 of the line around the fluctuation of each connection point of the local position of the display sub-area is not exactly equal to the slope k=sin (arctan (L1/M1)) of the display sub-area.

Illustratively, the absolute value of the difference of K-K2 ranges from 0.05 to 0.2, preferably from 0.07 to 0.12.

Illustratively, the maximum fluctuation range H of each connection point of the display subarea from the straight line is smaller than the H value. The absolute value of the difference H-H ranges from 5 to 200 microns, preferably from 10 to 50 microns.

In one embodiment, the distribution position of the connection points CP with respect to the diagonal DI varies periodically in the row direction X. It will be appreciated that the relative positions between each connection point CP and the diagonal DI are periodically, for example, in the row direction X, the m-th connection point CP in the p-th GOA cell group and the m-th connection point CP in the p+1-th GOA cell group are the same.

In one embodiment, the period of variation of the distribution position of the connection point CP is equal to the clock period of the group of GOA units or equal to one half of the clock period of the group of GOA units. By way of example, the clock period of each GOA unit group is 8, and the position distribution period of the connection point CP may be set to 4 or 8. In this way, the difference of the signals output by the GOA units in the same GOA unit group is smaller, which is helpful to improve the charging rate uniformity of the pixels of the display substrate.

In some embodiments, the respective connection points CP of each GOA unit group are symmetrically distributed about a diagonal DI.

As shown in fig. 4, the 1 st stage GOA unit is connected to the 1 st row first scan line H Gate through the 8 th column second scan line V Gate, the 2 nd stage GOA unit is connected to the 4 th row first scan line H Gate through the 4 th column second scan line V Gate, the 3 rd stage GOA unit is connected to the 3 rd row first scan line H Gate through the 3 rd column second scan line V Gate, the 4 th stage GOA unit is connected to the 2 nd row first scan line H Gate through the 22 nd column second scan line V Gate, the 5 th stage GOA unit is connected to the 5 th row first scan line H Gate through the 5 th column second scan line V Gate, the 6 th stage GOA unit is connected to the 6 th row first scan line H Gate through the 1 st column second scan line V Gate, the 7 th stage GOA unit is connected to the 7 th row first scan line H Gate through the 7 th column second scan line V Gate, and the 8 th stage GOA unit is connected to the 6 th row first scan line H Gate through the 6 th column second scan line V Gate.

With continued reference to fig. 4, the distances between the GOA units and the GOA unit groups are different, and thus the signal transmission delays are different, for example, the distance between the connection point corresponding to the GOA unit of level 1 and the GOA unit group is the largest, the signal delay is the largest, the distance between the connection point corresponding to the GOA unit of level 8 and the GOA unit group is the smallest, and the signal delay is the smallest. The signal delay between adjacent scan lines is thus balanced by adjusting the GOA cell order and the connection point correspondence order.

As shown in fig. 5, in some of these embodiments, in the case where J is even, the connection point CP corresponding to the J-th GOA cell of the GOA cells of the Q column cascade overlaps with the diagonal line DI, and in the case where J is odd, the connection point CP corresponding to the J-th GOA cell of the GOA cells of the Q column cascade is separated from the diagonal line DI.

Similar to the embodiment shown in fig. 4, in fig. 5, the distance between the connection point corresponding to the GOA unit of level 1 and the GOA unit group is the largest, and accordingly, the signal delay is the largest, and the distance between the connection point corresponding to the GOA unit of level 8 and the GOA unit group is the smallest, and accordingly, the signal delay is the smallest. And the local area takes one connecting point as the center, and the adjacent connecting points on two sides are distributed by taking the diagonal DI as the symmetry axis, so that the signal difference of the local area is reduced, and mura is reduced. For example: the corresponding connection points of the 2 nd and 4 th GOA units are distributed approximately along the diagonal line DI in a symmetrical axis by taking the 3 rd GOA unit as the center.

Similar to the embodiment shown in fig. 5, in other embodiments, the connection point CP corresponding to the J-th GOA cell of the GOA cells of the Q column cascade is separated from the diagonal DI in the case where J is even, and overlaps with the diagonal DI in the case where J is odd. For example, in the local area, 2 connection points are taken as symmetry axes, and adjacent connection points on one side or two sides of the 2 connection points are distributed approximately in the symmetry axes, so that signal difference of the local area is reduced, and mura is reduced. For example: and the connection points corresponding to the 1 st and 6 th GOA units are used as symmetry axes, and the connection points corresponding to the 2 nd to 5 th GOA units are distributed approximately by taking a diagonal line DI as symmetry axes or the symmetry axes as symmetry axes.

In the above embodiment, J is an integer, and Q is greater than or equal to J is greater than or equal to 1, it can be understood that by controlling the position of the connection point CP, the connection point CP can be symmetrically distributed about the diagonal line DI, so that the difference of signals output by each GOA unit is smaller, and the display uniformity of the display substrate is improved.

Illustratively, in one embodiment, each group of GOA units comprises 6 columns of cascaded GOA units, with the understanding that K is equal to 6.

As shown in fig. 6, in which the connection points CP corresponding to the 1 st and 6 th GOA units overlap the diagonal DI, the connection points CP corresponding to the 2 nd and 3 rd GOA units are separated from the diagonal DI and symmetrically distributed about the diagonal DI, and the connection points CP corresponding to the 4 th and 5 th GOA units are separated from the diagonal DI and symmetrically distributed about the diagonal DI.

Illustratively, in yet another embodiment, as shown in fig. 7, each GOA cell group includes 8 columns of GOA cells in cascade, wherein the connection points CP corresponding to the 3 rd, 4 th and 5 th GOA cells overlap with the diagonal DI, the connection points CP corresponding to the 1 st and 2 nd GOA cells are separated from the diagonal DI and symmetrically distributed about the diagonal DI, and the connection points CP corresponding to the 6 th and 7 th GOA cells are separated from the diagonal DI and symmetrically distributed about the diagonal DI.

In some of these embodiments, at least part of the second scan line V Gate includes a first portion 801 and a second portion 802 insulated from each other, wherein the first portion 801 is electrically connected to a corresponding GOA unit, and the second portion 802 is located at a side of the connection point CP away from the GOA unit group.

It can be understood that, in the column direction Y, each second scan line V Gate is disconnected at the connection point CP, where the first portion 801 is used to connect the GOA unit with the first scan line H Gate, and the second portion 802 is insulated from both the first portion 801 and the first scan line H Gate of the same second scan line V Gate. In implementation, the first portion 801 and the second portion 802 of the same second scan line V Gate are manufactured by a one-time patterning process, and the first portion 801 and the second portion 802 can form a space by adjusting the mask.

In some embodiments, there are at least two adjacent second scan lines V Gate, the lengths of the second portions 802 of which are not equal, which is understood to mean that the distances between the corresponding connection points CP of the two adjacent second scan lines V Gate and the DP side of the display substrate are not equal. By adjusting the lengths of the second portions 802 of the different second scan lines V Gate, it is possible to adjust the difference in signals output from the GOA units, which helps to improve the uniformity of the charging rate of the pixels of the display substrate.

In some embodiments, in the row direction X, the lengths of the second portions 802 of the second scan lines V Gate corresponding to the same GOA unit group sequentially change, which may be that the lengths sequentially increase or the lengths sequentially decrease. As shown in fig. 8, in one embodiment, the lengths of the second portions 802 of the second scan lines V Gate in each GOA unit group sequentially decrease in the row direction X, specifically, in the left-to-right direction. By adjusting the length of the second portion 802 of each second scan line V Gate to sequentially change, the difference of signals output by the GOA units can be adjusted, so as to reduce the influence of RC, and improve the uniformity of the charging rate of the pixels of the display substrate.

Illustratively, in the case where the lengths of the second portions 802 of the respective second scan lines V Gate sequentially vary, the difference in the lengths of the second portions 802 of the adjacent two second scan lines V Gate is smallest, and the difference in the lengths of the second portions 802 of the first and last second scan lines V Gate is largest.

The difference in length of the second portions 802 of two adjacent second scan lines V Gate is, for example, 1-9 sub-pixels in length. For example: differing by a length of 6 sub-pixels.

The difference in length of the second portions 802 of two adjacent second scan lines V Gate is, for example, 100um-2700um. Preferably, the second portions 802 of two adjacent second scan lines V Gate have a difference in length of 110-180um, or 120-170um, or 300-500, or 600-1200, or 1300-1800um.

The second scan line V Gate may be divided into a plurality of second portions, that is, the second scan line V Gate may be divided into at least 2 separate line segments, except for a portion connecting the GOA units. These individual line segments may be equal or unequal. For example: the second portion of the second scanning line V Gate is divided into 3 unequal segments which can be used for repairing repair lines for defective pixels. For example: the N (integer with N more than or equal to 1) Gate line has flaws or damages, and the adjacent N+P (integer with N more than or equal to 1) Gate line and Gate line are connected through the second part of the second scanning line V Gate.

In some embodiments, the sum of the lengths of the first portion 801 and the second portion 802 of each second scan line V Gate is approximately equal in the column direction Y, which is understood that the total lengths of each second scan line V Gate are equal, so as to improve the uniformity of the thickness of different areas of the display substrate, but the positions of the connection points CP corresponding to each second scan line V Gate are different, and accordingly, each second scan line V Gate is disconnected at different positions to form the first portion 801 and the second portion 802, and the lengths of the first portion 801 of each second scan line V Gate may not be equal.

In some embodiments, the second portion 802 of the second scan line V Gate may be used as a dummy electrode line to balance the thickness of different regions of the display substrate, and in other embodiments, the second portion 802 of the second scan line V Gate is used as a first common electrode line COM1, where the first common electrode line COM1 is electrically connected to a common signal source, so as to not only balance the thickness of different regions of the display substrate, but also provide a common signal.

As shown in fig. 9, in some embodiments, the display substrate further includes a second common electrode line COM2 extending in the row direction X, the second common electrode line COM2 including a third portion COM2-1 and a fourth portion COM2-2 separated from each other, and a spacer 901 is formed between the third portion COM2-1 and the fourth portion COM2-2 of the same second common electrode line COM 2.

The third portion COM2-1 and the fourth portion COM2-2 of the second common electrode line COM2 have a first orthographic projection on the substrate, the spacer 901 of the second common electrode line COM2 has a second orthographic projection on the substrate, and the first portion 801 of the second scan line V Gate has a third orthographic projection on the substrate.

Referring to fig. 9, of the two second common electrode lines COM2 shown in fig. 9, the upper one is the second common electrode line COM2 of the sub-pixel corresponding to the second scanning line V Gate labeled in the drawing, and the lower one is the second common electrode line COM2 of the sub-pixel not shown in the drawing. The upper one of the second common electrode lines COM2 is disposed to be disconnected at the second scan line V Gate, while the lower one of the second common electrode lines COM2 is still continuous at the overlapping position with the second scan line V Gate marked in the drawing. When viewed along the direction perpendicular to the display substrate, the corresponding second common electrode line COM2 and second scan line V Gate do not overlap, so that possible mutual interference between the second scan line V Gate and the second common electrode line COM2 can be reduced, which contributes to improvement of the display effect.

As shown in fig. 10, in some embodiments, the display substrate further includes a third electrode line extending along the column direction Y, where the third electrode line is used as a dummy electrode line, and the third electrode line may also be used as a common electrode line, and may be, for example, insulated from both the first scan line H Gate and the second scan line V Gate as the first common electrode line COM 1. The third electrode line can be manufactured with the first scanning line H Gate or the pixel electrode through a one-time composition process, so that the working procedure is saved, and the cost is saved.

In some embodiments, each GOA unit group includes a plurality of GOA unit groups, each GOA unit group includes a plurality of GOA units, the number of GOA units included in each GOA unit group is equal, each GOA unit group corresponds to a plurality of second electrode wires and at least one third electrode wire, the number of second electrode wires corresponding to each GOA unit group is equal, and the number of third electrode wires corresponding to each GOA unit group is equal.

As shown in fig. 10, in an exemplary embodiment, each GOA cell group includes 8 GOA cells, and the display substrate further includes a third electrode line corresponding to each GOA cell group, and correspondingly, includes 8 second scan lines V Gate and a third electrode line in one period.

In other embodiments, the number of third electrode lines in each ripple period may be set as desired, for example, 1-4 third electrode lines may be set in one ripple period, or 3-6 third electrode lines may be set in 2 ripple periods.

For example, two third electrode lines, eight second scan lines V Gate, and the like may be provided for one fluctuation period, and the number collocation thereof is not further limited and described herein. Here, the fluctuation period refers to a position fluctuation period of the connection point CP, and may be, for example, the clock period or half of the clock period mentioned above.

In some of these embodiments, the display substrate includes a plurality of pixels, each including a plurality of sub-pixels, which may include, illustratively, a red sub-pixel R, a blue sub-pixel B, and a green sub-pixel G, and in some of these embodiments, may include sub-pixels of other colors, such as a white sub-pixel. In each pixel unit, the number of sub-pixels with the same color can be one or more, and a certain display substrate includes one red sub-pixel R, one blue sub-pixel B and two green sub-pixels G.

It will be appreciated that in some embodiments, one or more of the third electrode line and the first common electrode line COM1 may be used for the touch electrode lead. For example: when the common electrode is multiplexed as a touch electrode, one or more of the third electrode line and the first common electrode line COM1 may be used for a touch electrode lead.

It will be appreciated that in some embodiments, one second scan line may be associated with each column of subpixels; alternatively, one or more pixels may correspond to one second scanning line in the row direction. For example: the red sub-pixel R, the blue sub-pixel B, and the green sub-pixel G correspond to one second scanning line.

In some embodiments, the third electrode line corresponds to a column of sub-pixels; or the third electrode line corresponds to one or more pixels. For example: the 3 pixel units correspond to a second scanning line.

In some embodiments, the first common electrode line COM1 corresponds to a column of sub-pixels; or the first common electrode line COM1 corresponds to one or more pixels. The red sub-pixel R, the blue sub-pixel B, and the green sub-pixel G correspond to one second scanning line.

In some of these embodiments, the subpixels of each pixel are arranged in the row direction X and the subpixels of the same color in the corresponding different pixels are arranged in the column direction Y.

As shown in fig. 11, the area corresponding to each sub-pixel is called a sub-pixel area 1101, and each sub-pixel area 1101 includes a color block area 11011 and a driving circuit area 11012 arranged along the column direction Y, it can be understood that the color block area 11011 corresponds to the light emitting area of the sub-pixel, and the driving circuit required by the sub-pixel is mainly distributed in the driving circuit area 11012 of the sub-pixel. For example, one or more thin film transistors or the like corresponding to the sub-pixel may be provided in the driving circuit region 11012.

As shown in fig. 9, in some embodiments, the display substrate further includes a first common electrode line COM1 disposed along the column direction Y, and it should be noted that the first common electrode line COM1 may be the second portion 802 of the second scan line V Gate, or may be a first common electrode line COM1 disposed independently.

The first common electrode line COM1 includes fifth portions 905 and sixth portions 906 alternately arranged in the column direction Y, the fifth portions 905 being located between two adjacent color resist regions 11011 in the row direction X, the sixth portions 906 being located between two adjacent driving circuit regions 11012 in the row direction X, and the size of the fifth portions 905 being larger than the size of the sixth portions 906 in the row direction X.

Referring to fig. 9, and referring to the relative positions of the color resist regions 11011 and the driving circuit regions 11012 shown in fig. 11, it is understood that the line width of the portion of the first common electrode line COM1 between the color resist regions 11011 of two adjacent sub-pixels in the row direction X is relatively wide, and the line width between the driving circuit regions 11012 of two adjacent sub-pixels in the row direction X is relatively narrow.

As shown in fig. 11, in some embodiments, the second scan line V Gate includes seventh portions 1107 and eighth portions 1108 alternately arranged along the column direction Y, the seventh portions 1107 being located between the color resist regions 11011 of two adjacent sub-pixels along the row direction X, the eighth portion 1108 being located between the adjacent two seventh portions 1107, the size of the seventh portions 1107 being greater than the size of the seventh portions 1107 along the row direction X.

Referring to fig. 11, it can be understood that the line width of the portion of the second scan line V Gate between two adjacent sub-pixels along the row direction X is relatively wide, and the line width of the portion of the second scan line V Gate between the driving circuit regions 11012 is relatively narrow.

In this embodiment, the two line width adjustment manners may be implemented separately or may be applied simultaneously. The purpose of adjusting the line width is to perform a light blocking function of the wiring between the color blocking regions 11011 of the sub-pixels, for example: when the display device is not provided with a Black Matrix (BM), a certain shielding effect is achieved; or when the display device has a black matrix, the black matrix can be matched to enhance light blocking. Therefore, the line width of the second scan line V Gate or the first common electrode line COM1 is increased between the adjacent color-blocking regions 11011, which can play a role in shielding light, prevent the occurrence of color cross of the sub-pixels with different colors, and facilitate the improvement of the display effect. While some traces along the row direction X may be included between the two driving circuit regions, for example, but not limited to, the second common electrode line COM2 may be included, by reducing the trace width of the first common electrode line COM1 and the second scan line V Gate between the driving circuit regions, the overlapping area of the first common electrode line COM1 and the second scan line V Gate with these lateral traces can be reduced, thereby helping to reduce RC and improving display effect. The overlapping area is understood to be the overlapping area of the orthographic projection of the tracks on the substrate.

Illustratively, in some embodiments, the line widths of the fifth portion 905 and the seventh portion 1107 may be controlled to be about 12.3 microns, while the line widths of the sixth portion 906 and the eighth portion 1108 may be controlled to be about 6.5 microns. In some embodiments, to further reduce the overlapping area with the lateral wires, the line width of the overlapping area with the lateral wires may be further reduced, for example, adjusted to about 5.5 micrometers, so that signal interference that may occur between the wires and other wires can be further reduced.

It is obvious that the above line width is only an exemplary arrangement in one embodiment, and the specific dimensions of the line width and the relative width may be set as required, which is not further defined and described herein.

As shown in fig. 11, in some embodiments, the display substrate further includes a plurality of Data lines Data extending along the column direction Y, at least two Data lines Data are included between two adjacent second scan lines V Gate, and the Data lines Data include a first segment Data1 extending along the column direction Y, a second segment Data2 extending along the column direction Y, and a bending segment Data3 connecting the first segment Data1 and the second segment Data 2.

In the row direction X, the first segment Data1 corresponds to the seventh portion 1107 of the adjacent Data line Data, the second segment Data2 corresponds to the eighth portion 1108 of the adjacent Data line Data, and the distance between the first segment Data1 and the seventh portion 1107 is equal to the distance between the second segment Data2 and the eighth portion 1108.

In this embodiment, the routing manner of the Data lines Data is also adjusted, so that the intervals between the second scan lines V Gate of the Data lines Data are kept relatively consistent.

Referring to fig. 11, it can be understood that the overall extending direction of the Data line Data is along the column direction Y, but the Data line Data does not extend along a straight line, but has a certain bend, and in the area where the line width of the second scan line V Gate changes, the Data line Data is provided with a bending segment Data3, so that the Data line Data extends in a direction away from the second scan line V Gate, and in the area where the line width of the second Data line Data remains unchanged, the Data line Data extends along a direction substantially parallel to the second Data line Data, so that in the area where the second Data line Data has different line widths, the distance between the Data line Data and the second scan line V Gate remains substantially uniform, thereby helping to improve the uniformity of parasitic capacitance between the second scan line V Gate and the Data line Data in the different areas, and helping to reduce the interference that the second scan line V Gate may generate on the Data signal.

With continued reference to fig. 11, in some embodiments, two Data lines Data adjacent to each second scan line V Gate are symmetrically disposed about the second scan line V Gate, which is helpful for further improving the uniformity of parasitic capacitance between the second scan line V Gate and the Data line Data in different areas, and for reducing possible interference of the second scan line V Gate on the Data signal.

In some embodiments, the first scan line H Gate and the second scan line V Gate are connected at a connection point CP through a Via hole Via penetrating through an insulating layer GI located between the first scan line H Gate and the second scan line V Gate in a direction perpendicular to the substrate. It will be appreciated that the location of the Via Via and the location of the connection point CP are coincident.

In some embodiments, in a cross section along the row direction X and perpendicular to the substrate in a region corresponding to the Via hole Via, a slope angle of the insulating layer is smaller than a slope angle of the first scan line hgate, and a width of the second scan line V Gate is larger than a width of the first scan line hgate.

As shown in fig. 12 to 13, fig. 12 is a schematic cross-sectional view showing the connection point of the substrate, it should be understood that the dimensions, angles, etc. in fig. 12 do not represent the actual size relationship of the structures, and fig. 12 is merely for illustrating the positional relationship of the structures.

As shown in fig. 13, fig. 13 is a cross-sectional view of the CP position of fig. 9 along a-a', where the second scan line V Gate and the first scan line H Gate are connected by a Via hole Via penetrating the insulating layer GI, and in one embodiment, the width of the second scan line V Gate is 12 micrometers, the width of the first scan line H Gate is 7 micrometers, the gradient angle a of the first scan line H Gate is 43 degrees, the gradient angle c of the second scan line V Gate is 35 degrees, the width of the Via hole Via is about 5 micrometers, and the gradient angle b of the insulating layer GI is about 30 degrees. Of course, the connection mode of the via/CP may also be adopted for the common electrode line of the same layer as the second scan line V Gate and the first scan line H Gate.

Here, the slope angle refers to an angle between a side surface away from the substrate and the substrate, and can be understood as an angle between an upper surface of each structure shown in fig. 12 and a horizontal direction.

In this embodiment, the gradient angle b of the insulating layer is smaller than the gradient angle a of the first scan line H Gate and the gradient angle c of the second scan line V Gate, and at the same time, the gradient angle a of the first scan line H Gate is smaller than the gradient angle c of the second scan line V Gate, so that the possibility that the first scan line H Gate or the second scan line V Gate is peeled off from the insulating layer GI can be reduced.

The width of the second scan line V Gate is about 4.07 microns, and the difference between the width of the second scan line V Gate and the width of the first scan line H Gate is about 5 microns, so that the second scan line V Gate can be completely covered by the first scan line H Gate, and the electrical connection effect can be ensured.

As shown in fig. 12, in some embodiments, the insulating layer GI includes a first sub-layer GI1 and a second sub-layer GI2 stacked in a direction away from the substrate, and the thickness ratio of the first sub-layer GI1 and the second sub-layer GI2 is 2.1 to 4.7. The purpose of setting the insulating layer GI to be two stacked sublayers is to increase the thickness of the insulating layer GI through two processes, and as can be known from a capacitance formula, the larger the distance between the electrode plates of the capacitor is, the smaller the capacitor is, therefore, increasing the thickness of the insulating layer GI can reduce the capacitance value generated between the first scan line H Gate and the second scan line V Gate, which is helpful for improving the interface characteristic of the thin film transistor, and simultaneously, is also helpful for reducing the possibility that the first scan line H Gate is damaged in the subsequent etching step.

As shown in fig. 14, in some embodiments, the second scan line V Gate is located between the adjacent columns of red sub-pixels R and blue sub-pixels B, and the distance between the second scan line V Gate and the red sub-pixels R is greater than the distance between the second scan line V Gate and the blue sub-pixels B.

It will be appreciated that at the interface between red subpixel R and blue subpixel B, via is more biased toward blue subpixel B, and in one embodiment, via is positioned at a location offset from the middle of red subpixel R and blue subpixel B by about 1.5 microns toward blue subpixel B, for example. It will be appreciated that the locations of the Via Via and the connection point CP are coincident, that is, the location of the connection point CP is biased toward the blue subpixel B.

As shown in fig. 14, in some embodiments, a portion of the Via hole Via overlaps a region corresponding to the red subpixel R, and a portion of the Via hole Via overlaps a region corresponding to the blue subpixel B, which helps to reduce the possibility of light leakage, thereby helping to improve the display effect.

As shown in fig. 14, in some embodiments, the distance between the Via hole Via and the color filter of the red subpixel R is smaller than the distance between the Via hole Via and the color filter of the blue subpixel B, so that the Via hole Via can avoid the spacer PS located near the driving circuit area of the blue subpixel B.

The circles at the pixel electrodes of the red and blue sub-pixels R and B in fig. 14 represent connection points of the second common electrode line COM2 and the pixel electrodes.

In some embodiments, the display substrate includes a plurality of spacers PS. It should be understood that the distribution position of the Via hole Via is not a straight line along the column direction Y, so that the relative positions of other positions are low, and if the periodic spacer PS is disposed, the spacer PS may not be effectively abutted against the display substrate and form a supporting effect, so that the spacer PS and the Via hole Via are controlled to avoid the design in the embodiment. Specifically, the distance between the orthographic projection of the spacer PS on the substrate and the orthographic projection of the connection point CP on the substrate is controlled to be not less than 1.2 times of the maximum width of the orthographic projection of the spacer PS on the substrate, so that the spacer PS can have a higher supporting effect, and the reliability of the display substrate is improved.

As shown in fig. 15, in some embodiments, the display substrate includes a plurality of groups of spacers PS arranged in an array, each group of spacers includes a main spacer M and a plurality of auxiliary spacers S, where the size of the main spacer M is greater than the size of the auxiliary spacers S.

Illustratively, as shown in fig. 15, in one embodiment, a spacer cycle includes a primary spacer M having a dimension of about 23 microns by 24 microns and 48 secondary spacers S having a dimension of about 20 microns by 19 microns.

In this embodiment, the front projection of the control connection point CP onto the substrate is separated from the front projection of the main spacer M onto the substrate, and the front projection of each connection point CP onto the substrate overlaps with the front projection of at most one sub spacer S onto the substrate. In one period, due to the limitation of the size and the distribution position, each connection point CP is controlled to be separated from the main spacer M, and the overlapping between the connection point CP and the auxiliary spacer S is reduced as much as possible.

As shown in fig. 15, the portion selected by the dashed frame may be understood as one spacer period, and the actual size of one spacer period corresponds to six rows of the first scan lines H Gate, and accordingly, the number and proportion of the connection points CP in one spacer period may be controlled. For example: in one spacer period, the number of the connecting points CP is more than or equal to 2 and less than or equal to 6; for example: the number of connection points CP is 4. Or the number ratio of the connecting point CP to the auxiliary spacer S is R1, and R1 is 1/20-1/8. Or the number ratio of the main spacers M to the connecting points CP is R2, and R1 is 1/6-1/4. In this way, the overlapping probability of the spacer PS and the connection point CP can be reduced, which is conducive to improving the supporting effect of the spacer PS, thereby improving the reliability of the display substrate. Here, overlapping means that there is overlapping in its orthographic projection on the substrate.

It is to be understood that the various embodiments of the application and features of the embodiments may be combined with each other without conflict. Moreover, the technical scheme of the embodiments of the application can be applied to different types of display substrates.

As shown in fig. 16, in an embodiment, the technical solution of the present application is applied to a display substrate with a dual-Gate line structure, where the display substrate with a dual-Gate line structure refers to two rows of pixels disposed between two adjacent Gate lines extending along a row direction X and arranged along a column direction Y, that is, two rows of pixels disposed between a k-1 row first scan line H Gate k-1 and a k-1 row first scan line H Gate k, where the two rows of pixels specifically include a first row of pixels where a sub-pixel P1 is located and a second row of pixels where a sub-pixel P2 is located.

In other embodiments, the technical solution of the embodiments of the present application may be applied to different types of display substrates such as ADS (advanced super-dimensional field Switching technology (Advanced Super Dimension Switch), IPS (In-Plane Switching) display panels, VA (vertical alignment vertical alignment) display panels, and the like, and may achieve the same or similar technical effects.

For example: as shown in fig. 17, the technical solution of the embodiment of the present application is also applied to an ADS display substrate, where the common electrode and the pixel electrode are not in the same layer; optionally, the common electrode and/or the pixel electrode are slit-shaped.

For example, in fig. 17, in one sub-pixel 1101, a first scanning line H Gate and a second scanning line VGate are connected through CP, a source of a transistor is connected to a data line data, a drain is connected to a pixel electrode pixel, which is different from a common electrode COM1 in layer, is plate-shaped, and the common electrode COM1 is slit-shaped, so that a plurality of sub-pixels 1101 can be covered; the adjacent data are overlapped by the common electrode COM1, so that a shielding effect is realized; the common electrode COM2 is connected to the common electrode line COM 2.

Of course, the pixel electrode may be slit-shaped, and the common electrode may be plate-shaped. The pixel electrode may be located at a side of the common electrode away from or close to the array substrate.

The technical scheme of the embodiment of the application can also be applied to IPS, as shown in FIG. 18, wherein the common electrode and the pixel electrode are arranged on the same layer. Alternatively, the common electrode and the pixel electrode are slit-shaped.

Alternatively, for example, in fig. 18, in a sub-pixel, the first scan line H Gate and the second scan line VGate are connected through CP, the source of the transistor is connected to the data line data, the drain is connected to the pixel electrode pixel, the pixel electrode pixel is in the same layer as the common electrode COM1, and the common electrode branch COM12 is arranged between adjacent data, so as to play a shielding role. The common electrode branch COM12 is in the same layer as the common electrode COM1, and the common electrode branch COM12 is connected to the common electrode line COM2 through the via hole CP 2.

The invention also provides electronic equipment, which comprises any display substrate.

Alternatively, the electronic device may be a liquid crystal display LCD or an organic light emitting display OLED or the like.

Because the display device of the present embodiment includes the technical solution of at least one embodiment of the display substrate, at least the above corresponding technical effects can be achieved, and details are not repeated here.

The foregoing is merely illustrative embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily think about variations or substitutions within the technical scope of the present invention, and the invention should be covered. Therefore, the protection scope of the invention is subject to the protection scope of the claims.

Claims

1. A display substrate comprising a substrate and, disposed on the substrate:

a plurality of second scanning lines sequentially arranged in a row direction;

Within at least one display sub-area, a distance H from a connection point of at least part of the first scanning line and the second scanning line to a diagonal line of the display sub-area is in a range of 0 to H;

where h=m2×sin (arctan (L1/M1)), L1 is the length of the display sub-region in the column direction, M1 is the width of the display sub-region in the row direction, M2 is the sum of the widths of N-1 columns of pixels in the row direction, and the value of N is equal to half the number of clock cycles of the gate driving circuit or the number of clock cycles of the gate driving circuit;

the display substrate further comprises a third electrode line extending along the column direction, wherein the third electrode line is used as one or more of a dummy electrode line and a first common electrode line, the third electrode line and the first scanning line are manufactured through a one-time composition process, and the third electrode line is insulated from the first scanning line and the second scanning line.

2. The display substrate according to claim 1, wherein h=m2×sin (arctan (L1/M1)), L1 is a length of the display sub-region in the column direction, M1 is a width of the display sub-region in the row direction, and M2 is a sum of widths of 3 to 5 columns of pixels in the row direction.

3. A display substrate according to claim 1 or 2, wherein the distance from the connection point of at least part of the first scanning lines and the second scanning lines to the diagonal line of the display sub-area is H, H being in the range of H/6 or more and H/2 or less.

4. The display substrate according to claim 1, wherein the angle between the diagonal and the row direction has a sine value of K, and the K value is 1.6 to 3.5.

5. The display substrate according to claim 1, wherein the angle between the diagonal and the row direction has a sine value of K, and the K value is 1.7 to 2.4.

6. A display substrate according to claim 4 or 5, characterized in that at least one display sub-area comprises a local position, the slope K2 of the connection point of the local position around the line of fluctuation;

the absolute value of the difference of K-K2 is in the range of 0.05-0.2.

7. A display substrate according to claim 4 or 5, characterized in that the display substrate comprises display sub-areas of the same size and the diagonals of the display sub-areas are parallel to each other.

8. A display substrate according to claim 4 or 5, characterized in that the number of display sub-areas is 4 to 6.

9. The display substrate according to claim 1, wherein at least part of the second scan lines include a first portion and a second portion insulated from each other, wherein the first portion is electrically connected to a corresponding gate driving circuit, and the second portion is located at a side of the connection point away from the gate driving circuit.

10. The display substrate according to claim 9, wherein at least two adjacent second scan lines are present, the lengths of the second portions of which are unequal, and the difference in lengths of the second portions of the adjacent two second scan lines is between 1 and 9 sub-pixels.

11. The display substrate according to claim 10, wherein a difference in length between second portions of two adjacent second scan lines is 110-180um; or 120-170um.

12. The display substrate according to claim 11, wherein a sum of lengths of a first portion and a second portion of at least two of the second scanning lines is equal in the column direction.

13. A display substrate according to any one of claims 9 to 12, wherein the second portion of the second scan line is for use as a first common electrode line, the first common electrode line being electrically connected to a common signal source.

14. The display substrate according to claim 1, wherein the display substrate includes a second common electrode line extending in the row direction, the second common electrode line including a third portion and a fourth portion separated from each other, a spacer being formed between the third portion and the fourth portion of the same second common electrode line;

15. The display substrate according to claim 1, wherein a distribution position of the connection points with respect to the diagonal line in the row direction varies periodically.

16. The display substrate according to claim 15, wherein a period of variation of distribution positions of the connection points is equal to a clock period of a gate driving circuit or equal to one half of the clock period of the gate driving circuit.

17. The display substrate according to claim 1 or 14, wherein a plurality of connection points corresponding to at least one of the gate driving circuits are symmetrically distributed about the diagonal line.

18. The display substrate according to claim 15, wherein in the case where J is an even number, a connection point corresponding to a J-th gate driving sub-circuit in the gate driving circuits cascaded with Q columns overlaps with the diagonal line;

19. The display substrate according to claim 15, wherein in the case where J is an even number, a connection point corresponding to a J-th gate driving sub-circuit in the gate driving circuits cascaded with Q columns is separated from the diagonal line;

20. The display substrate of claim 15, wherein each of the gate driving circuits includes 6 columns of gate driving sub-circuits in cascade, wherein connection points corresponding to 1 st and 6 th gate driving sub-circuits overlap the diagonal, connection points corresponding to 2 nd and 3 rd gate driving sub-circuits are separated from the diagonal and symmetrically distributed about the diagonal, and connection points corresponding to 4 th and 5 th gate driving sub-circuits are separated from the diagonal and symmetrically distributed about the diagonal.

21. The display substrate according to claim 15, wherein each of the gate driving circuits includes 7 columns of gate driving sub-circuits in cascade, wherein connection points corresponding to 3 rd, 4 th and 5 th gate driving sub-circuits overlap the diagonal line, connection points corresponding to 1 st and 2 nd gate driving sub-circuits are separated from the diagonal line and symmetrically distributed about the diagonal line, and connection points corresponding to 6 th and 7 th gate driving sub-circuits are separated from the diagonal line and symmetrically distributed about the diagonal line.

22. The display substrate of claim 20, wherein each of the gate driving circuits includes a plurality of gate driving sub-circuits, the gate driving circuits include equal numbers of gate driving sub-circuits, each of the gate driving circuits corresponds to a plurality of second electrode lines and at least one third electrode line, the gate driving circuits correspond to equal numbers of second electrode lines, and the gate driving circuits correspond to equal numbers of third electrode lines.

23. The display substrate according to claim 1, wherein the display substrate comprises a plurality of pixels, each pixel comprising a plurality of sub-pixels arranged in the row direction, each region corresponding to the sub-pixel comprising a color resist region and a driving circuit region arranged in the column direction, the first common electrode line comprising a fifth portion and a sixth portion alternately arranged in the column direction;

24. The display substrate according to claim 1, wherein the second scanning line includes seventh portions and eighth portions alternately arranged in the column direction, wherein the seventh portions are located between color resist regions of two sub-pixels adjacent in the row direction, and the eighth portions are located between the adjacent two seventh portions;

25. The display substrate of claim 24, further comprising a plurality of data lines extending along the column direction, at least two data lines being included between two adjacent second scan lines, the data lines including a first segment extending along the column direction, a second segment extending along the column direction, and a bending segment connecting the first segment and the second segment;

26. The display substrate according to claim 25, wherein two data lines adjacent to each of the second scan lines are symmetrically disposed with respect to the second scan lines.

27. The display substrate according to claim 1, wherein the first scanning line and the second scanning line are connected at the connection point by a via penetrating through an insulating layer located between the first scanning line and the second scanning line in a direction perpendicular to the substrate.

28. The display substrate according to claim 27, wherein in a cross section along the row direction and perpendicular to the substrate in a region corresponding to the via hole, a slope angle of the insulating layer is smaller than a slope angle of the first scan line, and a width of the second scan line is larger than a width of the first scan line.

29. The display substrate according to claim 27, wherein the insulating layer includes a first sub-layer and a second sub-layer stacked in a direction away from the substrate, and wherein a thickness ratio of the first sub-layer and the second sub-layer is 2.1 to 4.7.

30. The display substrate according to claim 1 or 27, wherein each pixel of the display substrate comprises a plurality of sub-pixels arranged in the row direction, each of the pixels comprising at least a red sub-pixel, a blue sub-pixel, and a green sub-pixel;

31. The display substrate according to claim 30, wherein the first scan line and the second scan line overlap a region corresponding to the red sub-pixel in a case where the connection point is connected by a via hole, and the via hole overlaps a region corresponding to the blue sub-pixel.

32. The display substrate of claim 31, wherein a distance between the via and the color filter of the red subpixel is less than a distance between the via and the color filter of the blue subpixel.

33. The display substrate of claim 1, wherein the display substrate comprises a plurality of spacers, a distance between an orthographic projection of the spacers on the substrate and an orthographic projection of the connection point on the substrate is not less than 1.2 times a maximum width of the orthographic projection of the spacers on the substrate.

34. The display substrate according to claim 1, wherein the display substrate comprises a plurality of groups of spacers arranged in an array, each group of spacers comprising a main spacer and a plurality of auxiliary spacers, wherein the size of the main spacer is larger than the size of the auxiliary spacers;

35. The display substrate of claim 1, further comprising a plurality of primary spacers and a plurality of secondary spacers, wherein a number of connection points of the first scan line and the second scan line is greater than or equal to 2 and less than or equal to 6 in one spacer cycle.

36. The display substrate according to claim 1, further comprising a plurality of main spacers and a plurality of sub spacers, wherein in one spacer cycle, the ratio of the number of the connection points to the number of the sub spacers is R1, and R1 is 1/20 to 1/8.

37. The display substrate of claim 1, further comprising a plurality of primary spacers and a plurality of secondary spacers, wherein the ratio of the number of primary spacers to the number of connection points in a spacer cycle is R2 and R1 is 1/6 to 1/4.

38. The display substrate according to claim 1, wherein two rows of pixels are provided between the first scanning line corresponding to the kth-1 row and the first scanning line corresponding to the kth row, and k is an integer of 2 or more.

39. The display substrate of claim 1, wherein: and a common electrode and a pixel electrode, wherein the common electrode and/or the pixel electrode are slit-shaped.

40. The display substrate of claim 2, wherein H ranges from 800 to 1800 microns; or 1200-1500 microns.

41. A display substrate according to claim 3, wherein the h range of the connection point of at least part of the first scan line and the second scan line is 180 to 500 μm.

42. An electronic device comprising the display substrate of any one of claims 1 to 41.